[LLVMdev] Problems with 64-bit register operands of inline asm on ARM

[Weiming Zhao]

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-----Original Message-----
From: Måns Rullgård [mailto:mans at mansr.com] 
Sent: Wednesday, March 27, 2013 6:41 PM
To: weimingz at codeaurora.org
Cc: 'Måns Rullgård'; 'Jim Grosbach'; 'Renato Golin'; 'Kristof Beyls'; 'Eric Christopher'; 'Jakob Stoklund Olesen'; 'LLVM Commits'
Subject: Re: [LLVMdev] Problems with 64-bit register operands of inline asm on ARM

"Weiming Zhao" <weimingz at codeaurora.org> writes:

> Hi Måns,
>
> If you try my patch, it supports "ldrd %0, [%1]" although my test case 
> doesn't include that.
>
> The current logic is, for inline asm, LLVM just emits one reg for %x 
> place holders.
> For a GPRPair, when it sees %0, it emits the first sub reg.
> When it sees %H0, it emits the second sub reg.

That matches the gcc behaviour and is what people would expect.

> On the other side, it's hard for LLVM to give a warning diagnose for 
> your test because LLVM doesn’t even parse the instruction string 
> inside the inline asm.

It currently fails if using the integrated assembler.  When using gas it obviously works exactly as with gcc.

[Weiming] Exactly. But if we decide to fix it, it should be fixed by integrated assembler. From inline asm part, we can't simply expand %0 to (Rt, Rt+1) because it will break other cases (ldrexd/strexd) as I mentioned before. It is also hard to specialize for ldrd/strd cse because we don't parse the inline asm string.

Thanks,
Weiming
--
Måns Rullgård
mans at mansr.com