[LLVMdev] Problems with 64-bit register operands of inline asm on ARM

[Måns Rullgård]

"Weiming Zhao" <weimingz at codeaurora.org> writes:

> Hi Måns,
>
> If you try my patch, it supports "ldrd %0, [%1]" although my test case
> doesn't include that.
>
> The current logic is, for inline asm, LLVM just emits one reg for %x place
> holders. 
> For a GPRPair, when it sees %0, it emits the first sub reg.
> When it sees %H0, it emits the second sub reg.

That matches the gcc behaviour and is what people would expect.

> On the other side, it's hard for LLVM to give a warning diagnose for your
> test because LLVM doesn’t even parse the instruction string inside the
> inline asm.

It currently fails if using the integrated assembler.  When using gas it
obviously works exactly as with gcc.

-- 
Måns Rullgård
mans at mansr.com