[PATCH] x86_64: designate most general purpose and SSE registers as callee save under coldcc

[Jakob Stoklund Olesen]

On Feb 20, 2013, at 2:10 PM, Peter Collingbourne <peter at pcc.me.uk> wrote:

> +def CSR_MostRegs_64 : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10,
> +                                           R11, R12, R13, R14, R15, RBP,
> +                                           (sequence "XMM%u", 0, 15))>;

Nice.

>     ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
>     oclBiCall = (F ? F->getCallingConv() == CallingConv::Intel_OCL_BI : false);
>     hipeCall = (F ? F->getCallingConv() == CallingConv::HiPE : false);
> +    coldCall = (F ? F->getCallingConv() == CallingConv::Cold : false);

Argh, this pattern stopped working two calling conventions ago.

Please rewrite this to use a switch (or something else sane).

> +++ test/CodeGen/X86/coldcc64.ll
> +  %b = add i64 %a, %a
…
> +  %z1 = add i64 %y, %y1
> +  ret i64 %z1
> +}

This dag of adds looks like it may get optimized one day, causing your test to fail.

You could use inline asm to clobber specific registers in the function instead, see for example test/CodeGen/Thumb2/aligned-spill.ll

Also, please add tests for XMM register spilling as well.

Otherwise looks good!

/jakob