[llvm-commits] Fix 64-bit atomic operations in Thumb mode

[Tim Northover]

Hi all,

Currently, 64-bit atomic operations cause an internal fault when used in Thumb 
mode on the ARM backend. This is because the LDREXD and STREXD show an unusual 
difference between ARM and Thumb encodings. On ARM two consecutive registers 
are required, but on Thumb the registers can be arbitrary.

As a result LLVM's instructions take different operands, which the current 
code doesn't handle.

The attached patch should fix this, as well as cleaning up the function 
slightly (before, pairs were formed in multiple places but I think this only 
has to happen at the operations that require it).

One detail I'm unsure of is the comment about constraining thumb register 
allocation. As far as I can see this is taken care of automatically since both 
registers in the LDREXD are live. Am I missing something?

Ok to commit?

Cheers.

Tim.
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