[llvm-commits] Fix 64-bit atomic operations in Thumb mode

[Jakob Stoklund Olesen]

On Jan 28, 2013, at 6:25 AM, Tim Northover <Tim.Northover at arm.com> wrote:

> Hi all,
> 
> Currently, 64-bit atomic operations cause an internal fault when used in Thumb 
> mode on the ARM backend. This is because the LDREXD and STREXD show an unusual 
> difference between ARM and Thumb encodings. On ARM two consecutive registers 
> are required, but on Thumb the registers can be arbitrary.
> 
> As a result LLVM's instructions take different operands, which the current 
> code doesn't handle.
> 
> The attached patch should fix this, as well as cleaning up the function 
> slightly (before, pairs were formed in multiple places but I think this only 
> has to happen at the operations that require it).
> 
> One detail I'm unsure of is the comment about constraining thumb register 
> allocation. As far as I can see this is taken care of automatically since both 
> registers in the LDREXD are live. Am I missing something?

You are not. The register allocator will never use the same register for two outputs on an instruction, even when both are dead.

> Ok to commit?

Looks good.

Thanks,
/jakob