[llvm-commits] [PATCH] Fix spill/reload code for PowerPC vector registers

[Jakob Stoklund Olesen]

On Oct 10, 2012, at 10:44 AM, William J. Schmidt <wschmidt at linux.vnet.ibm.com> wrote:

> I recently ran across a bug in the PowerPC target code.  When generating
> spill and reload code for vector registers, the compiler makes use of
> GPR0.  However, there are two flavors of GPR0 defined by the target:
> the 32-bit GPR0 (R0) and the 64-bit GPR0 (X0).  The spill/reload code
> makes use of R0 regardless of whether we are generating 32- or 64-bit
> code.

Hi Bill,

You should add -verify-machineinstrs to tests like this. The machine code verifier is usually able to point out these problems.

Otherwise, the patch looks good.

/jakob