[llvm-commits] [PATCH] Fix spill/reload code for PowerPC vector registers

[William J. Schmidt]

I recently ran across a bug in the PowerPC target code.  When generating
spill and reload code for vector registers, the compiler makes use of
GPR0.  However, there are two flavors of GPR0 defined by the target:
the 32-bit GPR0 (R0) and the 64-bit GPR0 (X0).  The spill/reload code
makes use of R0 regardless of whether we are generating 32- or 64-bit
code.

The attached patch fixes this oversight.  It has been tested with no new
regressions.  The included test case is dependent on my previous patch
for removing VRSAVE handling, since it exhibits the dangling-use bug
described there.  Ok to commit once the previous patch is committed?

Thanks,
Bill
-- 
Bill Schmidt, Ph.D.
IBM Advance Toolchain for PowerLinux
IBM Linux Technology Center
wschmidt at us.ibm.com
wschmidt at linux.vnet.ibm.com





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