[llvm-commits] [PATCH] 32-bit right shifts are being ignored by the ARM assembler for some instructions

[Richard Barton]

Hello reviewers

The ARM assembler was ignoring 32-bit right shifts on AND,SUB,EOR,ADD,ORR and
BIC ARM instructions. 

These instructions are special cased in the AsmParser so that redundant shifts
by 0 can be removed. MC stores right shifts by #32 as #0 in the MCInst, so this
case needs to be accounted for in the AsmParser.

Patch and updated regression tests attached.

Regards,

Richard Barton
ARM Ltd, Cambridge

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