[llvm-commits] [PATCH] 32-bit right shifts are being ignored by the ARM assembler for some instructions

[Jim Grosbach]

Hi Richard,

This looks great.

Same trivial tweak as before regarding using r0 in the test cases. Good for commit w/ that fix.

-Jim

On Jul 4, 2012, at 11:51 AM, Richard Barton <richard.barton at arm.com> wrote:

> Hello reviewers
> 
> The ARM assembler was ignoring 32-bit right shifts on AND,SUB,EOR,ADD,ORR and
> BIC ARM instructions. 
> 
> These instructions are special cased in the AsmParser so that redundant shifts
> by 0 can be removed. MC stores right shifts by #32 as #0 in the MCInst, so this
> case needs to be accounted for in the AsmParser.
> 
> Patch and updated regression tests attached.
> 
> Regards,
> 
> Richard Barton
> ARM Ltd, Cambridge
> 
> <shift_by_32_arm_assembly.patch>