[llvm-commits] [PATCH 1/4] (REVIEW REQUEST) Mips Inline asm 16 bit register allowed for GPR constraints

[Jack Carter]

When using inline asm constraints representing
non-floating point general registers we were now
allowing for 16 bit elements (shorts). This needed
to be added so wecould test some of the other constraints
that represent 16 bit elements.

The test for this will appear in the Constraint_I patch in
this patch series.

     short s_input = 7;
     short s_result = 0;
     short s_val = -3;

/*
        I - A signed 16 bit constant
 */
     __asm__ __volatile__(
           "addi %0,%1,%2\n\t "
	     : "=r" (s_result)
	     : "r" (s_input), "I" (s_val));

Without this patch "=r"(s_result) would produce an erroneous error.
---
 lib/Target/Mips/MipsISelLowering.cpp       |    2 +-
 test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll |   24 ++++++++++++++++++++++++
 2 files changed, 25 insertions(+), 1 deletions(-)
 create mode 100644 test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll
-------------- next part --------------
diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp
index 9cba688..7af6b16 100644
--- a/lib/Target/Mips/MipsISelLowering.cpp
+++ b/lib/Target/Mips/MipsISelLowering.cpp
@@ -2941,7 +2941,7 @@ getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
     case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
     case 'y': // Same as 'r'. Exists for compatibility.
     case 'r':
-      if (VT == MVT::i32)
+      if (VT == MVT::i32 || VT == MVT::i16)
         return std::make_pair(0U, Mips::CPURegsRegisterClass);
       assert(VT == MVT::i64 && "Unexpected type.");
       return std::make_pair(0U, Mips::CPU64RegsRegisterClass);
diff --git a/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll b/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll
new file mode 100644
index 0000000..42fd748
--- /dev/null
+++ b/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll
@@ -0,0 +1,24 @@
+;
+;Register constrain "r" should take both ints and shorts.
+;
+;
+; RUN: llc -march=mipsel < %s 
+
+
+ at .str = private unnamed_addr constant [22 x i8] c"mips_add(%d,%d) = %d\0A\00", align 1
+
+define i32 @main() nounwind {
+entry:
+;CHECK:	#APP
+;CHECK:	add $2,$16,$17
+;CHECK:	#NO_APP
+  %0 = tail call i16 asm "add $0,$1,$2", "=r,r,r,0"(i16 7, i16 8, i16 0) nounwind, !srcloc !0
+;CHECK:	#APP
+;CHECK:	add $18,$16,$17
+;CHECK:	#NO_APP
+  %1 = tail call i32 asm "add $0,$1,$2", "=r,r,r,0"(i32 7, i32 8, i32 0) nounwind, !srcloc !1
+  ret i32 0
+}
+
+!0 = metadata !{i32 127}
+!1 = metadata !{i32 374}