[llvm-commits] [PATCH 0/4] Mips patch Series short description

[Jack Carter]

The following series implements 3 of the Mips specific inline asm
operand constraints. They need to applied in order as the test case
is incrementally added to.

---

Jack Carter (4):
      (REVIEW REQUEST) Mips Inline asm 16 bit register allowed for GPR constraints
      (REVIEW REQUEST)  Mips specific inline asm constraint 'I'
      (REVIEW REQUEST) Mips specific inline asm constraint 'J'
      (REVIEW REQUEST) Mips specific constraint 'K':


 lib/Target/Mips/MipsISelLowering.cpp           |   76 ++++++++++++++++++++++++
 lib/Target/Mips/MipsISelLowering.h             |    9 +++
 test/CodeGen/Mips/inlineasm-cnstrnt-bad-I-1.ll |   19 ++++++
 test/CodeGen/Mips/inlineasm-cnstrnt-bad-J.ll   |   21 +++++++
 test/CodeGen/Mips/inlineasm-cnstrnt-bad-K.ll   |   16 +++++
 test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll     |   24 ++++++++
 test/CodeGen/Mips/inlineasm_constraint.ll      |   36 +++++++++++
 7 files changed, 200 insertions(+), 1 deletions(-)
 create mode 100644 test/CodeGen/Mips/inlineasm-cnstrnt-bad-I-1.ll
 create mode 100644 test/CodeGen/Mips/inlineasm-cnstrnt-bad-J.ll
 create mode 100644 test/CodeGen/Mips/inlineasm-cnstrnt-bad-K.ll
 create mode 100644 test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll
 create mode 100644 test/CodeGen/Mips/inlineasm_constraint.ll

-- 
Cheers,

Jack