[llvm-commits] [llvm] r142152 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ test/CodeGen/ARM/ test/CodeGen/CellSPU/ test/CodeGen/X86/

[Owen Anderson]

On Oct 17, 2011, at 10:29 AM, Owen Anderson wrote:

> Nadav,
> 
> 
> On Oct 16, 2011, at 1:31 PM, Nadav Rotem wrote:
> 
>> Author: nadav
>> Date: Sun Oct 16 15:31:33 2011
>> New Revision: 142152
> 
> …
> 
>> Modified: llvm/trunk/test/CodeGen/ARM/vrev.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vrev.ll?rev=142152&r1=142151&r2=142152&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/ARM/vrev.ll (original)
>> +++ llvm/trunk/test/CodeGen/ARM/vrev.ll Sun Oct 16 15:31:33 2011
>> @@ -150,9 +150,6 @@
>> 
>> ; vrev <4 x i16> should use VREV32 and not VREV64
>> define void @test_vrev64(<4 x i16>* nocapture %source, <2 x i16>* nocapture %dst) nounwind ssp {
>> -; CHECK: test_vrev64:
>> -; CHECK: vext.16
>> -; CHECK: vrev32.16
>> entry:
>>  %0 = bitcast <4 x i16>* %source to <8 x i16>*
>>  %tmp2 = load <8 x i16>* %0, align 4
> 
> You've removed all the CHECK lines from this test, essentially disabling it.  Please make sure it still works and add back correct CHECK lines.

To follow up on my own post, it does not still work.  The new generated code is MUCH worse than what is being checked for, involve extra stores rather than a shuffle instruction.  Please fix this or re-disable this patch until it can be fixed.

--Owen
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