[llvm-commits] [llvm] r141500 - /llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp

[Jakob Stoklund Olesen]

On Oct 8, 2011, at 10:19 PM, Cameron Zwarich wrote:

> On Oct 8, 2011, at 7:21 PM, Jakob Stoklund Olesen wrote:
> 
>> On Oct 8, 2011, at 2:25 PM, Cameron Zwarich wrote:
>> 
>>> Could this sort of thing be checked statically?
>> 
>> I wish.
>> 
>> The 20 x86 8-bit registers are crazy. 12 can only be accessed with an REX prefix, and the 4 H-regs can only be accessed without a prefix.
>> 
>> Ideally, GR8_NOREX shouldn't be a sub-class of GR8, and this wouldn't be as big a problem. Unfortunately, GR8 is identical to GR8_NOREX in 32-bit mode, so TableGen considers it a super-class.
>> 
>> We could create separate GR8 register classes for 32-bit and 64-bit modes, but that would require duplicating instruction definitions as well.
> 
> 
> Sounds like a good idea. We could add some metaprogramming features to Tablegen to reduce the burden of duplicating all of the instruction definitions...

I think we can avoid the need for hygienic macros by supporting recursive multiclasses. For example:

int O,o,i;char*I="";main(l){O&=l&1?*I:~*I,*I++||(l=2*getchar(),i+=O>8
?o:O?0:o+1,o=O>9,O=-1,I="t8B~pq`",l>0)?main(l/2):printf("%d\n",--i);}

/jakob

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