[llvm-commits] [llvm] r139004 - in /llvm/trunk: lib/Target/CellSPU/SPUInstrInfo.td test/CodeGen/CellSPU/or_ops.ll

[Kalle Raiskila]

Author: kraiskil
Date: Fri Sep  2 05:05:01 2011
New Revision: 139004

URL: http://llvm.org/viewvc/llvm-project?rev=139004&view=rev
Log:
Pass signed (not unsigned) 10 bit field to SPU 'ori' instruction.

Modified:
    llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td
    llvm/trunk/test/CodeGen/CellSPU/or_ops.ll

Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td?rev=139004&r1=139003&r2=139004&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td Fri Sep  2 05:05:01 2011
@@ -1594,8 +1594,8 @@
 {
   def v4i32: ORIVecInst<v4i32, v4i32Uns10Imm>;
 
-  def r32: ORIInst<(outs R32C:$rT), (ins R32C:$rA, u10imm_i32:$val),
-                   [(set R32C:$rT, (or R32C:$rA, i32ImmUns10:$val))]>;
+  def r32: ORIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
+                   [(set R32C:$rT, (or R32C:$rA, i32ImmSExt10:$val))]>;
 
   // i16i32: hacked version of the ori instruction to extend 16-bit quantities
   // to 32-bit quantities. used exclusively to match "anyext" conversions (vide

Modified: llvm/trunk/test/CodeGen/CellSPU/or_ops.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/or_ops.ll?rev=139004&r1=139003&r2=139004&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/or_ops.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/or_ops.ll Fri Sep  2 05:05:01 2011
@@ -1,9 +1,11 @@
 ; RUN: llc < %s -march=cellspu > %t1.s
 ; RUN: grep and    %t1.s | count 2
 ; RUN: grep orc    %t1.s | count 85
-; RUN: grep ori    %t1.s | count 30
+; RUN: grep ori    %t1.s | count 34
 ; RUN: grep orhi   %t1.s | count 30
 ; RUN: grep orbi   %t1.s | count 15
+; RUN: FileCheck %s < %t1.s
+
 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
 target triple = "spu"
 
@@ -210,6 +212,15 @@
         ret i32 %tmp38
 }
 
+define i32 @ori_i32_600(i32 %in) {
+	;600 does not fit into 'ori' immediate field
+	;CHECK: ori_i32_600
+	;CHECK: il
+	;CHECK: ori
+	%tmp = or i32 %in, 600
+	ret i32 %tmp
+}
+
 ; ORHI instruction generation (i16 data type):
 define <8 x i16> @orhi_v8i16_1(<8 x i16> %in) {
         %tmp2 = or <8 x i16> %in, < i16 511, i16 511, i16 511, i16 511,