[llvm-commits] [llvm] r138948 - in /llvm/trunk: lib/MC/MCDisassembler/Disassembler.cpp lib/MC/MCDisassembler/EDDisassembler.cpp lib/Target/ARM/Disassembler/ARMDisassembler.cpp utils/TableGen/DisassemblerEmitter.cpp
Nick Lewycky
nlewycky at google.com
Thu Sep 1 11:44:30 PDT 2011
Hi! I think your patch caused these build failures with newer gcc's:
llvm/lib/MC/MCDisassembler/EDDisassembler.cpp:265: error: control reaches
end of non-void function [-Wreturn-type]
llvm/lib/MC/MCDisassembler/Disassembler.cpp:159: error: control reaches end
of non-void function [-Wreturn-type]
Could you please take a look?
Nick
On 1 September 2011 11:02, James Molloy <james.molloy at arm.com> wrote:
> Author: jamesm
> Date: Thu Sep 1 13:02:14 2011
> New Revision: 138948
>
> URL: http://llvm.org/viewvc/llvm-project?rev=138948&view=rev
> Log:
> Fix up r137380 based on post-commit review by Jim Grosbach.
>
> Modified:
> llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp
> llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp
> llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
> llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp
>
> Modified: llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp?rev=138948&r1=138947&r2=138948&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp (original)
> +++ llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp Thu Sep 1 13:02:14
> 2011
> @@ -135,18 +135,25 @@
> MCInst Inst;
> const MCDisassembler *DisAsm = DC->getDisAsm();
> MCInstPrinter *IP = DC->getIP();
> - if (!DisAsm->getInstruction(Inst, Size, MemoryObject, PC, /*REMOVE*/
> nulls()))
> + MCDisassembler::DecodeStatus S;
> + S = DisAsm->getInstruction(Inst, Size, MemoryObject, PC, /*REMOVE*/
> nulls());
> + switch (S) {
> + case MCDisassembler::Fail:
> + case MCDisassembler::SoftFail:
> + // FIXME: Do something different for soft failure modes?
> return 0;
> + case MCDisassembler::Success: {
> + SmallVector<char, 64> InsnStr;
> + raw_svector_ostream OS(InsnStr);
> + IP->printInst(&Inst, OS);
> + OS.flush();
>
> - SmallVector<char, 64> InsnStr;
> - raw_svector_ostream OS(InsnStr);
> - IP->printInst(&Inst, OS);
> - OS.flush();
> + assert(OutStringSize != 0 && "Output buffer cannot be zero size");
> + size_t OutputSize = std::min(OutStringSize-1, InsnStr.size());
> + std::memcpy(OutString, InsnStr.data(), OutputSize);
> + OutString[OutputSize] = '\0'; // Terminate string.
>
> - assert(OutStringSize != 0 && "Output buffer cannot be zero size");
> - size_t OutputSize = std::min(OutStringSize-1, InsnStr.size());
> - std::memcpy(OutString, InsnStr.data(), OutputSize);
> - OutString[OutputSize] = '\0'; // Terminate string.
> -
> - return Size;
> + return Size;
> + }
> + }
> }
>
> Modified: llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp?rev=138948&r1=138947&r2=138948&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp (original)
> +++ llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp Thu Sep 1 13:02:14
> 2011
> @@ -239,14 +239,19 @@
> MCInst* inst = new MCInst;
> uint64_t byteSize;
>
> - if (!Disassembler->getInstruction(*inst,
> - byteSize,
> - memoryObject,
> - address,
> - ErrorStream)) {
> + MCDisassembler::DecodeStatus S;
> + S = Disassembler->getInstruction(*inst,
> + byteSize,
> + memoryObject,
> + address,
> + ErrorStream);
> + switch (S) {
> + case MCDisassembler::Fail:
> + case MCDisassembler::SoftFail:
> + // FIXME: Do something different on soft failure mode?
> delete inst;
> return NULL;
> - } else {
> + case MCDisassembler::Success: {
> const llvm::EDInstInfo *thisInstInfo = NULL;
>
> if (InstInfos) {
> @@ -256,6 +261,7 @@
> EDInst* sdInst = new EDInst(inst, byteSize, *this, thisInstInfo);
> return sdInst;
> }
> + }
> }
>
> void EDDisassembler::initMaps(const MCRegisterInfo ®isterInfo) {
>
> Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=138948&r1=138947&r2=138948&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Thu Sep 1
> 13:02:14 2011
> @@ -24,221 +24,223 @@
> #include "llvm/Support/TargetRegistry.h"
> #include "llvm/Support/raw_ostream.h"
>
> -// Pull DecodeStatus and its enum values into the global namespace.
> -typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;
> -#define Success llvm::MCDisassembler::Success
> -#define Unpredictable llvm::MCDisassembler::SoftFail
> -#define Fail llvm::MCDisassembler::Fail
> -
> -// Helper macro to perform setwise reduction of the current running status
> -// and another status, and return if the new status is Fail.
> -#define CHECK(S,X) do { \
> - S = (DecodeStatus) ((int)S & (X)); \
> - if (S == Fail) return Fail; \
> - } while(0)
> +using namespace llvm;
> +
> +static bool Check(MCDisassembler::DecodeStatus &Out,
> MCDisassembler::DecodeStatus In) {
> + switch (In) {
> + case MCDisassembler::Success:
> + // Out stays the same.
> + return true;
> + case MCDisassembler::SoftFail:
> + Out = In;
> + return true;
> + case MCDisassembler::Fail:
> + Out = In;
> + return false;
> + }
> + return false;
> +}
>
> // Forward declare these because the autogenerated code will reference
> them.
> // Definitions are further down.
> -static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned
> RegNo,
> +static MCDisassembler::DecodeStatus DecodeGPRRegisterClass(llvm::MCInst
> &Inst, unsigned RegNo,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
> +static MCDisassembler::DecodeStatus
> DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
> unsigned RegNo, uint64_t
> Address,
> const void *Decoder);
> -static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned
> RegNo,
> +static MCDisassembler::DecodeStatus DecodetGPRRegisterClass(llvm::MCInst
> &Inst, unsigned RegNo,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned
> RegNo,
> +static MCDisassembler::DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst
> &Inst, unsigned RegNo,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned
> RegNo,
> +static MCDisassembler::DecodeStatus DecoderGPRRegisterClass(llvm::MCInst
> &Inst, unsigned RegNo,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned
> RegNo,
> +static MCDisassembler::DecodeStatus DecodeSPRRegisterClass(llvm::MCInst
> &Inst, unsigned RegNo,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned
> RegNo,
> +static MCDisassembler::DecodeStatus DecodeDPRRegisterClass(llvm::MCInst
> &Inst, unsigned RegNo,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned
> RegNo,
> +static MCDisassembler::DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst
> &Inst, unsigned RegNo,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
> +static MCDisassembler::DecodeStatus
> DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
> unsigned RegNo,
> uint64_t Address,
> const void *Decoder);
> -static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned
> RegNo,
> +static MCDisassembler::DecodeStatus DecodeQPRRegisterClass(llvm::MCInst
> &Inst, unsigned RegNo,
> uint64_t Address, const void *Decoder);
>
> -static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodePredicateOperand(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
> +static MCDisassembler::DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst,
> unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
> +static MCDisassembler::DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst,
> unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
> +static MCDisassembler::DecodeStatus DecodeRegListOperand(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeSPRRegListOperand(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeDPRRegListOperand(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
>
> -static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned
> Insn,
> +static MCDisassembler::DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst
> &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned
> Insn,
> +static MCDisassembler::DecodeStatus DecodeCopMemInstruction(llvm::MCInst
> &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
> +static MCDisassembler::DecodeStatus
> DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
> unsigned Insn,
> uint64_t Address,
> const void *Decoder);
> -static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned
> Insn,
> +static MCDisassembler::DecodeStatus DecodeSORegMemOperand(llvm::MCInst
> &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned
> Insn,
> +static MCDisassembler::DecodeStatus
> DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned
> Insn,
> +static MCDisassembler::DecodeStatus DecodeSORegImmOperand(llvm::MCInst
> &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned
> Insn,
> +static MCDisassembler::DecodeStatus DecodeSORegRegOperand(llvm::MCInst
> &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
>
> -static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &
> Inst,
> +static MCDisassembler::DecodeStatus
> DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
> unsigned Insn,
> uint64_t Adddress,
> const void *Decoder);
> -static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned
> Insn,
> +static MCDisassembler::DecodeStatus DecodeSMLAInstruction(llvm::MCInst
> &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned
> Insn,
> +static MCDisassembler::DecodeStatus DecodeCPSInstruction(llvm::MCInst
> &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned
> Insn,
> +static MCDisassembler::DecodeStatus DecodeT2CPSInstruction(llvm::MCInst
> &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst,
> unsigned Val,
> +static MCDisassembler::DecodeStatus
> DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeAddrMode5Operand(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeAddrMode7Operand(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned
> Insn,
> +static MCDisassembler::DecodeStatus
> DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
> +static MCDisassembler::DecodeStatus DecodeVCVTImmOperand(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeAddrMode6Operand(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
> +static MCDisassembler::DecodeStatus DecodeVLDInstruction(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
> +static MCDisassembler::DecodeStatus DecodeVSTInstruction(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst
> &Inst,unsigned Val,
> +static MCDisassembler::DecodeStatus
> DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
> +static MCDisassembler::DecodeStatus DecodeShiftRight8Imm(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeShiftRight16Imm(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeShiftRight32Imm(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeShiftRight64Imm(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned
> Insn,
> +static MCDisassembler::DecodeStatus DecodeTBLInstruction(llvm::MCInst
> &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
> +static MCDisassembler::DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst,
> unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
> +static MCDisassembler::DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst,
> unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
> +static MCDisassembler::DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst,
> unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned
> Insn,
> +static MCDisassembler::DecodeStatus DecodeMemBarrierOption(llvm::MCInst
> &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
> +static MCDisassembler::DecodeStatus DecodeMSRMask(llvm::MCInst &Inst,
> unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
> +static MCDisassembler::DecodeStatus DecodeDoubleRegLoad(llvm::MCInst
> &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned
> Insn,
> +static MCDisassembler::DecodeStatus DecodeDoubleRegStore(llvm::MCInst
> &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
> +static MCDisassembler::DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst,
> unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
> +static MCDisassembler::DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst,
> unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
> +static MCDisassembler::DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst,
> unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
> +static MCDisassembler::DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst,
> unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
> +static MCDisassembler::DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst,
> unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
> +static MCDisassembler::DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst,
> unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
> +static MCDisassembler::DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst,
> unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
> +static MCDisassembler::DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst,
> unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
> +static MCDisassembler::DecodeStatus DecodeVST1LN(llvm::MCInst &Inst,
> unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
> +static MCDisassembler::DecodeStatus DecodeVST2LN(llvm::MCInst &Inst,
> unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
> +static MCDisassembler::DecodeStatus DecodeVST3LN(llvm::MCInst &Inst,
> unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
> +static MCDisassembler::DecodeStatus DecodeVST4LN(llvm::MCInst &Inst,
> unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
> +static MCDisassembler::DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst,
> unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
> +static MCDisassembler::DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst,
> unsigned Insn,
> uint64_t Address, const void *Decoder);
>
> -static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t
> Insn,
> +static MCDisassembler::DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst
> &Inst, uint16_t Insn,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
> +static MCDisassembler::DecodeStatus DecodeThumbBROperand(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
> +static MCDisassembler::DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst,
> unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeThumbAddrModePC(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
> +static MCDisassembler::DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst,
> unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
> +static MCDisassembler::DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst,
> unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
> +static MCDisassembler::DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst,
> unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
> +static MCDisassembler::DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
> +static MCDisassembler::DecodeStatus DecodeThumbAddSPImm(llvm::MCInst
> &Inst, uint16_t Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
> +static MCDisassembler::DecodeStatus DecodeThumbAddSPReg(llvm::MCInst
> &Inst, uint16_t Insn,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
> +static MCDisassembler::DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst,
> uint16_t Insn,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned
> Insn,
> +static MCDisassembler::DecodeStatus DecodeThumbBLXOffset(llvm::MCInst
> &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst,
> unsigned Val,
> +static MCDisassembler::DecodeStatus
> DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
> +static MCDisassembler::DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst,
> unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst
> &Inst,unsigned Val,
> +static MCDisassembler::DecodeStatus
> DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst,
> unsigned Val,
> +static MCDisassembler::DecodeStatus
> DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val,
> +static MCDisassembler::DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder);
>
> #include "ARMGenDisassemblerTables.inc"
> #include "ARMGenInstrInfo.inc"
> #include "ARMGenEDInfo.inc"
>
> -using namespace llvm;
> -
> static MCDisassembler *createARMDisassembler(const Target &T) {
> return new ARMDisassembler;
> }
> @@ -255,7 +257,7 @@
> return instInfoARM;
> }
>
> -DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
> +MCDisassembler::DecodeStatus ARMDisassembler::getInstruction(MCInst &MI,
> uint64_t &Size,
> const MemoryObject &Region,
> uint64_t Address,
> raw_ostream &os) const {
> @@ -264,7 +266,7 @@
> // We want to read exactly 4 bytes of data.
> if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
> Size = 0;
> - return Fail;
> + return MCDisassembler::Fail;
> }
>
> // Encoded as a small-endian 32-bit word in the stream.
> @@ -274,8 +276,8 @@
> (bytes[0] << 0);
>
> // Calling the auto-generated decoder function.
> - DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this);
> - if (result != Fail) {
> + MCDisassembler::DecodeStatus result = decodeARMInstruction32(MI, insn,
> Address, this);
> + if (result != MCDisassembler::Fail) {
> Size = 4;
> return result;
> }
> @@ -285,7 +287,7 @@
> // fact that we fail to encode a few instructions properly for Thumb.
> MI.clear();
> result = decodeCommonInstruction32(MI, insn, Address, this);
> - if (result != Fail) {
> + if (result != MCDisassembler::Fail) {
> Size = 4;
> return result;
> }
> @@ -294,45 +296,45 @@
> // and Thumb modes.
> MI.clear();
> result = decodeVFPInstruction32(MI, insn, Address, this);
> - if (result != Fail) {
> + if (result != MCDisassembler::Fail) {
> Size = 4;
> return result;
> }
>
> MI.clear();
> result = decodeNEONDataInstruction32(MI, insn, Address, this);
> - if (result != Fail) {
> + if (result != MCDisassembler::Fail) {
> Size = 4;
> // Add a fake predicate operand, because we share these instruction
> // definitions with Thumb2 where these instructions are predicable.
> - if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail;
> + if (!DecodePredicateOperand(MI, 0xE, Address, this)) return
> MCDisassembler::Fail;
> return result;
> }
>
> MI.clear();
> result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this);
> - if (result != Fail) {
> + if (result != MCDisassembler::Fail) {
> Size = 4;
> // Add a fake predicate operand, because we share these instruction
> // definitions with Thumb2 where these instructions are predicable.
> - if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail;
> + if (!DecodePredicateOperand(MI, 0xE, Address, this)) return
> MCDisassembler::Fail;
> return result;
> }
>
> MI.clear();
> result = decodeNEONDupInstruction32(MI, insn, Address, this);
> - if (result != Fail) {
> + if (result != MCDisassembler::Fail) {
> Size = 4;
> // Add a fake predicate operand, because we share these instruction
> // definitions with Thumb2 where these instructions are predicable.
> - if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail;
> + if (!DecodePredicateOperand(MI, 0xE, Address, this)) return
> MCDisassembler::Fail;
> return result;
> }
>
> MI.clear();
>
> Size = 0;
> - return Fail;
> + return MCDisassembler::Fail;
> }
>
> namespace llvm {
> @@ -438,7 +440,7 @@
> }
> }
>
> -DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
> +MCDisassembler::DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI,
> uint64_t &Size,
> const MemoryObject &Region,
> uint64_t Address,
> raw_ostream &os) const {
> @@ -447,12 +449,12 @@
> // We want to read exactly 2 bytes of data.
> if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
> Size = 0;
> - return Fail;
> + return MCDisassembler::Fail;
> }
>
> uint16_t insn16 = (bytes[1] << 8) | bytes[0];
> - DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address,
> this);
> - if (result != Fail) {
> + MCDisassembler::DecodeStatus result = decodeThumbInstruction16(MI,
> insn16, Address, this);
> + if (result != MCDisassembler::Fail) {
> Size = 2;
> AddThumbPredicate(MI);
> return result;
> @@ -470,7 +472,7 @@
>
> MI.clear();
> result = decodeThumb2Instruction16(MI, insn16, Address, this);
> - if (result != Fail) {
> + if (result != MCDisassembler::Fail) {
> Size = 2;
> AddThumbPredicate(MI);
>
> @@ -501,7 +503,7 @@
> // We want to read exactly 4 bytes of data.
> if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
> Size = 0;
> - return Fail;
> + return MCDisassembler::Fail;
> }
>
> uint32_t insn32 = (bytes[3] << 8) |
> @@ -510,7 +512,7 @@
> (bytes[0] << 16);
> MI.clear();
> result = decodeThumbInstruction32(MI, insn32, Address, this);
> - if (result != Fail) {
> + if (result != MCDisassembler::Fail) {
> Size = 4;
> bool InITBlock = ITBlock.size();
> AddThumbPredicate(MI);
> @@ -520,7 +522,7 @@
>
> MI.clear();
> result = decodeThumb2Instruction32(MI, insn32, Address, this);
> - if (result != Fail) {
> + if (result != MCDisassembler::Fail) {
> Size = 4;
> AddThumbPredicate(MI);
> return result;
> @@ -528,7 +530,7 @@
>
> MI.clear();
> result = decodeCommonInstruction32(MI, insn32, Address, this);
> - if (result != Fail) {
> + if (result != MCDisassembler::Fail) {
> Size = 4;
> AddThumbPredicate(MI);
> return result;
> @@ -536,7 +538,7 @@
>
> MI.clear();
> result = decodeVFPInstruction32(MI, insn32, Address, this);
> - if (result != Fail) {
> + if (result != MCDisassembler::Fail) {
> Size = 4;
> UpdateThumbVFPPredicate(MI);
> return result;
> @@ -544,7 +546,7 @@
>
> MI.clear();
> result = decodeNEONDupInstruction32(MI, insn32, Address, this);
> - if (result != Fail) {
> + if (result != MCDisassembler::Fail) {
> Size = 4;
> AddThumbPredicate(MI);
> return result;
> @@ -556,7 +558,7 @@
> NEONLdStInsn &= 0xF0FFFFFF;
> NEONLdStInsn |= 0x04000000;
> result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address,
> this);
> - if (result != Fail) {
> + if (result != MCDisassembler::Fail) {
> Size = 4;
> AddThumbPredicate(MI);
> return result;
> @@ -570,7 +572,7 @@
> NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit
> 24
> NEONDataInsn |= 0x12000000; // Set bits 28 and 25
> result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this);
> - if (result != Fail) {
> + if (result != MCDisassembler::Fail) {
> Size = 4;
> AddThumbPredicate(MI);
> return result;
> @@ -578,7 +580,7 @@
> }
>
> Size = 0;
> - return Fail;
> + return MCDisassembler::Fail;
> }
>
>
> @@ -596,31 +598,31 @@
> ARM::R12, ARM::SP, ARM::LR, ARM::PC
> };
>
> -static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned
> RegNo,
> +static MCDisassembler::DecodeStatus DecodeGPRRegisterClass(llvm::MCInst
> &Inst, unsigned RegNo,
> uint64_t Address, const void *Decoder) {
> if (RegNo > 15)
> - return Fail;
> + return MCDisassembler::Fail;
>
> unsigned Register = GPRDecoderTable[RegNo];
> Inst.addOperand(MCOperand::CreateReg(Register));
> - return Success;
> + return MCDisassembler::Success;
> }
>
> -static DecodeStatus
> +static MCDisassembler::DecodeStatus
> DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> uint64_t Address, const void *Decoder) {
> - if (RegNo == 15) return Fail;
> + if (RegNo == 15) return MCDisassembler::Fail;
> return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
> }
>
> -static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned
> RegNo,
> +static MCDisassembler::DecodeStatus DecodetGPRRegisterClass(llvm::MCInst
> &Inst, unsigned RegNo,
> uint64_t Address, const void *Decoder) {
> if (RegNo > 7)
> - return Fail;
> + return MCDisassembler::Fail;
> return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
> }
>
> -static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned
> RegNo,
> +static MCDisassembler::DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst
> &Inst, unsigned RegNo,
> uint64_t Address, const void *Decoder) {
> unsigned Register = 0;
> switch (RegNo) {
> @@ -643,16 +645,16 @@
> Register = ARM::R12;
> break;
> default:
> - return Fail;
> + return MCDisassembler::Fail;
> }
>
> Inst.addOperand(MCOperand::CreateReg(Register));
> - return Success;
> + return MCDisassembler::Success;
> }
>
> -static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned
> RegNo,
> +static MCDisassembler::DecodeStatus DecoderGPRRegisterClass(llvm::MCInst
> &Inst, unsigned RegNo,
> uint64_t Address, const void *Decoder) {
> - if (RegNo == 13 || RegNo == 15) return Fail;
> + if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
> return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
> }
>
> @@ -667,14 +669,14 @@
> ARM::S28, ARM::S29, ARM::S30, ARM::S31
> };
>
> -static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned
> RegNo,
> +static MCDisassembler::DecodeStatus DecodeSPRRegisterClass(llvm::MCInst
> &Inst, unsigned RegNo,
> uint64_t Address, const void *Decoder) {
> if (RegNo > 31)
> - return Fail;
> + return MCDisassembler::Fail;
>
> unsigned Register = SPRDecoderTable[RegNo];
> Inst.addOperand(MCOperand::CreateReg(Register));
> - return Success;
> + return MCDisassembler::Success;
> }
>
> static const unsigned DPRDecoderTable[] = {
> @@ -688,28 +690,28 @@
> ARM::D28, ARM::D29, ARM::D30, ARM::D31
> };
>
> -static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned
> RegNo,
> +static MCDisassembler::DecodeStatus DecodeDPRRegisterClass(llvm::MCInst
> &Inst, unsigned RegNo,
> uint64_t Address, const void *Decoder) {
> if (RegNo > 31)
> - return Fail;
> + return MCDisassembler::Fail;
>
> unsigned Register = DPRDecoderTable[RegNo];
> Inst.addOperand(MCOperand::CreateReg(Register));
> - return Success;
> + return MCDisassembler::Success;
> }
>
> -static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned
> RegNo,
> +static MCDisassembler::DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst
> &Inst, unsigned RegNo,
> uint64_t Address, const void *Decoder) {
> if (RegNo > 7)
> - return Fail;
> + return MCDisassembler::Fail;
> return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
> }
>
> -static DecodeStatus
> +static MCDisassembler::DecodeStatus
> DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> uint64_t Address, const void *Decoder) {
> if (RegNo > 15)
> - return Fail;
> + return MCDisassembler::Fail;
> return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
> }
>
> @@ -721,59 +723,59 @@
> };
>
>
> -static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned
> RegNo,
> +static MCDisassembler::DecodeStatus DecodeQPRRegisterClass(llvm::MCInst
> &Inst, unsigned RegNo,
> uint64_t Address, const void *Decoder) {
> if (RegNo > 31)
> - return Fail;
> + return MCDisassembler::Fail;
> RegNo >>= 1;
>
> unsigned Register = QPRDecoderTable[RegNo];
> Inst.addOperand(MCOperand::CreateReg(Register));
> - return Success;
> + return MCDisassembler::Success;
> }
>
> -static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodePredicateOperand(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> - if (Val == 0xF) return Fail;
> + if (Val == 0xF) return MCDisassembler::Fail;
> // AL predicate is not allowed on Thumb1 branches.
> if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
> - return Fail;
> + return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(Val));
> if (Val == ARMCC::AL) {
> Inst.addOperand(MCOperand::CreateReg(0));
> } else
> Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
> - return Success;
> + return MCDisassembler::Success;
> }
>
> -static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
> +static MCDisassembler::DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst,
> unsigned Val,
> uint64_t Address, const void *Decoder) {
> if (Val)
> Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
> else
> Inst.addOperand(MCOperand::CreateReg(0));
> - return Success;
> + return MCDisassembler::Success;
> }
>
> -static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
> +static MCDisassembler::DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst,
> unsigned Val,
> uint64_t Address, const void *Decoder) {
> uint32_t imm = Val & 0xFF;
> uint32_t rot = (Val & 0xF00) >> 7;
> uint32_t rot_imm = (imm >> rot) | (imm << (32-rot));
> Inst.addOperand(MCOperand::CreateImm(rot_imm));
> - return Success;
> + return MCDisassembler::Success;
> }
>
> -static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeSORegImmOperand(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rm = fieldFromInstruction32(Val, 0, 4);
> unsigned type = fieldFromInstruction32(Val, 5, 2);
> unsigned imm = fieldFromInstruction32(Val, 7, 5);
>
> // Register-immediate
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
>
> ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
> switch (type) {
> @@ -800,17 +802,17 @@
> return S;
> }
>
> -static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeSORegRegOperand(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rm = fieldFromInstruction32(Val, 0, 4);
> unsigned type = fieldFromInstruction32(Val, 5, 2);
> unsigned Rs = fieldFromInstruction32(Val, 8, 4);
>
> // Register-register
> - CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder));
> - CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder));
> + if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
> return MCDisassembler::Fail;
>
> ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
> switch (type) {
> @@ -833,52 +835,52 @@
> return S;
> }
>
> -static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
> +static MCDisassembler::DecodeStatus DecodeRegListOperand(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> // Empty register lists are not allowed.
> - if (CountPopulation_32(Val) == 0) return Fail;
> + if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
> for (unsigned i = 0; i < 16; ++i) {
> if (Val & (1 << i)) {
> - CHECK(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
> return MCDisassembler::Fail;
> }
> }
>
> return S;
> }
>
> -static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeSPRRegListOperand(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Vd = fieldFromInstruction32(Val, 8, 4);
> unsigned regs = Val & 0xFF;
>
> - CHECK(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder));
> + if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
> return MCDisassembler::Fail;
> for (unsigned i = 0; i < (regs - 1); ++i) {
> - CHECK(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder));
> + if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
> return MCDisassembler::Fail;
> }
>
> return S;
> }
>
> -static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeDPRRegListOperand(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Vd = fieldFromInstruction32(Val, 8, 4);
> unsigned regs = (Val & 0xFF) / 2;
>
> - CHECK(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder));
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
> return MCDisassembler::Fail;
> for (unsigned i = 0; i < (regs - 1); ++i) {
> - CHECK(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder));
> + if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
> return MCDisassembler::Fail;
> }
>
> return S;
> }
>
> -static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void
> *Decoder) {
> // This operand encodes a mask of contiguous zeros between a specified
> MSB
> // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
> @@ -890,12 +892,12 @@
> uint32_t msb_mask = (1 << (msb+1)) - 1;
> uint32_t lsb_mask = (1 << lsb) - 1;
> Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
> - return Success;
> + return MCDisassembler::Success;
> }
>
> -static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned
> Insn,
> +static MCDisassembler::DecodeStatus DecodeCopMemInstruction(llvm::MCInst
> &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned pred = fieldFromInstruction32(Insn, 28, 4);
> unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
> @@ -922,7 +924,7 @@
> case ARM::STCL_POST:
> case ARM::STCL_OPTION:
> if (coproc == 0xA || coproc == 0xB)
> - return Fail;
> + return MCDisassembler::Fail;
> break;
> default:
> break;
> @@ -930,7 +932,7 @@
>
> Inst.addOperand(MCOperand::CreateImm(coproc));
> Inst.addOperand(MCOperand::CreateImm(CRd));
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> switch (Inst.getOpcode()) {
> case ARM::LDC_OPTION:
> case ARM::LDCL_OPTION:
> @@ -1003,7 +1005,7 @@
> case ARM::STCL_PRE:
> case ARM::STCL_POST:
> case ARM::STCL_OPTION:
> - CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
> + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> return MCDisassembler::Fail;
> break;
> default:
> break;
> @@ -1012,10 +1014,10 @@
> return S;
> }
>
> -static DecodeStatus
> +static MCDisassembler::DecodeStatus
> DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
> @@ -1036,13 +1038,13 @@
> case ARM::STRT_POST_IMM:
> case ARM::STRBT_POST_REG:
> case ARM::STRBT_POST_IMM:
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> break;
> default:
> break;
> }
>
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
> return MCDisassembler::Fail;
>
> // On loads, the writeback operand comes after Rt.
> switch (Inst.getOpcode()) {
> @@ -1054,13 +1056,13 @@
> case ARM::LDRBT_POST_IMM:
> case ARM::LDRT_POST_REG:
> case ARM::LDRT_POST_IMM:
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> break;
> default:
> break;
> }
>
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
>
> ARM_AM::AddrOpc Op = ARM_AM::add;
> if (!fieldFromInstruction32(Insn, 23, 1))
> @@ -1073,10 +1075,10 @@
> else if (!P && writeback)
> idx_mode = ARMII::IndexModePost;
>
> - if (writeback && (Rn == 15 || Rn == Rt)) S = Unpredictable; //
> UNPREDICTABLE
> + if (writeback && (Rn == 15 || Rn == Rt)) S = MCDisassembler::SoftFail;
> // UNPREDICTABLE
>
> if (reg) {
> - CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder));
> + if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
> switch( fieldFromInstruction32(Insn, 5, 2)) {
> case 0:
> @@ -1092,7 +1094,7 @@
> Opc = ARM_AM::ror;
> break;
> default:
> - return Fail;
> + return MCDisassembler::Fail;
> }
> unsigned amt = fieldFromInstruction32(Insn, 7, 5);
> unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
> @@ -1104,14 +1106,14 @@
> Inst.addOperand(MCOperand::CreateImm(tmp));
> }
>
> - CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
> + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> return MCDisassembler::Fail;
>
> return S;
> }
>
> -static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeSORegMemOperand(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Val, 13, 4);
> unsigned Rm = fieldFromInstruction32(Val, 0, 4);
> @@ -1135,8 +1137,8 @@
> break;
> }
>
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> unsigned shift;
> if (U)
> shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
> @@ -1147,10 +1149,10 @@
> return S;
> }
>
> -static DecodeStatus
> +static MCDisassembler::DecodeStatus
> DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> @@ -1172,7 +1174,7 @@
> case ARM::LDRD:
> case ARM::LDRD_PRE:
> case ARM::LDRD_POST:
> - if (Rt & 0x1) return Fail;
> + if (Rt & 0x1) return MCDisassembler::Fail;
> break;
> default:
> break;
> @@ -1192,14 +1194,14 @@
> case ARM::STRH:
> case ARM::STRH_PRE:
> case ARM::STRH_POST:
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> break;
> default:
> break;
> }
> }
>
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
> return MCDisassembler::Fail;
> switch (Inst.getOpcode()) {
> case ARM::STRD:
> case ARM::STRD_PRE:
> @@ -1207,7 +1209,7 @@
> case ARM::LDRD:
> case ARM::LDRD_PRE:
> case ARM::LDRD_POST:
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
> return MCDisassembler::Fail;
> break;
> default:
> break;
> @@ -1230,31 +1232,31 @@
> case ARM::LDRSB_POST:
> case ARM::LDRHTr:
> case ARM::LDRSBTr:
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> break;
> default:
> break;
> }
> }
>
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
>
> if (type) {
> Inst.addOperand(MCOperand::CreateReg(0));
> Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
> } else {
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(U));
> }
>
> - CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
> + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> return MCDisassembler::Fail;
>
> return S;
> }
>
> -static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned
> Insn,
> +static MCDisassembler::DecodeStatus DecodeRFEInstruction(llvm::MCInst
> &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned mode = fieldFromInstruction32(Insn, 23, 2);
> @@ -1275,15 +1277,15 @@
> }
>
> Inst.addOperand(MCOperand::CreateImm(mode));
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
>
> return S;
> }
>
> -static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst
> &Inst,
> +static MCDisassembler::DecodeStatus
> DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
> unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned pred = fieldFromInstruction32(Insn, 28, 4);
> @@ -1340,7 +1342,7 @@
> Inst.setOpcode(ARM::SRSIB_UPD);
> break;
> default:
> - CHECK(S, Fail);
> + if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
> }
>
> // For stores (which become SRS's, the only operand is the mode.
> @@ -1353,29 +1355,29 @@
> return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
> }
>
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); // Tied
> - CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
> - CHECK(S, DecodeRegListOperand(Inst, reglist, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail; // Tied
> + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
> return MCDisassembler::Fail;
>
> return S;
> }
>
> -static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned
> Insn,
> +static MCDisassembler::DecodeStatus DecodeCPSInstruction(llvm::MCInst
> &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> unsigned imod = fieldFromInstruction32(Insn, 18, 2);
> unsigned M = fieldFromInstruction32(Insn, 17, 1);
> unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
> unsigned mode = fieldFromInstruction32(Insn, 0, 5);
>
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> // imod == '01' --> UNPREDICTABLE
> // NOTE: Even though this is technically UNPREDICTABLE, we choose to
> // return failure here. The '01' imod value is unprintable, so there's
> // nothing useful we could do even if we returned UNPREDICTABLE.
>
> - if (imod == 1) CHECK(S, Fail);
> + if (imod == 1) return MCDisassembler::Fail;
>
> if (imod && M) {
> Inst.setOpcode(ARM::CPS3p);
> @@ -1386,36 +1388,36 @@
> Inst.setOpcode(ARM::CPS2p);
> Inst.addOperand(MCOperand::CreateImm(imod));
> Inst.addOperand(MCOperand::CreateImm(iflags));
> - if (mode) CHECK(S, Unpredictable);
> + if (mode) S = MCDisassembler::SoftFail;
> } else if (!imod && M) {
> Inst.setOpcode(ARM::CPS1p);
> Inst.addOperand(MCOperand::CreateImm(mode));
> - if (iflags) CHECK(S, Unpredictable);
> + if (iflags) S = MCDisassembler::SoftFail;
> } else {
> // imod == '00' && M == '0' --> UNPREDICTABLE
> Inst.setOpcode(ARM::CPS1p);
> Inst.addOperand(MCOperand::CreateImm(mode));
> - CHECK(S, Unpredictable);
> + S = MCDisassembler::SoftFail;
> }
>
> return S;
> }
>
> -static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned
> Insn,
> +static MCDisassembler::DecodeStatus DecodeT2CPSInstruction(llvm::MCInst
> &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> unsigned imod = fieldFromInstruction32(Insn, 9, 2);
> unsigned M = fieldFromInstruction32(Insn, 8, 1);
> unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
> unsigned mode = fieldFromInstruction32(Insn, 0, 5);
>
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> // imod == '01' --> UNPREDICTABLE
> // NOTE: Even though this is technically UNPREDICTABLE, we choose to
> // return failure here. The '01' imod value is unprintable, so there's
> // nothing useful we could do even if we returned UNPREDICTABLE.
>
> - if (imod == 1) CHECK(S, Fail);
> + if (imod == 1) return MCDisassembler::Fail;
>
> if (imod && M) {
> Inst.setOpcode(ARM::t2CPS3p);
> @@ -1426,25 +1428,25 @@
> Inst.setOpcode(ARM::t2CPS2p);
> Inst.addOperand(MCOperand::CreateImm(imod));
> Inst.addOperand(MCOperand::CreateImm(iflags));
> - if (mode) CHECK(S, Unpredictable);
> + if (mode) S = MCDisassembler::SoftFail;
> } else if (!imod && M) {
> Inst.setOpcode(ARM::t2CPS1p);
> Inst.addOperand(MCOperand::CreateImm(mode));
> - if (iflags) CHECK(S, Unpredictable);
> + if (iflags) S = MCDisassembler::SoftFail;
> } else {
> // imod == '00' && M == '0' --> UNPREDICTABLE
> Inst.setOpcode(ARM::t2CPS1p);
> Inst.addOperand(MCOperand::CreateImm(mode));
> - CHECK(S, Unpredictable);
> + S = MCDisassembler::SoftFail;
> }
>
> return S;
> }
>
>
> -static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned
> Insn,
> +static MCDisassembler::DecodeStatus DecodeSMLAInstruction(llvm::MCInst
> &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
> @@ -1455,25 +1457,25 @@
> if (pred == 0xF)
> return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
>
> - CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder));
> - CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder));
> - CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder));
> - CHECK(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder));
> + if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
> return MCDisassembler::Fail;
>
> - CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
> + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> return MCDisassembler::Fail;
>
> return S;
> }
>
> -static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst,
> unsigned Val,
> +static MCDisassembler::DecodeStatus
> DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned add = fieldFromInstruction32(Val, 12, 1);
> unsigned imm = fieldFromInstruction32(Val, 0, 12);
> unsigned Rn = fieldFromInstruction32(Val, 13, 4);
>
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
>
> if (!add) imm *= -1;
> if (imm == 0 && !add) imm = INT32_MIN;
> @@ -1482,15 +1484,15 @@
> return S;
> }
>
> -static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeAddrMode5Operand(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Val, 9, 4);
> unsigned U = fieldFromInstruction32(Val, 8, 1);
> unsigned imm = fieldFromInstruction32(Val, 0, 8);
>
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
>
> if (U)
> Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add,
> imm)));
> @@ -1500,15 +1502,15 @@
> return S;
> }
>
> -static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeAddrMode7Operand(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
> }
>
> -static DecodeStatus
> +static MCDisassembler::DecodeStatus
> DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned pred = fieldFromInstruction32(Insn, 28, 4);
> unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
> @@ -1521,26 +1523,26 @@
> }
>
> Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
> - CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
> + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> return MCDisassembler::Fail;
>
> return S;
> }
>
>
> -static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
> +static MCDisassembler::DecodeStatus DecodeVCVTImmOperand(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> Inst.addOperand(MCOperand::CreateImm(64 - Val));
> - return Success;
> + return MCDisassembler::Success;
> }
>
> -static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeAddrMode6Operand(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rm = fieldFromInstruction32(Val, 0, 4);
> unsigned align = fieldFromInstruction32(Val, 4, 2);
>
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> if (!align)
> Inst.addOperand(MCOperand::CreateImm(0));
> else
> @@ -1549,9 +1551,9 @@
> return S;
> }
>
> -static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned
> Insn,
> +static MCDisassembler::DecodeStatus DecodeVLDInstruction(llvm::MCInst
> &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
> @@ -1561,7 +1563,7 @@
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
>
> // First output register
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
>
> // Second output register
> switch (Inst.getOpcode()) {
> @@ -1613,7 +1615,7 @@
> case ARM::VLD4d8_UPD:
> case ARM::VLD4d16_UPD:
> case ARM::VLD4d32_UPD:
> - CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder));
> + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address,
> Decoder))) return MCDisassembler::Fail;
> break;
> case ARM::VLD2b8:
> case ARM::VLD2b16:
> @@ -1633,7 +1635,7 @@
> case ARM::VLD4q8_UPD:
> case ARM::VLD4q16_UPD:
> case ARM::VLD4q32_UPD:
> - CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));
> + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address,
> Decoder))) return MCDisassembler::Fail;
> default:
> break;
> }
> @@ -1674,7 +1676,7 @@
> case ARM::VLD4d8_UPD:
> case ARM::VLD4d16_UPD:
> case ARM::VLD4d32_UPD:
> - CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));
> + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address,
> Decoder))) return MCDisassembler::Fail;
> break;
> case ARM::VLD3q8:
> case ARM::VLD3q16:
> @@ -1688,7 +1690,7 @@
> case ARM::VLD4q8_UPD:
> case ARM::VLD4q16_UPD:
> case ARM::VLD4q32_UPD:
> - CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder));
> + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address,
> Decoder))) return MCDisassembler::Fail;
> break;
> default:
> break;
> @@ -1716,7 +1718,7 @@
> case ARM::VLD4d8_UPD:
> case ARM::VLD4d16_UPD:
> case ARM::VLD4d32_UPD:
> - CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder));
> + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address,
> Decoder))) return MCDisassembler::Fail;
> break;
> case ARM::VLD4q8:
> case ARM::VLD4q16:
> @@ -1724,7 +1726,7 @@
> case ARM::VLD4q8_UPD:
> case ARM::VLD4q16_UPD:
> case ARM::VLD4q32_UPD:
> - CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder));
> + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address,
> Decoder))) return MCDisassembler::Fail;
> break;
> default:
> break;
> @@ -1769,28 +1771,28 @@
> case ARM::VLD4q8_UPD:
> case ARM::VLD4q16_UPD:
> case ARM::VLD4q32_UPD:
> - CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
> return MCDisassembler::Fail;
> break;
> default:
> break;
> }
>
> // AddrMode6 Base (register+alignment)
> - CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder));
> + if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
>
> // AddrMode6 Offset (register)
> if (Rm == 0xD)
> Inst.addOperand(MCOperand::CreateReg(0));
> else if (Rm != 0xF) {
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> }
>
> return S;
> }
>
> -static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned
> Insn,
> +static MCDisassembler::DecodeStatus DecodeVSTInstruction(llvm::MCInst
> &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
> @@ -1838,24 +1840,24 @@
> case ARM::VST4q8_UPD:
> case ARM::VST4q16_UPD:
> case ARM::VST4q32_UPD:
> - CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
> return MCDisassembler::Fail;
> break;
> default:
> break;
> }
>
> // AddrMode6 Base (register+alignment)
> - CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder));
> + if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
>
> // AddrMode6 Offset (register)
> if (Rm == 0xD)
> Inst.addOperand(MCOperand::CreateReg(0));
> else if (Rm != 0xF) {
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> }
>
> // First input register
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
>
> // Second input register
> switch (Inst.getOpcode()) {
> @@ -1907,7 +1909,7 @@
> case ARM::VST4d8_UPD:
> case ARM::VST4d16_UPD:
> case ARM::VST4d32_UPD:
> - CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder));
> + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address,
> Decoder))) return MCDisassembler::Fail;
> break;
> case ARM::VST2b8:
> case ARM::VST2b16:
> @@ -1927,7 +1929,7 @@
> case ARM::VST4q8_UPD:
> case ARM::VST4q16_UPD:
> case ARM::VST4q32_UPD:
> - CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));
> + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address,
> Decoder))) return MCDisassembler::Fail;
> break;
> default:
> break;
> @@ -1969,7 +1971,7 @@
> case ARM::VST4d8_UPD:
> case ARM::VST4d16_UPD:
> case ARM::VST4d32_UPD:
> - CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));
> + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address,
> Decoder))) return MCDisassembler::Fail;
> break;
> case ARM::VST3q8:
> case ARM::VST3q16:
> @@ -1983,7 +1985,7 @@
> case ARM::VST4q8_UPD:
> case ARM::VST4q16_UPD:
> case ARM::VST4q32_UPD:
> - CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder));
> + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address,
> Decoder))) return MCDisassembler::Fail;
> break;
> default:
> break;
> @@ -2011,7 +2013,7 @@
> case ARM::VST4d8_UPD:
> case ARM::VST4d16_UPD:
> case ARM::VST4d32_UPD:
> - CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder));
> + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address,
> Decoder))) return MCDisassembler::Fail;
> break;
> case ARM::VST4q8:
> case ARM::VST4q16:
> @@ -2019,7 +2021,7 @@
> case ARM::VST4q8_UPD:
> case ARM::VST4q16_UPD:
> case ARM::VST4q32_UPD:
> - CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder));
> + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address,
> Decoder))) return MCDisassembler::Fail;
> break;
> default:
> break;
> @@ -2028,9 +2030,9 @@
> return S;
> }
>
> -static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned
> Insn,
> +static MCDisassembler::DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst
> &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder)
> {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
> @@ -2042,29 +2044,29 @@
>
> align *= (1 << size);
>
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> if (regs == 2) {
> - CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder));
> + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address,
> Decoder))) return MCDisassembler::Fail;
> }
> if (Rm != 0xF) {
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> }
>
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(align));
>
> if (Rm == 0xD)
> Inst.addOperand(MCOperand::CreateReg(0));
> else if (Rm != 0xF) {
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> }
>
> return S;
> }
>
> -static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned
> Insn,
> +static MCDisassembler::DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst
> &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder)
> {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
> @@ -2075,27 +2077,27 @@
> unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
> align *= 2*size;
>
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
> - CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder));
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address,
> Decoder))) return MCDisassembler::Fail;
> if (Rm != 0xF) {
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> }
>
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(align));
>
> if (Rm == 0xD)
> Inst.addOperand(MCOperand::CreateReg(0));
> else if (Rm != 0xF) {
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> }
>
> return S;
> }
>
> -static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned
> Insn,
> +static MCDisassembler::DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst
> &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder)
> {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
> @@ -2103,28 +2105,28 @@
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
>
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
> - CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder));
> - CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder));
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address,
> Decoder))) return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address,
> Decoder))) return MCDisassembler::Fail;
> if (Rm != 0xF) {
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> }
>
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(0));
>
> if (Rm == 0xD)
> Inst.addOperand(MCOperand::CreateReg(0));
> else if (Rm != 0xF) {
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> }
>
> return S;
> }
>
> -static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned
> Insn,
> +static MCDisassembler::DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst
> &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder)
> {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
> @@ -2147,30 +2149,30 @@
> }
> }
>
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
> - CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder));
> - CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder));
> - CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder));
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address,
> Decoder))) return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address,
> Decoder))) return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address,
> Decoder))) return MCDisassembler::Fail;
> if (Rm != 0xF) {
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> }
>
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(align));
>
> if (Rm == 0xD)
> Inst.addOperand(MCOperand::CreateReg(0));
> else if (Rm != 0xF) {
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> }
>
> return S;
> }
>
> -static DecodeStatus
> +static MCDisassembler::DecodeStatus
> DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
> @@ -2182,9 +2184,9 @@
> unsigned Q = fieldFromInstruction32(Insn, 6, 1);
>
> if (Q) {
> - CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder));
> + if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> } else {
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> }
>
> Inst.addOperand(MCOperand::CreateImm(imm));
> @@ -2194,13 +2196,13 @@
> case ARM::VORRiv2i32:
> case ARM::VBICiv4i16:
> case ARM::VBICiv2i32:
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> break;
> case ARM::VORRiv8i16:
> case ARM::VORRiv4i32:
> case ARM::VBICiv8i16:
> case ARM::VBICiv4i32:
> - CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder));
> + if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> break;
> default:
> break;
> @@ -2209,9 +2211,9 @@
> return S;
> }
>
> -static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned
> Insn,
> +static MCDisassembler::DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst
> &Inst, unsigned Insn,
> uint64_t Address, const void
> *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
> @@ -2219,40 +2221,40 @@
> Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
> unsigned size = fieldFromInstruction32(Insn, 18, 2);
>
> - CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder));
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder));
> + if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(8 << size));
>
> return S;
> }
>
> -static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
> +static MCDisassembler::DecodeStatus DecodeShiftRight8Imm(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> Inst.addOperand(MCOperand::CreateImm(8 - Val));
> - return Success;
> + return MCDisassembler::Success;
> }
>
> -static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeShiftRight16Imm(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> Inst.addOperand(MCOperand::CreateImm(16 - Val));
> - return Success;
> + return MCDisassembler::Success;
> }
>
> -static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeShiftRight32Imm(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> Inst.addOperand(MCOperand::CreateImm(32 - Val));
> - return Success;
> + return MCDisassembler::Success;
> }
>
> -static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeShiftRight64Imm(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> Inst.addOperand(MCOperand::CreateImm(64 - Val));
> - return Success;
> + return MCDisassembler::Success;
> }
>
> -static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned
> Insn,
> +static MCDisassembler::DecodeStatus DecodeTBLInstruction(llvm::MCInst
> &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
> @@ -2263,21 +2265,21 @@
> unsigned op = fieldFromInstruction32(Insn, 6, 1);
> unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;
>
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> if (op) {
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); //
> Writeback
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail; // Writeback
> }
>
> for (unsigned i = 0; i < length; ++i) {
> - CHECK(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder));
> + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address,
> Decoder))) return MCDisassembler::Fail;
> }
>
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder));
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
>
> return S;
> }
>
> -static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
> +static MCDisassembler::DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst,
> unsigned Val,
> uint64_t Address, const void *Decoder) {
> // The immediate needs to be a fully instantiated float. However, the
> // auto-generated decoder is only able to fill in some of the bits
> @@ -2299,21 +2301,21 @@
> fp_conv.integer |= (~b & 0x1) << 30;
>
> Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp));
> - return Success;
> + return MCDisassembler::Success;
> }
>
> -static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t
> Insn,
> +static MCDisassembler::DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst
> &Inst, uint16_t Insn,
> uint64_t Address, const void *Decoder)
> {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned dst = fieldFromInstruction16(Insn, 8, 3);
> unsigned imm = fieldFromInstruction16(Insn, 0, 8);
>
> - CHECK(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder));
> + if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
> return MCDisassembler::Fail;
>
> switch(Inst.getOpcode()) {
> default:
> - return Fail;
> + return MCDisassembler::Fail;
> case ARM::tADR:
> break; // tADR does not explicitly represent the PC as an operand.
> case ARM::tADDrSPi:
> @@ -2325,83 +2327,83 @@
> return S;
> }
>
> -static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
> +static MCDisassembler::DecodeStatus DecodeThumbBROperand(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
> - return Success;
> + return MCDisassembler::Success;
> }
>
> -static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
> +static MCDisassembler::DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst,
> unsigned Val,
> uint64_t Address, const void *Decoder) {
> Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
> - return Success;
> + return MCDisassembler::Success;
> }
>
> -static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
> - return Success;
> + return MCDisassembler::Success;
> }
>
> -static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Val, 0, 3);
> unsigned Rm = fieldFromInstruction32(Val, 3, 3);
>
> - CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder));
> - CHECK(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder));
> + if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
>
> return S;
> }
>
> -static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Val, 0, 3);
> unsigned imm = fieldFromInstruction32(Val, 3, 5);
>
> - CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder));
> + if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(imm));
>
> return S;
> }
>
> -static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeThumbAddrModePC(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> Inst.addOperand(MCOperand::CreateImm(Val << 2));
>
> - return Success;
> + return MCDisassembler::Success;
> }
>
> -static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> Inst.addOperand(MCOperand::CreateReg(ARM::SP));
> Inst.addOperand(MCOperand::CreateImm(Val));
>
> - return Success;
> + return MCDisassembler::Success;
> }
>
> -static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Val, 6, 4);
> unsigned Rm = fieldFromInstruction32(Val, 2, 4);
> unsigned imm = fieldFromInstruction32(Val, 0, 2);
>
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> - CHECK(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(imm));
>
> return S;
> }
>
> -static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
> +static MCDisassembler::DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst,
> unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> switch (Inst.getOpcode()) {
> case ARM::t2PLDs:
> @@ -2410,7 +2412,7 @@
> break;
> default: {
> unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
> return MCDisassembler::Fail;
> }
> }
>
> @@ -2434,7 +2436,7 @@
> Inst.addOperand(MCOperand::CreateReg(ARM::PC));
> break;
> default:
> - return Fail;
> + return MCDisassembler::Fail;
> }
>
> int imm = fieldFromInstruction32(Insn, 0, 12);
> @@ -2447,46 +2449,46 @@
> unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
> addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
> addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
> - CHECK(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder));
> + if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
> return MCDisassembler::Fail;
>
> return S;
> }
>
> -static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
> +static MCDisassembler::DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst,
> unsigned Val,
> uint64_t Address, const void *Decoder) {
> int imm = Val & 0xFF;
> if (!(Val & 0x100)) imm *= -1;
> Inst.addOperand(MCOperand::CreateImm(imm << 2));
>
> - return Success;
> + return MCDisassembler::Success;
> }
>
> -static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Val, 9, 4);
> unsigned imm = fieldFromInstruction32(Val, 0, 9);
>
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> - CHECK(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) return
> MCDisassembler::Fail;
>
> return S;
> }
>
> -static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
> +static MCDisassembler::DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst,
> unsigned Val,
> uint64_t Address, const void *Decoder) {
> int imm = Val & 0xFF;
> if (!(Val & 0x100)) imm *= -1;
> Inst.addOperand(MCOperand::CreateImm(imm));
>
> - return Success;
> + return MCDisassembler::Success;
> }
>
>
> -static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
> +static MCDisassembler::DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Val, 9, 4);
> unsigned imm = fieldFromInstruction32(Val, 0, 9);
> @@ -2504,28 +2506,28 @@
> break;
> }
>
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> - CHECK(S, DecodeT2Imm8(Inst, imm, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) return
> MCDisassembler::Fail;
>
> return S;
> }
>
>
> -static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Val, 13, 4);
> unsigned imm = fieldFromInstruction32(Val, 0, 12);
>
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(imm));
>
> return S;
> }
>
>
> -static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
> +static MCDisassembler::DecodeStatus DecodeThumbAddSPImm(llvm::MCInst
> &Inst, uint16_t Insn,
> uint64_t Address, const void *Decoder) {
> unsigned imm = fieldFromInstruction16(Insn, 0, 7);
>
> @@ -2533,32 +2535,32 @@
> Inst.addOperand(MCOperand::CreateReg(ARM::SP));
> Inst.addOperand(MCOperand::CreateImm(imm));
>
> - return Success;
> + return MCDisassembler::Success;
> }
>
> -static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
> +static MCDisassembler::DecodeStatus DecodeThumbAddSPReg(llvm::MCInst
> &Inst, uint16_t Insn,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> if (Inst.getOpcode() == ARM::tADDrSP) {
> unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
> Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
>
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder));
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
> return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateReg(ARM::SP));
> } else if (Inst.getOpcode() == ARM::tADDspr) {
> unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
>
> Inst.addOperand(MCOperand::CreateReg(ARM::SP));
> Inst.addOperand(MCOperand::CreateReg(ARM::SP));
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> }
>
> return S;
> }
>
> -static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
> +static MCDisassembler::DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst,
> uint16_t Insn,
> uint64_t Address, const void *Decoder) {
> unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
> unsigned flags = fieldFromInstruction16(Insn, 0, 3);
> @@ -2566,47 +2568,47 @@
> Inst.addOperand(MCOperand::CreateImm(imod));
> Inst.addOperand(MCOperand::CreateImm(flags));
>
> - return Success;
> + return MCDisassembler::Success;
> }
>
> -static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
> +static MCDisassembler::DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst,
> unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> unsigned add = fieldFromInstruction32(Insn, 4, 1);
>
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) ;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(add));
>
> return S;
> }
>
> -static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
> +static MCDisassembler::DecodeStatus DecodeThumbBLXOffset(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
> - return Success;
> + return MCDisassembler::Success;
> }
>
> -static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
> +static MCDisassembler::DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst,
> unsigned Val,
> uint64_t Address, const void *Decoder) {
> if (Val == 0xA || Val == 0xB)
> - return Fail;
> + return MCDisassembler::Fail;
>
> Inst.addOperand(MCOperand::CreateImm(Val));
> - return Success;
> + return MCDisassembler::Success;
> }
>
> -static DecodeStatus
> +static MCDisassembler::DecodeStatus
> DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned pred = fieldFromInstruction32(Insn, 22, 4);
> if (pred == 0xE || pred == 0xF) {
> unsigned opc = fieldFromInstruction32(Insn, 4, 28);
> switch (opc) {
> default:
> - return Fail;
> + return MCDisassembler::Fail;
> case 0xf3bf8f4:
> Inst.setOpcode(ARM::t2DSB);
> break;
> @@ -2615,7 +2617,7 @@
> break;
> case 0xf3bf8f6:
> Inst.setOpcode(ARM::t2ISB);
> - return Success;
> + return MCDisassembler::Success;
> }
>
> unsigned imm = fieldFromInstruction32(Insn, 0, 4);
> @@ -2628,8 +2630,8 @@
> brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
> brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
>
> - CHECK(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder));
> - CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
> + if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> return MCDisassembler::Fail;
>
> return S;
> }
> @@ -2637,7 +2639,7 @@
> // Decode a shifted immediate operand. These basically consist
> // of an 8-bit value, and a 4-bit directive that specifies either
> // a splat operation or a rotation.
> -static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
> +static MCDisassembler::DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst,
> unsigned Val,
> uint64_t Address, const void *Decoder) {
> unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
> if (ctrl == 0) {
> @@ -2665,27 +2667,27 @@
> Inst.addOperand(MCOperand::CreateImm(imm));
> }
>
> - return Success;
> + return MCDisassembler::Success;
> }
>
> -static DecodeStatus
> +static MCDisassembler::DecodeStatus
> DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder){
> Inst.addOperand(MCOperand::CreateImm(Val << 1));
> - return Success;
> + return MCDisassembler::Success;
> }
>
> -static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst,
> unsigned Val,
> +static MCDisassembler::DecodeStatus
> DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void
> *Decoder){
> Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
> - return Success;
> + return MCDisassembler::Success;
> }
>
> -static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned
> Val,
> +static MCDisassembler::DecodeStatus DecodeMemBarrierOption(llvm::MCInst
> &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> switch (Val) {
> default:
> - return Fail;
> + return MCDisassembler::Fail;
> case 0xF: // SY
> case 0xE: // ST
> case 0xB: // ISH
> @@ -2698,60 +2700,60 @@
> }
>
> Inst.addOperand(MCOperand::CreateImm(Val));
> - return Success;
> + return MCDisassembler::Success;
> }
>
> -static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
> +static MCDisassembler::DecodeStatus DecodeMSRMask(llvm::MCInst &Inst,
> unsigned Val,
> uint64_t Address, const void *Decoder) {
> - if (!Val) return Fail;
> + if (!Val) return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(Val));
> - return Success;
> + return MCDisassembler::Success;
> }
>
> -static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
> +static MCDisassembler::DecodeStatus DecodeDoubleRegLoad(llvm::MCInst
> &Inst, unsigned Insn,
> uint64_t Address, const void
> *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned pred = fieldFromInstruction32(Insn, 28, 4);
>
> - if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail;
> + if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
>
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder));
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> - CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> return MCDisassembler::Fail;
>
> return S;
> }
>
>
> -static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned
> Insn,
> +static MCDisassembler::DecodeStatus DecodeDoubleRegStore(llvm::MCInst
> &Inst, unsigned Insn,
> uint64_t Address, const void
> *Decoder){
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned pred = fieldFromInstruction32(Insn, 28, 4);
>
> - CHECK(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder));
> + if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
>
> - if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail;
> - if (Rd == Rn || Rd == Rt || Rd == Rt+1) return Fail;
> + if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
> + if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
>
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder));
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> - CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> return MCDisassembler::Fail;
>
> return S;
> }
>
> -static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
> +static MCDisassembler::DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst,
> unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
> @@ -2760,19 +2762,19 @@
> imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
> unsigned pred = fieldFromInstruction32(Insn, 28, 4);
>
> - if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable);
> + if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
>
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> - CHECK(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder));
> - CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> return MCDisassembler::Fail;
>
> return S;
> }
>
> -static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
> +static MCDisassembler::DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst,
> unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
> @@ -2782,21 +2784,21 @@
> unsigned pred = fieldFromInstruction32(Insn, 28, 4);
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
>
> - if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable);
> - if (Rm == 0xF) CHECK(S, Unpredictable);
> + if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
> + if (Rm == 0xF) S = MCDisassembler::SoftFail;
>
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> - CHECK(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder));
> - CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> return MCDisassembler::Fail;
>
> return S;
> }
>
>
> -static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
> +static MCDisassembler::DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst,
> unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
> @@ -2805,19 +2807,19 @@
> imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
> unsigned pred = fieldFromInstruction32(Insn, 28, 4);
>
> - if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable);
> + if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
>
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
> - CHECK(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder));
> - CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> return MCDisassembler::Fail;
>
> return S;
> }
>
> -static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
> +static MCDisassembler::DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst,
> unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
> @@ -2826,19 +2828,19 @@
> imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
> unsigned pred = fieldFromInstruction32(Insn, 28, 4);
>
> - if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable);
> + if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
>
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
> - CHECK(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder));
> - CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> return MCDisassembler::Fail;
>
> return S;
> }
>
> -static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
> +static MCDisassembler::DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst,
> unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> @@ -2850,49 +2852,49 @@
> unsigned index = 0;
> switch (size) {
> default:
> - return Fail;
> + return MCDisassembler::Fail;
> case 0:
> if (fieldFromInstruction32(Insn, 4, 1))
> - return Fail; // UNDEFINED
> + return MCDisassembler::Fail; // UNDEFINED
> index = fieldFromInstruction32(Insn, 5, 3);
> break;
> case 1:
> if (fieldFromInstruction32(Insn, 5, 1))
> - return Fail; // UNDEFINED
> + return MCDisassembler::Fail; // UNDEFINED
> index = fieldFromInstruction32(Insn, 6, 2);
> if (fieldFromInstruction32(Insn, 4, 1))
> align = 2;
> break;
> case 2:
> if (fieldFromInstruction32(Insn, 6, 1))
> - return Fail; // UNDEFINED
> + return MCDisassembler::Fail; // UNDEFINED
> index = fieldFromInstruction32(Insn, 7, 1);
> if (fieldFromInstruction32(Insn, 4, 2) != 0)
> align = 4;
> }
>
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> if (Rm != 0xF) { // Writeback
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> }
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(align));
> if (Rm != 0xF) {
> - if (Rm != 0xD)
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
> - else
> + if (Rm != 0xD) {
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> + } else
> Inst.addOperand(MCOperand::CreateReg(0));
> }
>
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(index));
>
> return S;
> }
>
> -static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
> +static MCDisassembler::DecodeStatus DecodeVST1LN(llvm::MCInst &Inst,
> unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> @@ -2904,49 +2906,49 @@
> unsigned index = 0;
> switch (size) {
> default:
> - return Fail;
> + return MCDisassembler::Fail;
> case 0:
> if (fieldFromInstruction32(Insn, 4, 1))
> - return Fail; // UNDEFINED
> + return MCDisassembler::Fail; // UNDEFINED
> index = fieldFromInstruction32(Insn, 5, 3);
> break;
> case 1:
> if (fieldFromInstruction32(Insn, 5, 1))
> - return Fail; // UNDEFINED
> + return MCDisassembler::Fail; // UNDEFINED
> index = fieldFromInstruction32(Insn, 6, 2);
> if (fieldFromInstruction32(Insn, 4, 1))
> align = 2;
> break;
> case 2:
> if (fieldFromInstruction32(Insn, 6, 1))
> - return Fail; // UNDEFINED
> + return MCDisassembler::Fail; // UNDEFINED
> index = fieldFromInstruction32(Insn, 7, 1);
> if (fieldFromInstruction32(Insn, 4, 2) != 0)
> align = 4;
> }
>
> if (Rm != 0xF) { // Writeback
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> }
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(align));
> if (Rm != 0xF) {
> - if (Rm != 0xD)
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
> - else
> + if (Rm != 0xD) {
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> + } else
> Inst.addOperand(MCOperand::CreateReg(0));
> }
>
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(index));
>
> return S;
> }
>
>
> -static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
> +static MCDisassembler::DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst,
> unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> @@ -2959,7 +2961,7 @@
> unsigned inc = 1;
> switch (size) {
> default:
> - return Fail;
> + return MCDisassembler::Fail;
> case 0:
> index = fieldFromInstruction32(Insn, 5, 3);
> if (fieldFromInstruction32(Insn, 4, 1))
> @@ -2974,7 +2976,7 @@
> break;
> case 2:
> if (fieldFromInstruction32(Insn, 5, 1))
> - return Fail; // UNDEFINED
> + return MCDisassembler::Fail; // UNDEFINED
> index = fieldFromInstruction32(Insn, 7, 1);
> if (fieldFromInstruction32(Insn, 4, 1) != 0)
> align = 8;
> @@ -2983,30 +2985,30 @@
> break;
> }
>
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
> return MCDisassembler::Fail;
> if (Rm != 0xF) { // Writeback
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> }
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(align));
> if (Rm != 0xF) {
> - if (Rm != 0xD)
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
> - else
> + if (Rm != 0xD) {
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> + } else
> Inst.addOperand(MCOperand::CreateReg(0));
> }
>
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
> return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(index));
>
> return S;
> }
>
> -static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
> +static MCDisassembler::DecodeStatus DecodeVST2LN(llvm::MCInst &Inst,
> unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> @@ -3019,7 +3021,7 @@
> unsigned inc = 1;
> switch (size) {
> default:
> - return Fail;
> + return MCDisassembler::Fail;
> case 0:
> index = fieldFromInstruction32(Insn, 5, 3);
> if (fieldFromInstruction32(Insn, 4, 1))
> @@ -3034,7 +3036,7 @@
> break;
> case 2:
> if (fieldFromInstruction32(Insn, 5, 1))
> - return Fail; // UNDEFINED
> + return MCDisassembler::Fail; // UNDEFINED
> index = fieldFromInstruction32(Insn, 7, 1);
> if (fieldFromInstruction32(Insn, 4, 1) != 0)
> align = 8;
> @@ -3044,28 +3046,28 @@
> }
>
> if (Rm != 0xF) { // Writeback
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> }
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(align));
> if (Rm != 0xF) {
> - if (Rm != 0xD)
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
> - else
> + if (Rm != 0xD) {
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> + } else
> Inst.addOperand(MCOperand::CreateReg(0));
> }
>
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
> return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(index));
>
> return S;
> }
>
>
> -static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
> +static MCDisassembler::DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst,
> unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> @@ -3078,55 +3080,55 @@
> unsigned inc = 1;
> switch (size) {
> default:
> - return Fail;
> + return MCDisassembler::Fail;
> case 0:
> if (fieldFromInstruction32(Insn, 4, 1))
> - return Fail; // UNDEFINED
> + return MCDisassembler::Fail; // UNDEFINED
> index = fieldFromInstruction32(Insn, 5, 3);
> break;
> case 1:
> if (fieldFromInstruction32(Insn, 4, 1))
> - return Fail; // UNDEFINED
> + return MCDisassembler::Fail; // UNDEFINED
> index = fieldFromInstruction32(Insn, 6, 2);
> if (fieldFromInstruction32(Insn, 5, 1))
> inc = 2;
> break;
> case 2:
> if (fieldFromInstruction32(Insn, 4, 2))
> - return Fail; // UNDEFINED
> + return MCDisassembler::Fail; // UNDEFINED
> index = fieldFromInstruction32(Insn, 7, 1);
> if (fieldFromInstruction32(Insn, 6, 1))
> inc = 2;
> break;
> }
>
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
> return MCDisassembler::Fail;
>
> if (Rm != 0xF) { // Writeback
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> }
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(align));
> if (Rm != 0xF) {
> - if (Rm != 0xD)
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
> - else
> + if (Rm != 0xD) {
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> + } else
> Inst.addOperand(MCOperand::CreateReg(0));
> }
>
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
> return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(index));
>
> return S;
> }
>
> -static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
> +static MCDisassembler::DecodeStatus DecodeVST3LN(llvm::MCInst &Inst,
> unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> @@ -3139,22 +3141,22 @@
> unsigned inc = 1;
> switch (size) {
> default:
> - return Fail;
> + return MCDisassembler::Fail;
> case 0:
> if (fieldFromInstruction32(Insn, 4, 1))
> - return Fail; // UNDEFINED
> + return MCDisassembler::Fail; // UNDEFINED
> index = fieldFromInstruction32(Insn, 5, 3);
> break;
> case 1:
> if (fieldFromInstruction32(Insn, 4, 1))
> - return Fail; // UNDEFINED
> + return MCDisassembler::Fail; // UNDEFINED
> index = fieldFromInstruction32(Insn, 6, 2);
> if (fieldFromInstruction32(Insn, 5, 1))
> inc = 2;
> break;
> case 2:
> if (fieldFromInstruction32(Insn, 4, 2))
> - return Fail; // UNDEFINED
> + return MCDisassembler::Fail; // UNDEFINED
> index = fieldFromInstruction32(Insn, 7, 1);
> if (fieldFromInstruction32(Insn, 6, 1))
> inc = 2;
> @@ -3162,29 +3164,29 @@
> }
>
> if (Rm != 0xF) { // Writeback
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> }
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(align));
> if (Rm != 0xF) {
> - if (Rm != 0xD)
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
> - else
> + if (Rm != 0xD) {
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> + } else
> Inst.addOperand(MCOperand::CreateReg(0));
> }
>
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
> return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(index));
>
> return S;
> }
>
>
> -static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
> +static MCDisassembler::DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst,
> unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> @@ -3197,7 +3199,7 @@
> unsigned inc = 1;
> switch (size) {
> default:
> - return Fail;
> + return MCDisassembler::Fail;
> case 0:
> if (fieldFromInstruction32(Insn, 4, 1))
> align = 4;
> @@ -3219,35 +3221,35 @@
> break;
> }
>
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder));
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
> return MCDisassembler::Fail;
>
> if (Rm != 0xF) { // Writeback
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> }
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(align));
> if (Rm != 0xF) {
> - if (Rm != 0xD)
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
> - else
> + if (Rm != 0xD) {
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> + } else
> Inst.addOperand(MCOperand::CreateReg(0));
> }
>
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder));
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
> return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(index));
>
> return S;
> }
>
> -static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
> +static MCDisassembler::DecodeStatus DecodeVST4LN(llvm::MCInst &Inst,
> unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> @@ -3260,7 +3262,7 @@
> unsigned inc = 1;
> switch (size) {
> default:
> - return Fail;
> + return MCDisassembler::Fail;
> case 0:
> if (fieldFromInstruction32(Insn, 4, 1))
> align = 4;
> @@ -3283,29 +3285,29 @@
> }
>
> if (Rm != 0xF) { // Writeback
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> }
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(align));
> if (Rm != 0xF) {
> - if (Rm != 0xD)
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
> - else
> + if (Rm != 0xD) {
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> + } else
> Inst.addOperand(MCOperand::CreateReg(0));
> }
>
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
> - CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder));
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
> return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(index));
>
> return S;
> }
>
> -static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
> +static MCDisassembler::DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst,
> unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
> unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> @@ -3313,20 +3315,20 @@
> Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
>
> if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
> - CHECK(S, Unpredictable);
> + S = MCDisassembler::SoftFail;
>
> - CHECK(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder));
> - CHECK(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder));
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder));
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder));
> - CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
> + if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> return MCDisassembler::Fail;
>
> return S;
> }
>
> -static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
> +static MCDisassembler::DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst,
> unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
> unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> @@ -3334,20 +3336,20 @@
> Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
>
> if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
> - CHECK(S, Unpredictable);
> + S = MCDisassembler::SoftFail;
>
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder));
> - CHECK(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder));
> - CHECK(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder));
> - CHECK(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder));
> - CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> return MCDisassembler::Fail;
>
> return S;
> }
>
> -static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn,
> +static MCDisassembler::DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned
> Insn,
> uint64_t Address, const void *Decoder) {
> - DecodeStatus S = Success;
> + MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> unsigned pred = fieldFromInstruction16(Insn, 4, 4);
> // The InstPrinter needs to have the low bit of the predicate in
> // the mask operand to be able to print it properly.
> @@ -3355,7 +3357,7 @@
>
> if (pred == 0xF) {
> pred = 0xE;
> - CHECK(S, Unpredictable);
> + S = MCDisassembler::SoftFail;
> }
>
> if ((mask & 0xF) == 0) {
> @@ -3363,7 +3365,7 @@
> // the predicate.
> mask &= 0x10;
> mask |= 0x8;
> - CHECK(S, Unpredictable);
> + S = MCDisassembler::SoftFail;
> }
>
> Inst.addOperand(MCOperand::CreateImm(pred));
>
> Modified: llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp?rev=138948&r1=138947&r2=138948&view=diff
>
> ==============================================================================
> --- llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp (original)
> +++ llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp Thu Sep 1 13:02:14
> 2011
> @@ -132,9 +132,9 @@
> if (Target.getName() == "ARM" ||
> Target.getName() == "Thumb") {
> FixedLenDecoderEmitter(Records,
> - "CHECK(S, ", ");",
> - "S", "Fail",
> - "DecodeStatus S = Success;\n(void)S;").run(OS);
> + "if (!Check(S, ", ")) return
> MCDisassembler::Fail;",
> + "S", "MCDisassembler::Fail",
> + "MCDisassembler::DecodeStatus S =
> MCDisassembler::Success;\n(void)S;").run(OS);
> return;
> }
>
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
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