Hi! I think your patch caused these build failures with newer gcc's:<div><br></div><div>llvm/lib/MC/MCDisassembler/EDDisassembler.cpp:265: error: control reaches end of non-void function [-Wreturn-type]</div><div>llvm/lib/MC/MCDisassembler/Disassembler.cpp:159: error: control reaches end of non-void function [-Wreturn-type] </div>
<div><br></div><div>Could you please take a look?</div><div><br></div><div>Nick</div><div><br></div><div><div class="gmail_quote">On 1 September 2011 11:02, James Molloy <span dir="ltr"><<a href="mailto:james.molloy@arm.com">james.molloy@arm.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex;">Author: jamesm<br>
Date: Thu Sep 1 13:02:14 2011<br>
New Revision: 138948<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=138948&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=138948&view=rev</a><br>
Log:<br>
Fix up r137380 based on post-commit review by Jim Grosbach.<br>
<br>
Modified:<br>
llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp<br>
llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp<br>
llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp<br>
llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp<br>
<br>
Modified: llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp?rev=138948&r1=138947&r2=138948&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp?rev=138948&r1=138947&r2=138948&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp (original)<br>
+++ llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp Thu Sep 1 13:02:14 2011<br>
@@ -135,18 +135,25 @@<br>
MCInst Inst;<br>
const MCDisassembler *DisAsm = DC->getDisAsm();<br>
MCInstPrinter *IP = DC->getIP();<br>
- if (!DisAsm->getInstruction(Inst, Size, MemoryObject, PC, /*REMOVE*/ nulls()))<br>
+ MCDisassembler::DecodeStatus S;<br>
+ S = DisAsm->getInstruction(Inst, Size, MemoryObject, PC, /*REMOVE*/ nulls());<br>
+ switch (S) {<br>
+ case MCDisassembler::Fail:<br>
+ case MCDisassembler::SoftFail:<br>
+ // FIXME: Do something different for soft failure modes?<br>
return 0;<br>
+ case MCDisassembler::Success: {<br>
+ SmallVector<char, 64> InsnStr;<br>
+ raw_svector_ostream OS(InsnStr);<br>
+ IP->printInst(&Inst, OS);<br>
+ OS.flush();<br>
<br>
- SmallVector<char, 64> InsnStr;<br>
- raw_svector_ostream OS(InsnStr);<br>
- IP->printInst(&Inst, OS);<br>
- OS.flush();<br>
+ assert(OutStringSize != 0 && "Output buffer cannot be zero size");<br>
+ size_t OutputSize = std::min(OutStringSize-1, InsnStr.size());<br>
+ std::memcpy(OutString, InsnStr.data(), OutputSize);<br>
+ OutString[OutputSize] = '\0'; // Terminate string.<br>
<br>
- assert(OutStringSize != 0 && "Output buffer cannot be zero size");<br>
- size_t OutputSize = std::min(OutStringSize-1, InsnStr.size());<br>
- std::memcpy(OutString, InsnStr.data(), OutputSize);<br>
- OutString[OutputSize] = '\0'; // Terminate string.<br>
-<br>
- return Size;<br>
+ return Size;<br>
+ }<br>
+ }<br>
}<br>
<br>
Modified: llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp?rev=138948&r1=138947&r2=138948&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp?rev=138948&r1=138947&r2=138948&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp (original)<br>
+++ llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp Thu Sep 1 13:02:14 2011<br>
@@ -239,14 +239,19 @@<br>
MCInst* inst = new MCInst;<br>
uint64_t byteSize;<br>
<br>
- if (!Disassembler->getInstruction(*inst,<br>
- byteSize,<br>
- memoryObject,<br>
- address,<br>
- ErrorStream)) {<br>
+ MCDisassembler::DecodeStatus S;<br>
+ S = Disassembler->getInstruction(*inst,<br>
+ byteSize,<br>
+ memoryObject,<br>
+ address,<br>
+ ErrorStream);<br>
+ switch (S) {<br>
+ case MCDisassembler::Fail:<br>
+ case MCDisassembler::SoftFail:<br>
+ // FIXME: Do something different on soft failure mode?<br>
delete inst;<br>
return NULL;<br>
- } else {<br>
+ case MCDisassembler::Success: {<br>
const llvm::EDInstInfo *thisInstInfo = NULL;<br>
<br>
if (InstInfos) {<br>
@@ -256,6 +261,7 @@<br>
EDInst* sdInst = new EDInst(inst, byteSize, *this, thisInstInfo);<br>
return sdInst;<br>
}<br>
+ }<br>
}<br>
<br>
void EDDisassembler::initMaps(const MCRegisterInfo ®isterInfo) {<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=138948&r1=138947&r2=138948&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=138948&r1=138947&r2=138948&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Thu Sep 1 13:02:14 2011<br>
@@ -24,221 +24,223 @@<br>
#include "llvm/Support/TargetRegistry.h"<br>
#include "llvm/Support/raw_ostream.h"<br>
<br>
-// Pull DecodeStatus and its enum values into the global namespace.<br>
-typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;<br>
-#define Success llvm::MCDisassembler::Success<br>
-#define Unpredictable llvm::MCDisassembler::SoftFail<br>
-#define Fail llvm::MCDisassembler::Fail<br>
-<br>
-// Helper macro to perform setwise reduction of the current running status<br>
-// and another status, and return if the new status is Fail.<br>
-#define CHECK(S,X) do { \<br>
- S = (DecodeStatus) ((int)S & (X)); \<br>
- if (S == Fail) return Fail; \<br>
- } while(0)<br>
+using namespace llvm;<br>
+<br>
+static bool Check(MCDisassembler::DecodeStatus &Out, MCDisassembler::DecodeStatus In) {<br>
+ switch (In) {<br>
+ case MCDisassembler::Success:<br>
+ // Out stays the same.<br>
+ return true;<br>
+ case MCDisassembler::SoftFail:<br>
+ Out = In;<br>
+ return true;<br>
+ case MCDisassembler::Fail:<br>
+ Out = In;<br>
+ return false;<br>
+ }<br>
+ return false;<br>
+}<br>
<br>
// Forward declare these because the autogenerated code will reference them.<br>
// Definitions are further down.<br>
-static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,<br>
+static MCDisassembler::DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,<br>
+static MCDisassembler::DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,<br>
unsigned RegNo, uint64_t Address,<br>
const void *Decoder);<br>
-static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,<br>
+static MCDisassembler::DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,<br>
+static MCDisassembler::DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,<br>
+static MCDisassembler::DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,<br>
+static MCDisassembler::DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,<br>
+static MCDisassembler::DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,<br>
+static MCDisassembler::DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,<br>
+static MCDisassembler::DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,<br>
unsigned RegNo,<br>
uint64_t Address,<br>
const void *Decoder);<br>
-static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,<br>
+static MCDisassembler::DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,<br>
uint64_t Address, const void *Decoder);<br>
<br>
-static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
<br>
-static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,<br>
+static MCDisassembler::DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,<br>
unsigned Insn,<br>
uint64_t Address,<br>
const void *Decoder);<br>
-static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder);<br>
<br>
-static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,<br>
+static MCDisassembler::DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,<br>
unsigned Insn,<br>
uint64_t Adddress,<br>
const void *Decoder);<br>
-static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder);<br>
<br>
-static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,<br>
+static MCDisassembler::DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,<br>
+static MCDisassembler::DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,<br>
+static MCDisassembler::DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,<br>
+static MCDisassembler::DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
<br>
#include "ARMGenDisassemblerTables.inc"<br>
#include "ARMGenInstrInfo.inc"<br>
#include "ARMGenEDInfo.inc"<br>
<br>
-using namespace llvm;<br>
-<br>
static MCDisassembler *createARMDisassembler(const Target &T) {<br>
return new ARMDisassembler;<br>
}<br>
@@ -255,7 +257,7 @@<br>
return instInfoARM;<br>
}<br>
<br>
-DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,<br>
+MCDisassembler::DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,<br>
const MemoryObject &Region,<br>
uint64_t Address,<br>
raw_ostream &os) const {<br>
@@ -264,7 +266,7 @@<br>
// We want to read exactly 4 bytes of data.<br>
if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {<br>
Size = 0;<br>
- return Fail;<br>
+ return MCDisassembler::Fail;<br>
}<br>
<br>
// Encoded as a small-endian 32-bit word in the stream.<br>
@@ -274,8 +276,8 @@<br>
(bytes[0] << 0);<br>
<br>
// Calling the auto-generated decoder function.<br>
- DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this);<br>
- if (result != Fail) {<br>
+ MCDisassembler::DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this);<br>
+ if (result != MCDisassembler::Fail) {<br>
Size = 4;<br>
return result;<br>
}<br>
@@ -285,7 +287,7 @@<br>
// fact that we fail to encode a few instructions properly for Thumb.<br>
MI.clear();<br>
result = decodeCommonInstruction32(MI, insn, Address, this);<br>
- if (result != Fail) {<br>
+ if (result != MCDisassembler::Fail) {<br>
Size = 4;<br>
return result;<br>
}<br>
@@ -294,45 +296,45 @@<br>
// and Thumb modes.<br>
MI.clear();<br>
result = decodeVFPInstruction32(MI, insn, Address, this);<br>
- if (result != Fail) {<br>
+ if (result != MCDisassembler::Fail) {<br>
Size = 4;<br>
return result;<br>
}<br>
<br>
MI.clear();<br>
result = decodeNEONDataInstruction32(MI, insn, Address, this);<br>
- if (result != Fail) {<br>
+ if (result != MCDisassembler::Fail) {<br>
Size = 4;<br>
// Add a fake predicate operand, because we share these instruction<br>
// definitions with Thumb2 where these instructions are predicable.<br>
- if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail;<br>
+ if (!DecodePredicateOperand(MI, 0xE, Address, this)) return MCDisassembler::Fail;<br>
return result;<br>
}<br>
<br>
MI.clear();<br>
result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this);<br>
- if (result != Fail) {<br>
+ if (result != MCDisassembler::Fail) {<br>
Size = 4;<br>
// Add a fake predicate operand, because we share these instruction<br>
// definitions with Thumb2 where these instructions are predicable.<br>
- if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail;<br>
+ if (!DecodePredicateOperand(MI, 0xE, Address, this)) return MCDisassembler::Fail;<br>
return result;<br>
}<br>
<br>
MI.clear();<br>
result = decodeNEONDupInstruction32(MI, insn, Address, this);<br>
- if (result != Fail) {<br>
+ if (result != MCDisassembler::Fail) {<br>
Size = 4;<br>
// Add a fake predicate operand, because we share these instruction<br>
// definitions with Thumb2 where these instructions are predicable.<br>
- if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail;<br>
+ if (!DecodePredicateOperand(MI, 0xE, Address, this)) return MCDisassembler::Fail;<br>
return result;<br>
}<br>
<br>
MI.clear();<br>
<br>
Size = 0;<br>
- return Fail;<br>
+ return MCDisassembler::Fail;<br>
}<br>
<br>
namespace llvm {<br>
@@ -438,7 +440,7 @@<br>
}<br>
}<br>
<br>
-DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,<br>
+MCDisassembler::DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,<br>
const MemoryObject &Region,<br>
uint64_t Address,<br>
raw_ostream &os) const {<br>
@@ -447,12 +449,12 @@<br>
// We want to read exactly 2 bytes of data.<br>
if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {<br>
Size = 0;<br>
- return Fail;<br>
+ return MCDisassembler::Fail;<br>
}<br>
<br>
uint16_t insn16 = (bytes[1] << 8) | bytes[0];<br>
- DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this);<br>
- if (result != Fail) {<br>
+ MCDisassembler::DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this);<br>
+ if (result != MCDisassembler::Fail) {<br>
Size = 2;<br>
AddThumbPredicate(MI);<br>
return result;<br>
@@ -470,7 +472,7 @@<br>
<br>
MI.clear();<br>
result = decodeThumb2Instruction16(MI, insn16, Address, this);<br>
- if (result != Fail) {<br>
+ if (result != MCDisassembler::Fail) {<br>
Size = 2;<br>
AddThumbPredicate(MI);<br>
<br>
@@ -501,7 +503,7 @@<br>
// We want to read exactly 4 bytes of data.<br>
if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {<br>
Size = 0;<br>
- return Fail;<br>
+ return MCDisassembler::Fail;<br>
}<br>
<br>
uint32_t insn32 = (bytes[3] << 8) |<br>
@@ -510,7 +512,7 @@<br>
(bytes[0] << 16);<br>
MI.clear();<br>
result = decodeThumbInstruction32(MI, insn32, Address, this);<br>
- if (result != Fail) {<br>
+ if (result != MCDisassembler::Fail) {<br>
Size = 4;<br>
bool InITBlock = ITBlock.size();<br>
AddThumbPredicate(MI);<br>
@@ -520,7 +522,7 @@<br>
<br>
MI.clear();<br>
result = decodeThumb2Instruction32(MI, insn32, Address, this);<br>
- if (result != Fail) {<br>
+ if (result != MCDisassembler::Fail) {<br>
Size = 4;<br>
AddThumbPredicate(MI);<br>
return result;<br>
@@ -528,7 +530,7 @@<br>
<br>
MI.clear();<br>
result = decodeCommonInstruction32(MI, insn32, Address, this);<br>
- if (result != Fail) {<br>
+ if (result != MCDisassembler::Fail) {<br>
Size = 4;<br>
AddThumbPredicate(MI);<br>
return result;<br>
@@ -536,7 +538,7 @@<br>
<br>
MI.clear();<br>
result = decodeVFPInstruction32(MI, insn32, Address, this);<br>
- if (result != Fail) {<br>
+ if (result != MCDisassembler::Fail) {<br>
Size = 4;<br>
UpdateThumbVFPPredicate(MI);<br>
return result;<br>
@@ -544,7 +546,7 @@<br>
<br>
MI.clear();<br>
result = decodeNEONDupInstruction32(MI, insn32, Address, this);<br>
- if (result != Fail) {<br>
+ if (result != MCDisassembler::Fail) {<br>
Size = 4;<br>
AddThumbPredicate(MI);<br>
return result;<br>
@@ -556,7 +558,7 @@<br>
NEONLdStInsn &= 0xF0FFFFFF;<br>
NEONLdStInsn |= 0x04000000;<br>
result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this);<br>
- if (result != Fail) {<br>
+ if (result != MCDisassembler::Fail) {<br>
Size = 4;<br>
AddThumbPredicate(MI);<br>
return result;<br>
@@ -570,7 +572,7 @@<br>
NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24<br>
NEONDataInsn |= 0x12000000; // Set bits 28 and 25<br>
result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this);<br>
- if (result != Fail) {<br>
+ if (result != MCDisassembler::Fail) {<br>
Size = 4;<br>
AddThumbPredicate(MI);<br>
return result;<br>
@@ -578,7 +580,7 @@<br>
}<br>
<br>
Size = 0;<br>
- return Fail;<br>
+ return MCDisassembler::Fail;<br>
}<br>
<br>
<br>
@@ -596,31 +598,31 @@<br>
ARM::R12, ARM::SP, ARM::LR, ARM::PC<br>
};<br>
<br>
-static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,<br>
+static MCDisassembler::DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,<br>
uint64_t Address, const void *Decoder) {<br>
if (RegNo > 15)<br>
- return Fail;<br>
+ return MCDisassembler::Fail;<br>
<br>
unsigned Register = GPRDecoderTable[RegNo];<br>
Inst.addOperand(MCOperand::CreateReg(Register));<br>
- return Success;<br>
+ return MCDisassembler::Success;<br>
}<br>
<br>
-static DecodeStatus<br>
+static MCDisassembler::DecodeStatus<br>
DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,<br>
uint64_t Address, const void *Decoder) {<br>
- if (RegNo == 15) return Fail;<br>
+ if (RegNo == 15) return MCDisassembler::Fail;<br>
return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);<br>
}<br>
<br>
-static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,<br>
+static MCDisassembler::DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,<br>
uint64_t Address, const void *Decoder) {<br>
if (RegNo > 7)<br>
- return Fail;<br>
+ return MCDisassembler::Fail;<br>
return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);<br>
}<br>
<br>
-static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,<br>
+static MCDisassembler::DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,<br>
uint64_t Address, const void *Decoder) {<br>
unsigned Register = 0;<br>
switch (RegNo) {<br>
@@ -643,16 +645,16 @@<br>
Register = ARM::R12;<br>
break;<br>
default:<br>
- return Fail;<br>
+ return MCDisassembler::Fail;<br>
}<br>
<br>
Inst.addOperand(MCOperand::CreateReg(Register));<br>
- return Success;<br>
+ return MCDisassembler::Success;<br>
}<br>
<br>
-static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,<br>
+static MCDisassembler::DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,<br>
uint64_t Address, const void *Decoder) {<br>
- if (RegNo == 13 || RegNo == 15) return Fail;<br>
+ if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;<br>
return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);<br>
}<br>
<br>
@@ -667,14 +669,14 @@<br>
ARM::S28, ARM::S29, ARM::S30, ARM::S31<br>
};<br>
<br>
-static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,<br>
+static MCDisassembler::DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,<br>
uint64_t Address, const void *Decoder) {<br>
if (RegNo > 31)<br>
- return Fail;<br>
+ return MCDisassembler::Fail;<br>
<br>
unsigned Register = SPRDecoderTable[RegNo];<br>
Inst.addOperand(MCOperand::CreateReg(Register));<br>
- return Success;<br>
+ return MCDisassembler::Success;<br>
}<br>
<br>
static const unsigned DPRDecoderTable[] = {<br>
@@ -688,28 +690,28 @@<br>
ARM::D28, ARM::D29, ARM::D30, ARM::D31<br>
};<br>
<br>
-static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,<br>
+static MCDisassembler::DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,<br>
uint64_t Address, const void *Decoder) {<br>
if (RegNo > 31)<br>
- return Fail;<br>
+ return MCDisassembler::Fail;<br>
<br>
unsigned Register = DPRDecoderTable[RegNo];<br>
Inst.addOperand(MCOperand::CreateReg(Register));<br>
- return Success;<br>
+ return MCDisassembler::Success;<br>
}<br>
<br>
-static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,<br>
+static MCDisassembler::DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,<br>
uint64_t Address, const void *Decoder) {<br>
if (RegNo > 7)<br>
- return Fail;<br>
+ return MCDisassembler::Fail;<br>
return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);<br>
}<br>
<br>
-static DecodeStatus<br>
+static MCDisassembler::DecodeStatus<br>
DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,<br>
uint64_t Address, const void *Decoder) {<br>
if (RegNo > 15)<br>
- return Fail;<br>
+ return MCDisassembler::Fail;<br>
return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);<br>
}<br>
<br>
@@ -721,59 +723,59 @@<br>
};<br>
<br>
<br>
-static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,<br>
+static MCDisassembler::DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,<br>
uint64_t Address, const void *Decoder) {<br>
if (RegNo > 31)<br>
- return Fail;<br>
+ return MCDisassembler::Fail;<br>
RegNo >>= 1;<br>
<br>
unsigned Register = QPRDecoderTable[RegNo];<br>
Inst.addOperand(MCOperand::CreateReg(Register));<br>
- return Success;<br>
+ return MCDisassembler::Success;<br>
}<br>
<br>
-static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder) {<br>
- if (Val == 0xF) return Fail;<br>
+ if (Val == 0xF) return MCDisassembler::Fail;<br>
// AL predicate is not allowed on Thumb1 branches.<br>
if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)<br>
- return Fail;<br>
+ return MCDisassembler::Fail;<br>
Inst.addOperand(MCOperand::CreateImm(Val));<br>
if (Val == ARMCC::AL) {<br>
Inst.addOperand(MCOperand::CreateReg(0));<br>
} else<br>
Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));<br>
- return Success;<br>
+ return MCDisassembler::Success;<br>
}<br>
<br>
-static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder) {<br>
if (Val)<br>
Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));<br>
else<br>
Inst.addOperand(MCOperand::CreateReg(0));<br>
- return Success;<br>
+ return MCDisassembler::Success;<br>
}<br>
<br>
-static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder) {<br>
uint32_t imm = Val & 0xFF;<br>
uint32_t rot = (Val & 0xF00) >> 7;<br>
uint32_t rot_imm = (imm >> rot) | (imm << (32-rot));<br>
Inst.addOperand(MCOperand::CreateImm(rot_imm));<br>
- return Success;<br>
+ return MCDisassembler::Success;<br>
}<br>
<br>
-static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Rm = fieldFromInstruction32(Val, 0, 4);<br>
unsigned type = fieldFromInstruction32(Val, 5, 2);<br>
unsigned imm = fieldFromInstruction32(Val, 7, 5);<br>
<br>
// Register-immediate<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;<br>
<br>
ARM_AM::ShiftOpc Shift = ARM_AM::lsl;<br>
switch (type) {<br>
@@ -800,17 +802,17 @@<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Rm = fieldFromInstruction32(Val, 0, 4);<br>
unsigned type = fieldFromInstruction32(Val, 5, 2);<br>
unsigned Rs = fieldFromInstruction32(Val, 8, 4);<br>
<br>
// Register-register<br>
- CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder));<br>
- CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) return MCDisassembler::Fail;<br>
<br>
ARM_AM::ShiftOpc Shift = ARM_AM::lsl;<br>
switch (type) {<br>
@@ -833,52 +835,52 @@<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
// Empty register lists are not allowed.<br>
- if (CountPopulation_32(Val) == 0) return Fail;<br>
+ if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;<br>
for (unsigned i = 0; i < 16; ++i) {<br>
if (Val & (1 << i)) {<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) return MCDisassembler::Fail;<br>
}<br>
}<br>
<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Vd = fieldFromInstruction32(Val, 8, 4);<br>
unsigned regs = Val & 0xFF;<br>
<br>
- CHECK(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder));<br>
+ if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) return MCDisassembler::Fail;<br>
for (unsigned i = 0; i < (regs - 1); ++i) {<br>
- CHECK(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder));<br>
+ if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) return MCDisassembler::Fail;<br>
}<br>
<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Vd = fieldFromInstruction32(Val, 8, 4);<br>
unsigned regs = (Val & 0xFF) / 2;<br>
<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder));<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) return MCDisassembler::Fail;<br>
for (unsigned i = 0; i < (regs - 1); ++i) {<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder));<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) return MCDisassembler::Fail;<br>
}<br>
<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder) {<br>
// This operand encodes a mask of contiguous zeros between a specified MSB<br>
// and LSB. To decode it, we create the mask of all bits MSB-and-lower,<br>
@@ -890,12 +892,12 @@<br>
uint32_t msb_mask = (1 << (msb+1)) - 1;<br>
uint32_t lsb_mask = (1 << lsb) - 1;<br>
Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));<br>
- return Success;<br>
+ return MCDisassembler::Success;<br>
}<br>
<br>
-static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned pred = fieldFromInstruction32(Insn, 28, 4);<br>
unsigned CRd = fieldFromInstruction32(Insn, 12, 4);<br>
@@ -922,7 +924,7 @@<br>
case ARM::STCL_POST:<br>
case ARM::STCL_OPTION:<br>
if (coproc == 0xA || coproc == 0xB)<br>
- return Fail;<br>
+ return MCDisassembler::Fail;<br>
break;<br>
default:<br>
break;<br>
@@ -930,7 +932,7 @@<br>
<br>
Inst.addOperand(MCOperand::CreateImm(coproc));<br>
Inst.addOperand(MCOperand::CreateImm(CRd));<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
switch (Inst.getOpcode()) {<br>
case ARM::LDC_OPTION:<br>
case ARM::LDCL_OPTION:<br>
@@ -1003,7 +1005,7 @@<br>
case ARM::STCL_PRE:<br>
case ARM::STCL_POST:<br>
case ARM::STCL_OPTION:<br>
- CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));<br>
+ if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler::Fail;<br>
break;<br>
default:<br>
break;<br>
@@ -1012,10 +1014,10 @@<br>
return S;<br>
}<br>
<br>
-static DecodeStatus<br>
+static MCDisassembler::DecodeStatus<br>
DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);<br>
unsigned Rt = fieldFromInstruction32(Insn, 12, 4);<br>
@@ -1036,13 +1038,13 @@<br>
case ARM::STRT_POST_IMM:<br>
case ARM::STRBT_POST_REG:<br>
case ARM::STRBT_POST_IMM:<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
break;<br>
default:<br>
break;<br>
}<br>
<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail;<br>
<br>
// On loads, the writeback operand comes after Rt.<br>
switch (Inst.getOpcode()) {<br>
@@ -1054,13 +1056,13 @@<br>
case ARM::LDRBT_POST_IMM:<br>
case ARM::LDRT_POST_REG:<br>
case ARM::LDRT_POST_IMM:<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
break;<br>
default:<br>
break;<br>
}<br>
<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
<br>
ARM_AM::AddrOpc Op = ARM_AM::add;<br>
if (!fieldFromInstruction32(Insn, 23, 1))<br>
@@ -1073,10 +1075,10 @@<br>
else if (!P && writeback)<br>
idx_mode = ARMII::IndexModePost;<br>
<br>
- if (writeback && (Rn == 15 || Rn == Rt)) S = Unpredictable; // UNPREDICTABLE<br>
+ if (writeback && (Rn == 15 || Rn == Rt)) S = MCDisassembler::SoftFail; // UNPREDICTABLE<br>
<br>
if (reg) {<br>
- CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;<br>
ARM_AM::ShiftOpc Opc = ARM_AM::lsl;<br>
switch( fieldFromInstruction32(Insn, 5, 2)) {<br>
case 0:<br>
@@ -1092,7 +1094,7 @@<br>
Opc = ARM_AM::ror;<br>
break;<br>
default:<br>
- return Fail;<br>
+ return MCDisassembler::Fail;<br>
}<br>
unsigned amt = fieldFromInstruction32(Insn, 7, 5);<br>
unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);<br>
@@ -1104,14 +1106,14 @@<br>
Inst.addOperand(MCOperand::CreateImm(tmp));<br>
}<br>
<br>
- CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));<br>
+ if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler::Fail;<br>
<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Rn = fieldFromInstruction32(Val, 13, 4);<br>
unsigned Rm = fieldFromInstruction32(Val, 0, 4);<br>
@@ -1135,8 +1137,8 @@<br>
break;<br>
}<br>
<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;<br>
unsigned shift;<br>
if (U)<br>
shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);<br>
@@ -1147,10 +1149,10 @@<br>
return S;<br>
}<br>
<br>
-static DecodeStatus<br>
+static MCDisassembler::DecodeStatus<br>
DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Rt = fieldFromInstruction32(Insn, 12, 4);<br>
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);<br>
@@ -1172,7 +1174,7 @@<br>
case ARM::LDRD:<br>
case ARM::LDRD_PRE:<br>
case ARM::LDRD_POST:<br>
- if (Rt & 0x1) return Fail;<br>
+ if (Rt & 0x1) return MCDisassembler::Fail;<br>
break;<br>
default:<br>
break;<br>
@@ -1192,14 +1194,14 @@<br>
case ARM::STRH:<br>
case ARM::STRH_PRE:<br>
case ARM::STRH_POST:<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
break;<br>
default:<br>
break;<br>
}<br>
}<br>
<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail;<br>
switch (Inst.getOpcode()) {<br>
case ARM::STRD:<br>
case ARM::STRD_PRE:<br>
@@ -1207,7 +1209,7 @@<br>
case ARM::LDRD:<br>
case ARM::LDRD_PRE:<br>
case ARM::LDRD_POST:<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) return MCDisassembler::Fail;<br>
break;<br>
default:<br>
break;<br>
@@ -1230,31 +1232,31 @@<br>
case ARM::LDRSB_POST:<br>
case ARM::LDRHTr:<br>
case ARM::LDRSBTr:<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
break;<br>
default:<br>
break;<br>
}<br>
}<br>
<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
<br>
if (type) {<br>
Inst.addOperand(MCOperand::CreateReg(0));<br>
Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));<br>
} else {<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;<br>
Inst.addOperand(MCOperand::CreateImm(U));<br>
}<br>
<br>
- CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));<br>
+ if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler::Fail;<br>
<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);<br>
unsigned mode = fieldFromInstruction32(Insn, 23, 2);<br>
@@ -1275,15 +1277,15 @@<br>
}<br>
<br>
Inst.addOperand(MCOperand::CreateImm(mode));<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,<br>
+static MCDisassembler::DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,<br>
unsigned Insn,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);<br>
unsigned pred = fieldFromInstruction32(Insn, 28, 4);<br>
@@ -1340,7 +1342,7 @@<br>
Inst.setOpcode(ARM::SRSIB_UPD);<br>
break;<br>
default:<br>
- CHECK(S, Fail);<br>
+ if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;<br>
}<br>
<br>
// For stores (which become SRS's, the only operand is the mode.<br>
@@ -1353,29 +1355,29 @@<br>
return DecodeRFEInstruction(Inst, Insn, Address, Decoder);<br>
}<br>
<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); // Tied<br>
- CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));<br>
- CHECK(S, DecodeRegListOperand(Inst, reglist, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; // Tied<br>
+ if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) return MCDisassembler::Fail;<br>
<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder) {<br>
unsigned imod = fieldFromInstruction32(Insn, 18, 2);<br>
unsigned M = fieldFromInstruction32(Insn, 17, 1);<br>
unsigned iflags = fieldFromInstruction32(Insn, 6, 3);<br>
unsigned mode = fieldFromInstruction32(Insn, 0, 5);<br>
<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
// imod == '01' --> UNPREDICTABLE<br>
// NOTE: Even though this is technically UNPREDICTABLE, we choose to<br>
// return failure here. The '01' imod value is unprintable, so there's<br>
// nothing useful we could do even if we returned UNPREDICTABLE.<br>
<br>
- if (imod == 1) CHECK(S, Fail);<br>
+ if (imod == 1) return MCDisassembler::Fail;<br>
<br>
if (imod && M) {<br>
Inst.setOpcode(ARM::CPS3p);<br>
@@ -1386,36 +1388,36 @@<br>
Inst.setOpcode(ARM::CPS2p);<br>
Inst.addOperand(MCOperand::CreateImm(imod));<br>
Inst.addOperand(MCOperand::CreateImm(iflags));<br>
- if (mode) CHECK(S, Unpredictable);<br>
+ if (mode) S = MCDisassembler::SoftFail;<br>
} else if (!imod && M) {<br>
Inst.setOpcode(ARM::CPS1p);<br>
Inst.addOperand(MCOperand::CreateImm(mode));<br>
- if (iflags) CHECK(S, Unpredictable);<br>
+ if (iflags) S = MCDisassembler::SoftFail;<br>
} else {<br>
// imod == '00' && M == '0' --> UNPREDICTABLE<br>
Inst.setOpcode(ARM::CPS1p);<br>
Inst.addOperand(MCOperand::CreateImm(mode));<br>
- CHECK(S, Unpredictable);<br>
+ S = MCDisassembler::SoftFail;<br>
}<br>
<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder) {<br>
unsigned imod = fieldFromInstruction32(Insn, 9, 2);<br>
unsigned M = fieldFromInstruction32(Insn, 8, 1);<br>
unsigned iflags = fieldFromInstruction32(Insn, 5, 3);<br>
unsigned mode = fieldFromInstruction32(Insn, 0, 5);<br>
<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
// imod == '01' --> UNPREDICTABLE<br>
// NOTE: Even though this is technically UNPREDICTABLE, we choose to<br>
// return failure here. The '01' imod value is unprintable, so there's<br>
// nothing useful we could do even if we returned UNPREDICTABLE.<br>
<br>
- if (imod == 1) CHECK(S, Fail);<br>
+ if (imod == 1) return MCDisassembler::Fail;<br>
<br>
if (imod && M) {<br>
Inst.setOpcode(ARM::t2CPS3p);<br>
@@ -1426,25 +1428,25 @@<br>
Inst.setOpcode(ARM::t2CPS2p);<br>
Inst.addOperand(MCOperand::CreateImm(imod));<br>
Inst.addOperand(MCOperand::CreateImm(iflags));<br>
- if (mode) CHECK(S, Unpredictable);<br>
+ if (mode) S = MCDisassembler::SoftFail;<br>
} else if (!imod && M) {<br>
Inst.setOpcode(ARM::t2CPS1p);<br>
Inst.addOperand(MCOperand::CreateImm(mode));<br>
- if (iflags) CHECK(S, Unpredictable);<br>
+ if (iflags) S = MCDisassembler::SoftFail;<br>
} else {<br>
// imod == '00' && M == '0' --> UNPREDICTABLE<br>
Inst.setOpcode(ARM::t2CPS1p);<br>
Inst.addOperand(MCOperand::CreateImm(mode));<br>
- CHECK(S, Unpredictable);<br>
+ S = MCDisassembler::SoftFail;<br>
}<br>
<br>
return S;<br>
}<br>
<br>
<br>
-static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Rd = fieldFromInstruction32(Insn, 16, 4);<br>
unsigned Rn = fieldFromInstruction32(Insn, 0, 4);<br>
@@ -1455,25 +1457,25 @@<br>
if (pred == 0xF)<br>
return DecodeCPSInstruction(Inst, Insn, Address, Decoder);<br>
<br>
- CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder));<br>
- CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder));<br>
- CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder));<br>
- CHECK(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) return MCDisassembler::Fail;<br>
<br>
- CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));<br>
+ if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler::Fail;<br>
<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned add = fieldFromInstruction32(Val, 12, 1);<br>
unsigned imm = fieldFromInstruction32(Val, 0, 12);<br>
unsigned Rn = fieldFromInstruction32(Val, 13, 4);<br>
<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
<br>
if (!add) imm *= -1;<br>
if (imm == 0 && !add) imm = INT32_MIN;<br>
@@ -1482,15 +1484,15 @@<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Rn = fieldFromInstruction32(Val, 9, 4);<br>
unsigned U = fieldFromInstruction32(Val, 8, 1);<br>
unsigned imm = fieldFromInstruction32(Val, 0, 8);<br>
<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
<br>
if (U)<br>
Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));<br>
@@ -1500,15 +1502,15 @@<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder) {<br>
return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);<br>
}<br>
<br>
-static DecodeStatus<br>
+static MCDisassembler::DecodeStatus<br>
DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned pred = fieldFromInstruction32(Insn, 28, 4);<br>
unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;<br>
@@ -1521,26 +1523,26 @@<br>
}<br>
<br>
Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));<br>
- CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));<br>
+ if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler::Fail;<br>
<br>
return S;<br>
}<br>
<br>
<br>
-static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder) {<br>
Inst.addOperand(MCOperand::CreateImm(64 - Val));<br>
- return Success;<br>
+ return MCDisassembler::Success;<br>
}<br>
<br>
-static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Rm = fieldFromInstruction32(Val, 0, 4);<br>
unsigned align = fieldFromInstruction32(Val, 4, 2);<br>
<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;<br>
if (!align)<br>
Inst.addOperand(MCOperand::CreateImm(0));<br>
else<br>
@@ -1549,9 +1551,9 @@<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Rd = fieldFromInstruction32(Insn, 12, 4);<br>
Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;<br>
@@ -1561,7 +1563,7 @@<br>
unsigned Rm = fieldFromInstruction32(Insn, 0, 4);<br>
<br>
// First output register<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;<br>
<br>
// Second output register<br>
switch (Inst.getOpcode()) {<br>
@@ -1613,7 +1615,7 @@<br>
case ARM::VLD4d8_UPD:<br>
case ARM::VLD4d16_UPD:<br>
case ARM::VLD4d32_UPD:<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder));<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) return MCDisassembler::Fail;<br>
break;<br>
case ARM::VLD2b8:<br>
case ARM::VLD2b16:<br>
@@ -1633,7 +1635,7 @@<br>
case ARM::VLD4q8_UPD:<br>
case ARM::VLD4q16_UPD:<br>
case ARM::VLD4q32_UPD:<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) return MCDisassembler::Fail;<br>
default:<br>
break;<br>
}<br>
@@ -1674,7 +1676,7 @@<br>
case ARM::VLD4d8_UPD:<br>
case ARM::VLD4d16_UPD:<br>
case ARM::VLD4d32_UPD:<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) return MCDisassembler::Fail;<br>
break;<br>
case ARM::VLD3q8:<br>
case ARM::VLD3q16:<br>
@@ -1688,7 +1690,7 @@<br>
case ARM::VLD4q8_UPD:<br>
case ARM::VLD4q16_UPD:<br>
case ARM::VLD4q32_UPD:<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder));<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) return MCDisassembler::Fail;<br>
break;<br>
default:<br>
break;<br>
@@ -1716,7 +1718,7 @@<br>
case ARM::VLD4d8_UPD:<br>
case ARM::VLD4d16_UPD:<br>
case ARM::VLD4d32_UPD:<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder));<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) return MCDisassembler::Fail;<br>
break;<br>
case ARM::VLD4q8:<br>
case ARM::VLD4q16:<br>
@@ -1724,7 +1726,7 @@<br>
case ARM::VLD4q8_UPD:<br>
case ARM::VLD4q16_UPD:<br>
case ARM::VLD4q32_UPD:<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder));<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) return MCDisassembler::Fail;<br>
break;<br>
default:<br>
break;<br>
@@ -1769,28 +1771,28 @@<br>
case ARM::VLD4q8_UPD:<br>
case ARM::VLD4q16_UPD:<br>
case ARM::VLD4q32_UPD:<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) return MCDisassembler::Fail;<br>
break;<br>
default:<br>
break;<br>
}<br>
<br>
// AddrMode6 Base (register+alignment)<br>
- CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder));<br>
+ if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
<br>
// AddrMode6 Offset (register)<br>
if (Rm == 0xD)<br>
Inst.addOperand(MCOperand::CreateReg(0));<br>
else if (Rm != 0xF) {<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;<br>
}<br>
<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Rd = fieldFromInstruction32(Insn, 12, 4);<br>
Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;<br>
@@ -1838,24 +1840,24 @@<br>
case ARM::VST4q8_UPD:<br>
case ARM::VST4q16_UPD:<br>
case ARM::VST4q32_UPD:<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) return MCDisassembler::Fail;<br>
break;<br>
default:<br>
break;<br>
}<br>
<br>
// AddrMode6 Base (register+alignment)<br>
- CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder));<br>
+ if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
<br>
// AddrMode6 Offset (register)<br>
if (Rm == 0xD)<br>
Inst.addOperand(MCOperand::CreateReg(0));<br>
else if (Rm != 0xF) {<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;<br>
}<br>
<br>
// First input register<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;<br>
<br>
// Second input register<br>
switch (Inst.getOpcode()) {<br>
@@ -1907,7 +1909,7 @@<br>
case ARM::VST4d8_UPD:<br>
case ARM::VST4d16_UPD:<br>
case ARM::VST4d32_UPD:<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder));<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) return MCDisassembler::Fail;<br>
break;<br>
case ARM::VST2b8:<br>
case ARM::VST2b16:<br>
@@ -1927,7 +1929,7 @@<br>
case ARM::VST4q8_UPD:<br>
case ARM::VST4q16_UPD:<br>
case ARM::VST4q32_UPD:<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) return MCDisassembler::Fail;<br>
break;<br>
default:<br>
break;<br>
@@ -1969,7 +1971,7 @@<br>
case ARM::VST4d8_UPD:<br>
case ARM::VST4d16_UPD:<br>
case ARM::VST4d32_UPD:<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) return MCDisassembler::Fail;<br>
break;<br>
case ARM::VST3q8:<br>
case ARM::VST3q16:<br>
@@ -1983,7 +1985,7 @@<br>
case ARM::VST4q8_UPD:<br>
case ARM::VST4q16_UPD:<br>
case ARM::VST4q32_UPD:<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder));<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) return MCDisassembler::Fail;<br>
break;<br>
default:<br>
break;<br>
@@ -2011,7 +2013,7 @@<br>
case ARM::VST4d8_UPD:<br>
case ARM::VST4d16_UPD:<br>
case ARM::VST4d32_UPD:<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder));<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) return MCDisassembler::Fail;<br>
break;<br>
case ARM::VST4q8:<br>
case ARM::VST4q16:<br>
@@ -2019,7 +2021,7 @@<br>
case ARM::VST4q8_UPD:<br>
case ARM::VST4q16_UPD:<br>
case ARM::VST4q32_UPD:<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder));<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) return MCDisassembler::Fail;<br>
break;<br>
default:<br>
break;<br>
@@ -2028,9 +2030,9 @@<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Rd = fieldFromInstruction32(Insn, 12, 4);<br>
Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;<br>
@@ -2042,29 +2044,29 @@<br>
<br>
align *= (1 << size);<br>
<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;<br>
if (regs == 2) {<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder));<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) return MCDisassembler::Fail;<br>
}<br>
if (Rm != 0xF) {<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
}<br>
<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
Inst.addOperand(MCOperand::CreateImm(align));<br>
<br>
if (Rm == 0xD)<br>
Inst.addOperand(MCOperand::CreateReg(0));<br>
else if (Rm != 0xF) {<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;<br>
}<br>
<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Rd = fieldFromInstruction32(Insn, 12, 4);<br>
Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;<br>
@@ -2075,27 +2077,27 @@<br>
unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;<br>
align *= 2*size;<br>
<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder));<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) return MCDisassembler::Fail;<br>
if (Rm != 0xF) {<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
}<br>
<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
Inst.addOperand(MCOperand::CreateImm(align));<br>
<br>
if (Rm == 0xD)<br>
Inst.addOperand(MCOperand::CreateReg(0));<br>
else if (Rm != 0xF) {<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;<br>
}<br>
<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Rd = fieldFromInstruction32(Insn, 12, 4);<br>
Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;<br>
@@ -2103,28 +2105,28 @@<br>
unsigned Rm = fieldFromInstruction32(Insn, 0, 4);<br>
unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;<br>
<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder));<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder));<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) return MCDisassembler::Fail;<br>
if (Rm != 0xF) {<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
}<br>
<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
Inst.addOperand(MCOperand::CreateImm(0));<br>
<br>
if (Rm == 0xD)<br>
Inst.addOperand(MCOperand::CreateReg(0));<br>
else if (Rm != 0xF) {<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;<br>
}<br>
<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Rd = fieldFromInstruction32(Insn, 12, 4);<br>
Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;<br>
@@ -2147,30 +2149,30 @@<br>
}<br>
}<br>
<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder));<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder));<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder));<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) return MCDisassembler::Fail;<br>
if (Rm != 0xF) {<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
}<br>
<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
Inst.addOperand(MCOperand::CreateImm(align));<br>
<br>
if (Rm == 0xD)<br>
Inst.addOperand(MCOperand::CreateReg(0));<br>
else if (Rm != 0xF) {<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;<br>
}<br>
<br>
return S;<br>
}<br>
<br>
-static DecodeStatus<br>
+static MCDisassembler::DecodeStatus<br>
DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Rd = fieldFromInstruction32(Insn, 12, 4);<br>
Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;<br>
@@ -2182,9 +2184,9 @@<br>
unsigned Q = fieldFromInstruction32(Insn, 6, 1);<br>
<br>
if (Q) {<br>
- CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder));<br>
+ if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;<br>
} else {<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;<br>
}<br>
<br>
Inst.addOperand(MCOperand::CreateImm(imm));<br>
@@ -2194,13 +2196,13 @@<br>
case ARM::VORRiv2i32:<br>
case ARM::VBICiv4i16:<br>
case ARM::VBICiv2i32:<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;<br>
break;<br>
case ARM::VORRiv8i16:<br>
case ARM::VORRiv4i32:<br>
case ARM::VBICiv8i16:<br>
case ARM::VBICiv4i32:<br>
- CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder));<br>
+ if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;<br>
break;<br>
default:<br>
break;<br>
@@ -2209,9 +2211,9 @@<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Rd = fieldFromInstruction32(Insn, 12, 4);<br>
Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;<br>
@@ -2219,40 +2221,40 @@<br>
Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;<br>
unsigned size = fieldFromInstruction32(Insn, 18, 2);<br>
<br>
- CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder));<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder));<br>
+ if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;<br>
Inst.addOperand(MCOperand::CreateImm(8 << size));<br>
<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder) {<br>
Inst.addOperand(MCOperand::CreateImm(8 - Val));<br>
- return Success;<br>
+ return MCDisassembler::Success;<br>
}<br>
<br>
-static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder) {<br>
Inst.addOperand(MCOperand::CreateImm(16 - Val));<br>
- return Success;<br>
+ return MCDisassembler::Success;<br>
}<br>
<br>
-static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder) {<br>
Inst.addOperand(MCOperand::CreateImm(32 - Val));<br>
- return Success;<br>
+ return MCDisassembler::Success;<br>
}<br>
<br>
-static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder) {<br>
Inst.addOperand(MCOperand::CreateImm(64 - Val));<br>
- return Success;<br>
+ return MCDisassembler::Success;<br>
}<br>
<br>
-static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Rd = fieldFromInstruction32(Insn, 12, 4);<br>
Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;<br>
@@ -2263,21 +2265,21 @@<br>
unsigned op = fieldFromInstruction32(Insn, 6, 1);<br>
unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;<br>
<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;<br>
if (op) {<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); // Writeback<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; // Writeback<br>
}<br>
<br>
for (unsigned i = 0; i < length; ++i) {<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder));<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder))) return MCDisassembler::Fail;<br>
}<br>
<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder));<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;<br>
<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder) {<br>
// The immediate needs to be a fully instantiated float. However, the<br>
// auto-generated decoder is only able to fill in some of the bits<br>
@@ -2299,21 +2301,21 @@<br>
fp_conv.integer |= (~b & 0x1) << 30;<br>
<br>
Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp));<br>
- return Success;<br>
+ return MCDisassembler::Success;<br>
}<br>
<br>
-static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,<br>
+static MCDisassembler::DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned dst = fieldFromInstruction16(Insn, 8, 3);<br>
unsigned imm = fieldFromInstruction16(Insn, 0, 8);<br>
<br>
- CHECK(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder));<br>
+ if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) return MCDisassembler::Fail;<br>
<br>
switch(Inst.getOpcode()) {<br>
default:<br>
- return Fail;<br>
+ return MCDisassembler::Fail;<br>
case ARM::tADR:<br>
break; // tADR does not explicitly represent the PC as an operand.<br>
case ARM::tADDrSPi:<br>
@@ -2325,83 +2327,83 @@<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder) {<br>
Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));<br>
- return Success;<br>
+ return MCDisassembler::Success;<br>
}<br>
<br>
-static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder) {<br>
Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));<br>
- return Success;<br>
+ return MCDisassembler::Success;<br>
}<br>
<br>
-static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder) {<br>
Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));<br>
- return Success;<br>
+ return MCDisassembler::Success;<br>
}<br>
<br>
-static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Rn = fieldFromInstruction32(Val, 0, 3);<br>
unsigned Rm = fieldFromInstruction32(Val, 3, 3);<br>
<br>
- CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
- CHECK(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder));<br>
+ if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;<br>
<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Rn = fieldFromInstruction32(Val, 0, 3);<br>
unsigned imm = fieldFromInstruction32(Val, 3, 5);<br>
<br>
- CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
+ if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
Inst.addOperand(MCOperand::CreateImm(imm));<br>
<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder) {<br>
Inst.addOperand(MCOperand::CreateImm(Val << 2));<br>
<br>
- return Success;<br>
+ return MCDisassembler::Success;<br>
}<br>
<br>
-static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder) {<br>
Inst.addOperand(MCOperand::CreateReg(ARM::SP));<br>
Inst.addOperand(MCOperand::CreateImm(Val));<br>
<br>
- return Success;<br>
+ return MCDisassembler::Success;<br>
}<br>
<br>
-static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Rn = fieldFromInstruction32(Val, 6, 4);<br>
unsigned Rm = fieldFromInstruction32(Val, 2, 4);<br>
unsigned imm = fieldFromInstruction32(Val, 0, 2);<br>
<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
- CHECK(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;<br>
Inst.addOperand(MCOperand::CreateImm(imm));<br>
<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
switch (Inst.getOpcode()) {<br>
case ARM::t2PLDs:<br>
@@ -2410,7 +2412,7 @@<br>
break;<br>
default: {<br>
unsigned Rt = fieldFromInstruction32(Insn, 12, 4);<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail;<br>
}<br>
}<br>
<br>
@@ -2434,7 +2436,7 @@<br>
Inst.addOperand(MCOperand::CreateReg(ARM::PC));<br>
break;<br>
default:<br>
- return Fail;<br>
+ return MCDisassembler::Fail;<br>
}<br>
<br>
int imm = fieldFromInstruction32(Insn, 0, 12);<br>
@@ -2447,46 +2449,46 @@<br>
unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);<br>
addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;<br>
addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;<br>
- CHECK(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder));<br>
+ if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) return MCDisassembler::Fail;<br>
<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder) {<br>
int imm = Val & 0xFF;<br>
if (!(Val & 0x100)) imm *= -1;<br>
Inst.addOperand(MCOperand::CreateImm(imm << 2));<br>
<br>
- return Success;<br>
+ return MCDisassembler::Success;<br>
}<br>
<br>
-static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Rn = fieldFromInstruction32(Val, 9, 4);<br>
unsigned imm = fieldFromInstruction32(Val, 0, 9);<br>
<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
- CHECK(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) return MCDisassembler::Fail;<br>
<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder) {<br>
int imm = Val & 0xFF;<br>
if (!(Val & 0x100)) imm *= -1;<br>
Inst.addOperand(MCOperand::CreateImm(imm));<br>
<br>
- return Success;<br>
+ return MCDisassembler::Success;<br>
}<br>
<br>
<br>
-static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Rn = fieldFromInstruction32(Val, 9, 4);<br>
unsigned imm = fieldFromInstruction32(Val, 0, 9);<br>
@@ -2504,28 +2506,28 @@<br>
break;<br>
}<br>
<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
- CHECK(S, DecodeT2Imm8(Inst, imm, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) return MCDisassembler::Fail;<br>
<br>
return S;<br>
}<br>
<br>
<br>
-static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Rn = fieldFromInstruction32(Val, 13, 4);<br>
unsigned imm = fieldFromInstruction32(Val, 0, 12);<br>
<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
Inst.addOperand(MCOperand::CreateImm(imm));<br>
<br>
return S;<br>
}<br>
<br>
<br>
-static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,<br>
+static MCDisassembler::DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,<br>
uint64_t Address, const void *Decoder) {<br>
unsigned imm = fieldFromInstruction16(Insn, 0, 7);<br>
<br>
@@ -2533,32 +2535,32 @@<br>
Inst.addOperand(MCOperand::CreateReg(ARM::SP));<br>
Inst.addOperand(MCOperand::CreateImm(imm));<br>
<br>
- return Success;<br>
+ return MCDisassembler::Success;<br>
}<br>
<br>
-static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,<br>
+static MCDisassembler::DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
if (Inst.getOpcode() == ARM::tADDrSP) {<br>
unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);<br>
Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;<br>
<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder));<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) return MCDisassembler::Fail;<br>
Inst.addOperand(MCOperand::CreateReg(ARM::SP));<br>
} else if (Inst.getOpcode() == ARM::tADDspr) {<br>
unsigned Rm = fieldFromInstruction16(Insn, 3, 4);<br>
<br>
Inst.addOperand(MCOperand::CreateReg(ARM::SP));<br>
Inst.addOperand(MCOperand::CreateReg(ARM::SP));<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;<br>
}<br>
<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,<br>
+static MCDisassembler::DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,<br>
uint64_t Address, const void *Decoder) {<br>
unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;<br>
unsigned flags = fieldFromInstruction16(Insn, 0, 3);<br>
@@ -2566,47 +2568,47 @@<br>
Inst.addOperand(MCOperand::CreateImm(imod));<br>
Inst.addOperand(MCOperand::CreateImm(flags));<br>
<br>
- return Success;<br>
+ return MCDisassembler::Success;<br>
}<br>
<br>
-static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
unsigned Rm = fieldFromInstruction32(Insn, 0, 4);<br>
unsigned add = fieldFromInstruction32(Insn, 4, 1);<br>
<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) ;<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;<br>
Inst.addOperand(MCOperand::CreateImm(add));<br>
<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder) {<br>
Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));<br>
- return Success;<br>
+ return MCDisassembler::Success;<br>
}<br>
<br>
-static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder) {<br>
if (Val == 0xA || Val == 0xB)<br>
- return Fail;<br>
+ return MCDisassembler::Fail;<br>
<br>
Inst.addOperand(MCOperand::CreateImm(Val));<br>
- return Success;<br>
+ return MCDisassembler::Success;<br>
}<br>
<br>
-static DecodeStatus<br>
+static MCDisassembler::DecodeStatus<br>
DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned pred = fieldFromInstruction32(Insn, 22, 4);<br>
if (pred == 0xE || pred == 0xF) {<br>
unsigned opc = fieldFromInstruction32(Insn, 4, 28);<br>
switch (opc) {<br>
default:<br>
- return Fail;<br>
+ return MCDisassembler::Fail;<br>
case 0xf3bf8f4:<br>
Inst.setOpcode(ARM::t2DSB);<br>
break;<br>
@@ -2615,7 +2617,7 @@<br>
break;<br>
case 0xf3bf8f6:<br>
Inst.setOpcode(ARM::t2ISB);<br>
- return Success;<br>
+ return MCDisassembler::Success;<br>
}<br>
<br>
unsigned imm = fieldFromInstruction32(Insn, 0, 4);<br>
@@ -2628,8 +2630,8 @@<br>
brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;<br>
brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;<br>
<br>
- CHECK(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder));<br>
- CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));<br>
+ if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler::Fail;<br>
<br>
return S;<br>
}<br>
@@ -2637,7 +2639,7 @@<br>
// Decode a shifted immediate operand. These basically consist<br>
// of an 8-bit value, and a 4-bit directive that specifies either<br>
// a splat operation or a rotation.<br>
-static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder) {<br>
unsigned ctrl = fieldFromInstruction32(Val, 10, 2);<br>
if (ctrl == 0) {<br>
@@ -2665,27 +2667,27 @@<br>
Inst.addOperand(MCOperand::CreateImm(imm));<br>
}<br>
<br>
- return Success;<br>
+ return MCDisassembler::Success;<br>
}<br>
<br>
-static DecodeStatus<br>
+static MCDisassembler::DecodeStatus<br>
DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder){<br>
Inst.addOperand(MCOperand::CreateImm(Val << 1));<br>
- return Success;<br>
+ return MCDisassembler::Success;<br>
}<br>
<br>
-static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder){<br>
Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));<br>
- return Success;<br>
+ return MCDisassembler::Success;<br>
}<br>
<br>
-static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder) {<br>
switch (Val) {<br>
default:<br>
- return Fail;<br>
+ return MCDisassembler::Fail;<br>
case 0xF: // SY<br>
case 0xE: // ST<br>
case 0xB: // ISH<br>
@@ -2698,60 +2700,60 @@<br>
}<br>
<br>
Inst.addOperand(MCOperand::CreateImm(Val));<br>
- return Success;<br>
+ return MCDisassembler::Success;<br>
}<br>
<br>
-static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,<br>
+static MCDisassembler::DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder) {<br>
- if (!Val) return Fail;<br>
+ if (!Val) return MCDisassembler::Fail;<br>
Inst.addOperand(MCOperand::CreateImm(Val));<br>
- return Success;<br>
+ return MCDisassembler::Success;<br>
}<br>
<br>
-static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Rt = fieldFromInstruction32(Insn, 12, 4);<br>
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);<br>
unsigned pred = fieldFromInstruction32(Insn, 28, 4);<br>
<br>
- if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail;<br>
+ if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;<br>
<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder));<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
- CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler::Fail;<br>
<br>
return S;<br>
}<br>
<br>
<br>
-static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder){<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Rd = fieldFromInstruction32(Insn, 12, 4);<br>
unsigned Rt = fieldFromInstruction32(Insn, 0, 4);<br>
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);<br>
unsigned pred = fieldFromInstruction32(Insn, 28, 4);<br>
<br>
- CHECK(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder));<br>
+ if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;<br>
<br>
- if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail;<br>
- if (Rd == Rn || Rd == Rt || Rd == Rt+1) return Fail;<br>
+ if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;<br>
+ if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;<br>
<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder));<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
- CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler::Fail;<br>
<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);<br>
unsigned Rt = fieldFromInstruction32(Insn, 12, 4);<br>
@@ -2760,19 +2762,19 @@<br>
imm |= fieldFromInstruction32(Insn, 23, 1) << 12;<br>
unsigned pred = fieldFromInstruction32(Insn, 28, 4);<br>
<br>
- if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable);<br>
+ if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;<br>
<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
- CHECK(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder));<br>
- CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler::Fail;<br>
<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);<br>
unsigned Rt = fieldFromInstruction32(Insn, 12, 4);<br>
@@ -2782,21 +2784,21 @@<br>
unsigned pred = fieldFromInstruction32(Insn, 28, 4);<br>
unsigned Rm = fieldFromInstruction32(Insn, 0, 4);<br>
<br>
- if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable);<br>
- if (Rm == 0xF) CHECK(S, Unpredictable);<br>
+ if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;<br>
+ if (Rm == 0xF) S = MCDisassembler::SoftFail;<br>
<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
- CHECK(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder));<br>
- CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler::Fail;<br>
<br>
return S;<br>
}<br>
<br>
<br>
-static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);<br>
unsigned Rt = fieldFromInstruction32(Insn, 12, 4);<br>
@@ -2805,19 +2807,19 @@<br>
imm |= fieldFromInstruction32(Insn, 23, 1) << 12;<br>
unsigned pred = fieldFromInstruction32(Insn, 28, 4);<br>
<br>
- if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable);<br>
+ if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;<br>
<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));<br>
- CHECK(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder));<br>
- CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler::Fail;<br>
<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);<br>
unsigned Rt = fieldFromInstruction32(Insn, 12, 4);<br>
@@ -2826,19 +2828,19 @@<br>
imm |= fieldFromInstruction32(Insn, 23, 1) << 12;<br>
unsigned pred = fieldFromInstruction32(Insn, 28, 4);<br>
<br>
- if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable);<br>
+ if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;<br>
<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));<br>
- CHECK(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder));<br>
- CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler::Fail;<br>
<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);<br>
unsigned Rm = fieldFromInstruction32(Insn, 0, 4);<br>
@@ -2850,49 +2852,49 @@<br>
unsigned index = 0;<br>
switch (size) {<br>
default:<br>
- return Fail;<br>
+ return MCDisassembler::Fail;<br>
case 0:<br>
if (fieldFromInstruction32(Insn, 4, 1))<br>
- return Fail; // UNDEFINED<br>
+ return MCDisassembler::Fail; // UNDEFINED<br>
index = fieldFromInstruction32(Insn, 5, 3);<br>
break;<br>
case 1:<br>
if (fieldFromInstruction32(Insn, 5, 1))<br>
- return Fail; // UNDEFINED<br>
+ return MCDisassembler::Fail; // UNDEFINED<br>
index = fieldFromInstruction32(Insn, 6, 2);<br>
if (fieldFromInstruction32(Insn, 4, 1))<br>
align = 2;<br>
break;<br>
case 2:<br>
if (fieldFromInstruction32(Insn, 6, 1))<br>
- return Fail; // UNDEFINED<br>
+ return MCDisassembler::Fail; // UNDEFINED<br>
index = fieldFromInstruction32(Insn, 7, 1);<br>
if (fieldFromInstruction32(Insn, 4, 2) != 0)<br>
align = 4;<br>
}<br>
<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;<br>
if (Rm != 0xF) { // Writeback<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
}<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
Inst.addOperand(MCOperand::CreateImm(align));<br>
if (Rm != 0xF) {<br>
- if (Rm != 0xD)<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));<br>
- else<br>
+ if (Rm != 0xD) {<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;<br>
+ } else<br>
Inst.addOperand(MCOperand::CreateReg(0));<br>
}<br>
<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;<br>
Inst.addOperand(MCOperand::CreateImm(index));<br>
<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);<br>
unsigned Rm = fieldFromInstruction32(Insn, 0, 4);<br>
@@ -2904,49 +2906,49 @@<br>
unsigned index = 0;<br>
switch (size) {<br>
default:<br>
- return Fail;<br>
+ return MCDisassembler::Fail;<br>
case 0:<br>
if (fieldFromInstruction32(Insn, 4, 1))<br>
- return Fail; // UNDEFINED<br>
+ return MCDisassembler::Fail; // UNDEFINED<br>
index = fieldFromInstruction32(Insn, 5, 3);<br>
break;<br>
case 1:<br>
if (fieldFromInstruction32(Insn, 5, 1))<br>
- return Fail; // UNDEFINED<br>
+ return MCDisassembler::Fail; // UNDEFINED<br>
index = fieldFromInstruction32(Insn, 6, 2);<br>
if (fieldFromInstruction32(Insn, 4, 1))<br>
align = 2;<br>
break;<br>
case 2:<br>
if (fieldFromInstruction32(Insn, 6, 1))<br>
- return Fail; // UNDEFINED<br>
+ return MCDisassembler::Fail; // UNDEFINED<br>
index = fieldFromInstruction32(Insn, 7, 1);<br>
if (fieldFromInstruction32(Insn, 4, 2) != 0)<br>
align = 4;<br>
}<br>
<br>
if (Rm != 0xF) { // Writeback<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
}<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
Inst.addOperand(MCOperand::CreateImm(align));<br>
if (Rm != 0xF) {<br>
- if (Rm != 0xD)<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));<br>
- else<br>
+ if (Rm != 0xD) {<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;<br>
+ } else<br>
Inst.addOperand(MCOperand::CreateReg(0));<br>
}<br>
<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;<br>
Inst.addOperand(MCOperand::CreateImm(index));<br>
<br>
return S;<br>
}<br>
<br>
<br>
-static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);<br>
unsigned Rm = fieldFromInstruction32(Insn, 0, 4);<br>
@@ -2959,7 +2961,7 @@<br>
unsigned inc = 1;<br>
switch (size) {<br>
default:<br>
- return Fail;<br>
+ return MCDisassembler::Fail;<br>
case 0:<br>
index = fieldFromInstruction32(Insn, 5, 3);<br>
if (fieldFromInstruction32(Insn, 4, 1))<br>
@@ -2974,7 +2976,7 @@<br>
break;<br>
case 2:<br>
if (fieldFromInstruction32(Insn, 5, 1))<br>
- return Fail; // UNDEFINED<br>
+ return MCDisassembler::Fail; // UNDEFINED<br>
index = fieldFromInstruction32(Insn, 7, 1);<br>
if (fieldFromInstruction32(Insn, 4, 1) != 0)<br>
align = 8;<br>
@@ -2983,30 +2985,30 @@<br>
break;<br>
}<br>
<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) return MCDisassembler::Fail;<br>
if (Rm != 0xF) { // Writeback<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
}<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
Inst.addOperand(MCOperand::CreateImm(align));<br>
if (Rm != 0xF) {<br>
- if (Rm != 0xD)<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));<br>
- else<br>
+ if (Rm != 0xD) {<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;<br>
+ } else<br>
Inst.addOperand(MCOperand::CreateReg(0));<br>
}<br>
<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) return MCDisassembler::Fail;<br>
Inst.addOperand(MCOperand::CreateImm(index));<br>
<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);<br>
unsigned Rm = fieldFromInstruction32(Insn, 0, 4);<br>
@@ -3019,7 +3021,7 @@<br>
unsigned inc = 1;<br>
switch (size) {<br>
default:<br>
- return Fail;<br>
+ return MCDisassembler::Fail;<br>
case 0:<br>
index = fieldFromInstruction32(Insn, 5, 3);<br>
if (fieldFromInstruction32(Insn, 4, 1))<br>
@@ -3034,7 +3036,7 @@<br>
break;<br>
case 2:<br>
if (fieldFromInstruction32(Insn, 5, 1))<br>
- return Fail; // UNDEFINED<br>
+ return MCDisassembler::Fail; // UNDEFINED<br>
index = fieldFromInstruction32(Insn, 7, 1);<br>
if (fieldFromInstruction32(Insn, 4, 1) != 0)<br>
align = 8;<br>
@@ -3044,28 +3046,28 @@<br>
}<br>
<br>
if (Rm != 0xF) { // Writeback<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
}<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
Inst.addOperand(MCOperand::CreateImm(align));<br>
if (Rm != 0xF) {<br>
- if (Rm != 0xD)<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));<br>
- else<br>
+ if (Rm != 0xD) {<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;<br>
+ } else<br>
Inst.addOperand(MCOperand::CreateReg(0));<br>
}<br>
<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) return MCDisassembler::Fail;<br>
Inst.addOperand(MCOperand::CreateImm(index));<br>
<br>
return S;<br>
}<br>
<br>
<br>
-static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);<br>
unsigned Rm = fieldFromInstruction32(Insn, 0, 4);<br>
@@ -3078,55 +3080,55 @@<br>
unsigned inc = 1;<br>
switch (size) {<br>
default:<br>
- return Fail;<br>
+ return MCDisassembler::Fail;<br>
case 0:<br>
if (fieldFromInstruction32(Insn, 4, 1))<br>
- return Fail; // UNDEFINED<br>
+ return MCDisassembler::Fail; // UNDEFINED<br>
index = fieldFromInstruction32(Insn, 5, 3);<br>
break;<br>
case 1:<br>
if (fieldFromInstruction32(Insn, 4, 1))<br>
- return Fail; // UNDEFINED<br>
+ return MCDisassembler::Fail; // UNDEFINED<br>
index = fieldFromInstruction32(Insn, 6, 2);<br>
if (fieldFromInstruction32(Insn, 5, 1))<br>
inc = 2;<br>
break;<br>
case 2:<br>
if (fieldFromInstruction32(Insn, 4, 2))<br>
- return Fail; // UNDEFINED<br>
+ return MCDisassembler::Fail; // UNDEFINED<br>
index = fieldFromInstruction32(Insn, 7, 1);<br>
if (fieldFromInstruction32(Insn, 6, 1))<br>
inc = 2;<br>
break;<br>
}<br>
<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) return MCDisassembler::Fail;<br>
<br>
if (Rm != 0xF) { // Writeback<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
}<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
Inst.addOperand(MCOperand::CreateImm(align));<br>
if (Rm != 0xF) {<br>
- if (Rm != 0xD)<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));<br>
- else<br>
+ if (Rm != 0xD) {<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;<br>
+ } else<br>
Inst.addOperand(MCOperand::CreateReg(0));<br>
}<br>
<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) return MCDisassembler::Fail;<br>
Inst.addOperand(MCOperand::CreateImm(index));<br>
<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);<br>
unsigned Rm = fieldFromInstruction32(Insn, 0, 4);<br>
@@ -3139,22 +3141,22 @@<br>
unsigned inc = 1;<br>
switch (size) {<br>
default:<br>
- return Fail;<br>
+ return MCDisassembler::Fail;<br>
case 0:<br>
if (fieldFromInstruction32(Insn, 4, 1))<br>
- return Fail; // UNDEFINED<br>
+ return MCDisassembler::Fail; // UNDEFINED<br>
index = fieldFromInstruction32(Insn, 5, 3);<br>
break;<br>
case 1:<br>
if (fieldFromInstruction32(Insn, 4, 1))<br>
- return Fail; // UNDEFINED<br>
+ return MCDisassembler::Fail; // UNDEFINED<br>
index = fieldFromInstruction32(Insn, 6, 2);<br>
if (fieldFromInstruction32(Insn, 5, 1))<br>
inc = 2;<br>
break;<br>
case 2:<br>
if (fieldFromInstruction32(Insn, 4, 2))<br>
- return Fail; // UNDEFINED<br>
+ return MCDisassembler::Fail; // UNDEFINED<br>
index = fieldFromInstruction32(Insn, 7, 1);<br>
if (fieldFromInstruction32(Insn, 6, 1))<br>
inc = 2;<br>
@@ -3162,29 +3164,29 @@<br>
}<br>
<br>
if (Rm != 0xF) { // Writeback<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
}<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
Inst.addOperand(MCOperand::CreateImm(align));<br>
if (Rm != 0xF) {<br>
- if (Rm != 0xD)<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));<br>
- else<br>
+ if (Rm != 0xD) {<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;<br>
+ } else<br>
Inst.addOperand(MCOperand::CreateReg(0));<br>
}<br>
<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) return MCDisassembler::Fail;<br>
Inst.addOperand(MCOperand::CreateImm(index));<br>
<br>
return S;<br>
}<br>
<br>
<br>
-static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);<br>
unsigned Rm = fieldFromInstruction32(Insn, 0, 4);<br>
@@ -3197,7 +3199,7 @@<br>
unsigned inc = 1;<br>
switch (size) {<br>
default:<br>
- return Fail;<br>
+ return MCDisassembler::Fail;<br>
case 0:<br>
if (fieldFromInstruction32(Insn, 4, 1))<br>
align = 4;<br>
@@ -3219,35 +3221,35 @@<br>
break;<br>
}<br>
<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder));<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) return MCDisassembler::Fail;<br>
<br>
if (Rm != 0xF) { // Writeback<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
}<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
Inst.addOperand(MCOperand::CreateImm(align));<br>
if (Rm != 0xF) {<br>
- if (Rm != 0xD)<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));<br>
- else<br>
+ if (Rm != 0xD) {<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;<br>
+ } else<br>
Inst.addOperand(MCOperand::CreateReg(0));<br>
}<br>
<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder));<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) return MCDisassembler::Fail;<br>
Inst.addOperand(MCOperand::CreateImm(index));<br>
<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
<br>
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);<br>
unsigned Rm = fieldFromInstruction32(Insn, 0, 4);<br>
@@ -3260,7 +3262,7 @@<br>
unsigned inc = 1;<br>
switch (size) {<br>
default:<br>
- return Fail;<br>
+ return MCDisassembler::Fail;<br>
case 0:<br>
if (fieldFromInstruction32(Insn, 4, 1))<br>
align = 4;<br>
@@ -3283,29 +3285,29 @@<br>
}<br>
<br>
if (Rm != 0xF) { // Writeback<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
}<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;<br>
Inst.addOperand(MCOperand::CreateImm(align));<br>
if (Rm != 0xF) {<br>
- if (Rm != 0xD)<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));<br>
- else<br>
+ if (Rm != 0xD) {<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;<br>
+ } else<br>
Inst.addOperand(MCOperand::CreateReg(0));<br>
}<br>
<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));<br>
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder));<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) return MCDisassembler::Fail;<br>
Inst.addOperand(MCOperand::CreateImm(index));<br>
<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
unsigned Rt = fieldFromInstruction32(Insn, 12, 4);<br>
unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);<br>
unsigned Rm = fieldFromInstruction32(Insn, 0, 4);<br>
@@ -3313,20 +3315,20 @@<br>
Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;<br>
<br>
if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)<br>
- CHECK(S, Unpredictable);<br>
+ S = MCDisassembler::SoftFail;<br>
<br>
- CHECK(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder));<br>
- CHECK(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder));<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder));<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder));<br>
- CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));<br>
+ if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler::Fail;<br>
<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
unsigned Rt = fieldFromInstruction32(Insn, 12, 4);<br>
unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);<br>
unsigned Rm = fieldFromInstruction32(Insn, 0, 4);<br>
@@ -3334,20 +3336,20 @@<br>
Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;<br>
<br>
if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)<br>
- CHECK(S, Unpredictable);<br>
+ S = MCDisassembler::SoftFail;<br>
<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder));<br>
- CHECK(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder));<br>
- CHECK(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder));<br>
- CHECK(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder));<br>
- CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler::Fail;<br>
<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn,<br>
+static MCDisassembler::DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder) {<br>
- DecodeStatus S = Success;<br>
+ MCDisassembler::DecodeStatus S = MCDisassembler::Success;<br>
unsigned pred = fieldFromInstruction16(Insn, 4, 4);<br>
// The InstPrinter needs to have the low bit of the predicate in<br>
// the mask operand to be able to print it properly.<br>
@@ -3355,7 +3357,7 @@<br>
<br>
if (pred == 0xF) {<br>
pred = 0xE;<br>
- CHECK(S, Unpredictable);<br>
+ S = MCDisassembler::SoftFail;<br>
}<br>
<br>
if ((mask & 0xF) == 0) {<br>
@@ -3363,7 +3365,7 @@<br>
// the predicate.<br>
mask &= 0x10;<br>
mask |= 0x8;<br>
- CHECK(S, Unpredictable);<br>
+ S = MCDisassembler::SoftFail;<br>
}<br>
<br>
Inst.addOperand(MCOperand::CreateImm(pred));<br>
<br>
Modified: llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp?rev=138948&r1=138947&r2=138948&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp?rev=138948&r1=138947&r2=138948&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp (original)<br>
+++ llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp Thu Sep 1 13:02:14 2011<br>
@@ -132,9 +132,9 @@<br>
if (Target.getName() == "ARM" ||<br>
Target.getName() == "Thumb") {<br>
FixedLenDecoderEmitter(Records,<br>
- "CHECK(S, ", ");",<br>
- "S", "Fail",<br>
- "DecodeStatus S = Success;\n(void)S;").run(OS);<br>
+ "if (!Check(S, ", ")) return MCDisassembler::Fail;",<br>
+ "S", "MCDisassembler::Fail",<br>
+ "MCDisassembler::DecodeStatus S = MCDisassembler::Success;\n(void)S;").run(OS);<br>
return;<br>
}<br>
<br>
<br>
<br>
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</blockquote></div><br></div>