[llvm-commits] [llvm] r128746 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td test/MC/Disassembler/ARM/arm-tests.txt

[Johnny Chen]

Author: johnny
Date: Fri Apr  1 17:32:51 2011
New Revision: 128746

URL: http://llvm.org/viewvc/llvm-project?rev=128746&view=rev
Log:
Fix the instruction table entries for AI1_adde_sube_s_irs multiclass definition so that
all the instruction have:

    let Inst{31-27} = 0b1110; // non-predicated

Before, the ARM decoder was confusing:

> 0x40 0xf3 0xb8 0x80

as:

Opcode=16 Name=ADCSSrs Format=ARM_FORMAT_DPSOREGFRM(5)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------

	adcs	pc, r8, r0, asr #6

since the cond field for ADCSSrs is a wild card, and so is ADCrs, with the ADCSSrs having Inst{20} as '1'.

Now, the AR decoder behaves correctly:

> 0x40 0xf3 0xb8 0x80
> END
Executing command: /Volumes/data/lldb/llvm/Debug+Asserts/bin/llvm-mc -disassemble -triple=arm-apple-darwin -debug-only=arm-disassembler mc-input.txt

Opcode=19 Name=ADCrs Format=ARM_FORMAT_DPSOREGFRM(5)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------

	adcshi	pc, r8, r0, asr #6
> 

rdar://problem/9223094

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=128746&r1=128745&r2=128746&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Fri Apr  1 17:32:51 2011
@@ -939,6 +939,7 @@
     bits<4> Rd;
     bits<4> Rn;
     bits<12> imm;
+    let Inst{31-27} = 0b1110; // non-predicated
     let Inst{15-12} = Rd;
     let Inst{19-16} = Rn;
     let Inst{11-0} = imm;
@@ -952,6 +953,7 @@
     bits<4> Rd;
     bits<4> Rn;
     bits<4> Rm;
+    let Inst{31-27} = 0b1110; // non-predicated
     let Inst{11-4} = 0b00000000;
     let isCommutable = Commutable;
     let Inst{3-0} = Rm;
@@ -967,6 +969,7 @@
     bits<4> Rd;
     bits<4> Rn;
     bits<12> shift;
+    let Inst{31-27} = 0b1110; // non-predicated
     let Inst{11-0} = shift;
     let Inst{15-12} = Rd;
     let Inst{19-16} = Rn;

Modified: llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt?rev=128746&r1=128745&r2=128746&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt Fri Apr  1 17:32:51 2011
@@ -226,3 +226,10 @@
 
 # CHECK:	blx	#60
 0x0f 0x00 0x00 0xfa
+
+# CHECK-NOT:	adcs	r10, r8, r0, asr #6
+# CHECK:	adcshi	r10, r8, r0, asr #6
+0x40 0xa3 0xb8 0x80
+
+# CHECK:	adcshi	r10, r8, r0, asr r3
+0x50 0xa3 0xb8 0x80