[llvm-commits] [llvm] r119855 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

[Jim Grosbach]

Author: grosbach
Date: Fri Nov 19 16:22:37 2010
New Revision: 119855

URL: http://llvm.org/viewvc/llvm-project?rev=119855&view=rev
Log:
Fix encoding for ARM MLS instruction.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=119855&r1=119854&r2=119855&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Fri Nov 19 16:22:37 2010
@@ -2547,14 +2547,16 @@
   let Inst{15-12} = Ra;
 }
 
-def MLS  : AMul1I<0b0000011, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
-                   IIC_iMAC32, "mls", "\t$dst, $a, $b, $c",
-                   [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>,
+def MLS  : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
+                   IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
+                   [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
                    Requires<[IsARM, HasV6T2]> {
   bits<4> Rd;
   bits<4> Rm;
   bits<4> Rn;
+  bits<4> Ra;
   let Inst{19-16} = Rd;
+  let Inst{15-12} = Ra;
   let Inst{11-8}  = Rm;
   let Inst{3-0}   = Rn;
 }