[llvm-commits] [llvm] r116992 - in /llvm/trunk: lib/Target/ARM/ARMScheduleA8.td lib/Target/ARM/ARMScheduleA9.td lib/Target/ARM/ARMScheduleV6.td test/CodeGen/ARM/fmscs.ll test/CodeGen/ARM/reg_sequence.ll test/MC/ARM/simple-fp-encoding.ll
Evan Cheng
evan.cheng at apple.com
Thu Oct 21 12:55:12 PDT 2010
Thanks Andy!
Don't we have a better way to write encoding tests? Is this due to the lack of ARM assembly parser?
Evan
On Oct 20, 2010, at 8:40 PM, Andrew Trick wrote:
> Author: atrick
> Date: Wed Oct 20 22:40:16 2010
> New Revision: 116992
>
> URL: http://llvm.org/viewvc/llvm-project?rev=116992&view=rev
> Log:
> putback r116983 and fix simple-fp-encoding.ll tests
>
> Modified:
> llvm/trunk/lib/Target/ARM/ARMScheduleA8.td
> llvm/trunk/lib/Target/ARM/ARMScheduleA9.td
> llvm/trunk/lib/Target/ARM/ARMScheduleV6.td
> llvm/trunk/test/CodeGen/ARM/fmscs.ll
> llvm/trunk/test/CodeGen/ARM/reg_sequence.ll
> llvm/trunk/test/MC/ARM/simple-fp-encoding.ll
>
> Modified: llvm/trunk/lib/Target/ARM/ARMScheduleA8.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA8.td?rev=116992&r1=116991&r2=116992&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMScheduleA8.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMScheduleA8.td Wed Oct 20 22:40:16 2010
> @@ -331,6 +331,28 @@
> InstrItinData<IIC_fpSQRT64, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
> InstrStage<29, [A8_NPipe], 0>,
> InstrStage<29, [A8_NLSPipe]>], [29, 1]>,
> +
> + //
> + // Integer to Single-precision Move
> + InstrItinData<IIC_fpMOVIS, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
> + InstrStage<1, [A8_NPipe]>],
> + [2, 1]>,
> + //
> + // Integer to Double-precision Move
> + InstrItinData<IIC_fpMOVID, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
> + InstrStage<1, [A8_NPipe]>],
> + [2, 1, 1]>,
> + //
> + // Single-precision to Integer Move
> + InstrItinData<IIC_fpMOVSI, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
> + InstrStage<1, [A8_NPipe]>],
> + [20, 1]>,
> + //
> + // Double-precision to Integer Move
> + InstrItinData<IIC_fpMOVDI, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
> + InstrStage<1, [A8_NPipe]>],
> + [20, 20, 1]>,
> +
> //
> // Single-precision FP Load
> InstrItinData<IIC_fpLoad32, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
>
> Modified: llvm/trunk/lib/Target/ARM/ARMScheduleA9.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA9.td?rev=116992&r1=116991&r2=116992&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMScheduleA9.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMScheduleA9.td Wed Oct 20 22:40:16 2010
> @@ -641,7 +641,7 @@
> InstrStage<1, [A9_DRegsVFP], 0, Required>,
> InstrStage<2, [A9_DRegsN], 0, Reserved>,
> InstrStage<1, [A9_NPipe]>],
> - [1, 1]>,
> + [2, 1]>,
> //
> // Double-precision to Integer Move
> InstrItinData<IIC_fpMOVDI, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
> @@ -649,7 +649,7 @@
> InstrStage<1, [A9_DRegsVFP], 0, Required>,
> InstrStage<2, [A9_DRegsN], 0, Reserved>,
> InstrStage<1, [A9_NPipe]>],
> - [1, 1, 1]>,
> + [2, 1, 1]>,
> //
> // Single-precision FP Load
> InstrItinData<IIC_fpLoad32, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
> @@ -1430,7 +1430,7 @@
> InstrStage<1, [A9_DRegsN], 0, Required>,
> InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
> InstrStage<1, [A9_NPipe]>],
> - [2, 1]>,
> + [1, 1]>,
> //
> // Integer to Double-precision Move
> InstrItinData<IIC_VMOVID , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
> @@ -1438,7 +1438,7 @@
> InstrStage<1, [A9_DRegsN], 0, Required>,
> InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
> InstrStage<1, [A9_NPipe]>],
> - [2, 1, 1]>,
> + [1, 1, 1]>,
> //
> // Single-precision to Integer Move
> InstrItinData<IIC_VMOVSI , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
>
> Modified: llvm/trunk/lib/Target/ARM/ARMScheduleV6.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleV6.td?rev=116992&r1=116991&r2=116992&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMScheduleV6.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMScheduleV6.td Wed Oct 20 22:40:16 2010
> @@ -247,6 +247,18 @@
> // Double-precision FP SQRT
> InstrItinData<IIC_fpSQRT64 , [InstrStage<29, [V6_Pipe]>], [34, 2, 2]>,
> //
> + // Integer to Single-precision Move
> + InstrItinData<IIC_fpMOVIS, [InstrStage<1, [V6_Pipe]>], [10, 1]>,
> + //
> + // Integer to Double-precision Move
> + InstrItinData<IIC_fpMOVID, [InstrStage<1, [V6_Pipe]>], [10, 1, 1]>,
> + //
> + // Single-precision to Integer Move
> + InstrItinData<IIC_fpMOVSI, [InstrStage<1, [V6_Pipe]>], [10, 1]>,
> + //
> + // Double-precision to Integer Move
> + InstrItinData<IIC_fpMOVDI, [InstrStage<1, [V6_Pipe]>], [10, 10, 1]>,
> + //
> // Single-precision FP Load
> InstrItinData<IIC_fpLoad32 , [InstrStage<1, [V6_Pipe]>], [5, 2, 2]>,
> //
>
> Modified: llvm/trunk/test/CodeGen/ARM/fmscs.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fmscs.ll?rev=116992&r1=116991&r2=116992&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/fmscs.ll (original)
> +++ llvm/trunk/test/CodeGen/ARM/fmscs.ll Wed Oct 20 22:40:16 2010
> @@ -19,6 +19,6 @@
> ; NFP0: vnmls.f32 s2, s1, s0
>
> ; CORTEXA8: test:
> -; CORTEXA8: vnmls.f32 s2, s1, s0
> +; CORTEXA8: vnmls.f32 s1, s2, s0
> ; CORTEXA9: test:
> ; CORTEXA9: vnmls.f32 s0, s1, s2
>
> Modified: llvm/trunk/test/CodeGen/ARM/reg_sequence.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/reg_sequence.ll?rev=116992&r1=116991&r2=116992&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/reg_sequence.ll (original)
> +++ llvm/trunk/test/CodeGen/ARM/reg_sequence.ll Wed Oct 20 22:40:16 2010
> @@ -75,7 +75,8 @@
> ; CHECK: t3:
> ; CHECK: vld3.8
> ; CHECK: vmul.i8
> -; CHECK-NOT: vmov
> +; CHECK: vmov r
> +; CHECK-NOT: vmov d
> ; CHECK: vst3.8
> %tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2]
> %tmp2 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 0 ; <<8 x i8>> [#uses=1]
>
> Modified: llvm/trunk/test/MC/ARM/simple-fp-encoding.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/simple-fp-encoding.ll?rev=116992&r1=116991&r2=116992&view=diff
> ==============================================================================
> --- llvm/trunk/test/MC/ARM/simple-fp-encoding.ll (original)
> +++ llvm/trunk/test/MC/ARM/simple-fp-encoding.ll Wed Oct 20 22:40:16 2010
> @@ -269,7 +269,7 @@
> define float @f91(float %a, float %b, float %c) nounwind readnone {
> entry:
> ; CHECK: f91
> -; CHECK: vmla.f32 s2, s1, s0 @ encoding: [0x80,0x1a,0x00,0xee]
> +; CHECK: vmla.f32 s1, s2, s0 @ encoding: [0x00,0x0a,0x41,0xee]
> %mul = fmul float %a, %b
> %add = fadd float %mul, %c
> ret float %add
> @@ -287,7 +287,7 @@
> define float @f93(float %a, float %b, float %c) nounwind readnone {
> entry:
> ; CHECK: f93
> -; CHECK: vmls.f32 s2, s1, s0 @ encoding: [0xc0,0x1a,0x00,0xee]
> +; CHECK: vmls.f32 s1, s2, s0 @ encoding: [0x40,0x0a,0x41,0xee]
> %mul = fmul float %a, %b
> %sub = fsub float %c, %mul
> ret float %sub
> @@ -306,7 +306,7 @@
> define float @f95(float %a, float %b, float %c) nounwind readnone {
> entry:
> ; CHECK: f95
> -; CHECK: vnmla.f32 s2, s1, s0 @ encoding: [0xc0,0x1a,0x10,0xee]
> +; CHECK: vnmla.f32 s1, s2, s0 @ encoding: [0x40,0x0a,0x51,0xee]
> %mul = fmul float %a, %b
> %sub = fsub float -0.000000e+00, %mul
> %sub3 = fsub float %sub, %c
> @@ -325,7 +325,7 @@
> define float @f97(float %a, float %b, float %c) nounwind readnone {
> entry:
> ; CHECK: f97
> -; CHECK: vnmls.f32 s2, s1, s0 @ encoding: [0x80,0x1a,0x10,0xee]
> +; CHECK: vnmls.f32 s1, s2, s0 @ encoding: [0x00,0x0a,0x51,0xee]
> %mul = fmul float %a, %b
> %sub = fsub float %mul, %c
> ret float %sub
> @@ -404,10 +404,10 @@
> define void @f104(float %a, float %b, float %c, float %d, float %e, float %f) nounwind {
> entry:
> ; CHECK: f104
> -; CHECK: vmov s2, r0 @ encoding: [0x10,0x0a,0x01,0xee]
> -; CHECK: vmov s3, r1 @ encoding: [0x90,0x1a,0x01,0xee]
> -; CHECK: vmov s4, r2 @ encoding: [0x10,0x2a,0x02,0xee]
> -; CHECK: vmov s5, r3 @ encoding: [0x90,0x3a,0x02,0xee]
> +; CHECK: vmov s0, r0 @ encoding: [0x10,0x0a,0x00,0xee]
> +; CHECK: vmov s1, r1 @ encoding: [0x90,0x1a,0x00,0xee]
> +; CHECK: vmov s2, r2 @ encoding: [0x10,0x2a,0x01,0xee]
> +; CHECK: vmov s3, r3 @ encoding: [0x90,0x3a,0x01,0xee]
> %conv = fptosi float %a to i32
> %conv2 = fptosi float %b to i32
> %conv4 = fptosi float %c to i32
> @@ -415,10 +415,10 @@
> %conv8 = fptosi float %e to i32
> %conv10 = fptosi float %f to i32
> tail call void @g104(i32 %conv, i32 %conv2, i32 %conv4, i32 %conv6, i32 %conv8, i32 %conv10) nounwind
> -; CHECK: vmov r0, s2 @ encoding: [0x10,0x0a,0x11,0xee]
> -; CHECK: vmov r1, s3 @ encoding: [0x90,0x1a,0x11,0xee]
> -; CHECK: vmov r2, s4 @ encoding: [0x10,0x2a,0x12,0xee]
> -; CHECK: vmov r3, s5 @ encoding: [0x90,0x3a,0x12,0xee]
> +; CHECK: vmov r0, s0 @ encoding: [0x10,0x0a,0x10,0xee]
> +; CHECK: vmov r1, s1 @ encoding: [0x90,0x1a,0x10,0xee]
> +; CHECK: vmov r2, s2 @ encoding: [0x10,0x2a,0x11,0xee]
> +; CHECK: vmov r3, s3 @ encoding: [0x90,0x3a,0x11,0xee]
> ret void
> }
>
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20101021/31603e12/attachment.html>
More information about the llvm-commits
mailing list