<html><head></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; ">Thanks Andy!<div><br></div><div>Don't we have a better way to write encoding tests? Is this due to the lack of ARM assembly parser?</div><div><br></div><div>Evan</div><div><br><div><div>On Oct 20, 2010, at 8:40 PM, Andrew Trick wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div>Author: atrick<br>Date: Wed Oct 20 22:40:16 2010<br>New Revision: 116992<br><br>URL: <a href="http://llvm.org/viewvc/llvm-project?rev=116992&view=rev">http://llvm.org/viewvc/llvm-project?rev=116992&view=rev</a><br>Log:<br>putback r116983 and fix simple-fp-encoding.ll tests<br><br>Modified:<br> llvm/trunk/lib/Target/ARM/ARMScheduleA8.td<br> llvm/trunk/lib/Target/ARM/ARMScheduleA9.td<br> llvm/trunk/lib/Target/ARM/ARMScheduleV6.td<br> llvm/trunk/test/CodeGen/ARM/fmscs.ll<br> llvm/trunk/test/CodeGen/ARM/reg_sequence.ll<br> llvm/trunk/test/MC/ARM/simple-fp-encoding.ll<br><br>Modified: llvm/trunk/lib/Target/ARM/ARMScheduleA8.td<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA8.td?rev=116992&r1=116991&r2=116992&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA8.td?rev=116992&r1=116991&r2=116992&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/ARM/ARMScheduleA8.td (original)<br>+++ llvm/trunk/lib/Target/ARM/ARMScheduleA8.td Wed Oct 20 22:40:16 2010<br>@@ -331,6 +331,28 @@<br> InstrItinData<IIC_fpSQRT64, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,<br> InstrStage<29, [A8_NPipe], 0>,<br> InstrStage<29, [A8_NLSPipe]>], [29, 1]>,<br>+<br>+ //<br>+ // Integer to Single-precision Move<br>+ InstrItinData<IIC_fpMOVIS, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,<br>+ InstrStage<1, [A8_NPipe]>],<br>+ [2, 1]>,<br>+ //<br>+ // Integer to Double-precision Move<br>+ InstrItinData<IIC_fpMOVID, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,<br>+ InstrStage<1, [A8_NPipe]>],<br>+ [2, 1, 1]>,<br>+ //<br>+ // Single-precision to Integer Move<br>+ InstrItinData<IIC_fpMOVSI, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,<br>+ InstrStage<1, [A8_NPipe]>],<br>+ [20, 1]>,<br>+ //<br>+ // Double-precision to Integer Move<br>+ InstrItinData<IIC_fpMOVDI, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,<br>+ InstrStage<1, [A8_NPipe]>],<br>+ [20, 20, 1]>,<br>+<br> //<br> // Single-precision FP Load<br> InstrItinData<IIC_fpLoad32, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,<br><br>Modified: llvm/trunk/lib/Target/ARM/ARMScheduleA9.td<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA9.td?rev=116992&r1=116991&r2=116992&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA9.td?rev=116992&r1=116991&r2=116992&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/ARM/ARMScheduleA9.td (original)<br>+++ llvm/trunk/lib/Target/ARM/ARMScheduleA9.td Wed Oct 20 22:40:16 2010<br>@@ -641,7 +641,7 @@<br> InstrStage<1, [A9_DRegsVFP], 0, Required>,<br> InstrStage<2, [A9_DRegsN], 0, Reserved>,<br> InstrStage<1, [A9_NPipe]>],<br>- [1, 1]>,<br>+ [2, 1]>,<br> //<br> // Double-precision to Integer Move<br> InstrItinData<IIC_fpMOVDI, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,<br>@@ -649,7 +649,7 @@<br> InstrStage<1, [A9_DRegsVFP], 0, Required>,<br> InstrStage<2, [A9_DRegsN], 0, Reserved>,<br> InstrStage<1, [A9_NPipe]>],<br>- [1, 1, 1]>,<br>+ [2, 1, 1]>,<br> //<br> // Single-precision FP Load<br> InstrItinData<IIC_fpLoad32, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,<br>@@ -1430,7 +1430,7 @@<br> InstrStage<1, [A9_DRegsN], 0, Required>,<br> InstrStage<3, [A9_DRegsVFP], 0, Reserved>,<br> InstrStage<1, [A9_NPipe]>],<br>- [2, 1]>,<br>+ [1, 1]>,<br> //<br> // Integer to Double-precision Move<br> InstrItinData<IIC_VMOVID , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,<br>@@ -1438,7 +1438,7 @@<br> InstrStage<1, [A9_DRegsN], 0, Required>,<br> InstrStage<3, [A9_DRegsVFP], 0, Reserved>,<br> InstrStage<1, [A9_NPipe]>],<br>- [2, 1, 1]>,<br>+ [1, 1, 1]>,<br> //<br> // Single-precision to Integer Move<br> InstrItinData<IIC_VMOVSI , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,<br><br>Modified: llvm/trunk/lib/Target/ARM/ARMScheduleV6.td<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleV6.td?rev=116992&r1=116991&r2=116992&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleV6.td?rev=116992&r1=116991&r2=116992&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/ARM/ARMScheduleV6.td (original)<br>+++ llvm/trunk/lib/Target/ARM/ARMScheduleV6.td Wed Oct 20 22:40:16 2010<br>@@ -247,6 +247,18 @@<br> // Double-precision FP SQRT<br> InstrItinData<IIC_fpSQRT64 , [InstrStage<29, [V6_Pipe]>], [34, 2, 2]>,<br> //<br>+ // Integer to Single-precision Move<br>+ InstrItinData<IIC_fpMOVIS, [InstrStage<1, [V6_Pipe]>], [10, 1]>,<br>+ //<br>+ // Integer to Double-precision Move<br>+ InstrItinData<IIC_fpMOVID, [InstrStage<1, [V6_Pipe]>], [10, 1, 1]>,<br>+ //<br>+ // Single-precision to Integer Move<br>+ InstrItinData<IIC_fpMOVSI, [InstrStage<1, [V6_Pipe]>], [10, 1]>,<br>+ //<br>+ // Double-precision to Integer Move<br>+ InstrItinData<IIC_fpMOVDI, [InstrStage<1, [V6_Pipe]>], [10, 10, 1]>,<br>+ //<br> // Single-precision FP Load<br> InstrItinData<IIC_fpLoad32 , [InstrStage<1, [V6_Pipe]>], [5, 2, 2]>,<br> //<br><br>Modified: llvm/trunk/test/CodeGen/ARM/fmscs.ll<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fmscs.ll?rev=116992&r1=116991&r2=116992&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fmscs.ll?rev=116992&r1=116991&r2=116992&view=diff</a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/ARM/fmscs.ll (original)<br>+++ llvm/trunk/test/CodeGen/ARM/fmscs.ll Wed Oct 20 22:40:16 2010<br>@@ -19,6 +19,6 @@<br> ; NFP0: <span class="Apple-tab-span" style="white-space:pre"> </span>vnmls.f32<span class="Apple-tab-span" style="white-space:pre"> </span>s2, s1, s0<br><br> ; CORTEXA8: test:<br>-; CORTEXA8: <span class="Apple-tab-span" style="white-space:pre"> </span>vnmls.f32<span class="Apple-tab-span" style="white-space:pre"> </span>s2, s1, s0<br>+; CORTEXA8: <span class="Apple-tab-span" style="white-space:pre"> </span>vnmls.f32<span class="Apple-tab-span" style="white-space:pre"> </span>s1, s2, s0<br> ; CORTEXA9: test:<br> ; CORTEXA9: <span class="Apple-tab-span" style="white-space:pre"> </span>vnmls.f32<span class="Apple-tab-span" style="white-space:pre"> </span>s0, s1, s2<br><br>Modified: llvm/trunk/test/CodeGen/ARM/reg_sequence.ll<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/reg_sequence.ll?rev=116992&r1=116991&r2=116992&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/reg_sequence.ll?rev=116992&r1=116991&r2=116992&view=diff</a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/ARM/reg_sequence.ll (original)<br>+++ llvm/trunk/test/CodeGen/ARM/reg_sequence.ll Wed Oct 20 22:40:16 2010<br>@@ -75,7 +75,8 @@<br> ; CHECK: t3:<br> ; CHECK: vld3.8<br> ; CHECK: vmul.i8<br>-; CHECK-NOT: vmov<br>+; CHECK: vmov r<br>+; CHECK-NOT: vmov d<br> ; CHECK: vst3.8<br> %tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2]<br> %tmp2 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 0 ; <<8 x i8>> [#uses=1]<br><br>Modified: llvm/trunk/test/MC/ARM/simple-fp-encoding.ll<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/simple-fp-encoding.ll?rev=116992&r1=116991&r2=116992&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/simple-fp-encoding.ll?rev=116992&r1=116991&r2=116992&view=diff</a><br>==============================================================================<br>--- llvm/trunk/test/MC/ARM/simple-fp-encoding.ll (original)<br>+++ llvm/trunk/test/MC/ARM/simple-fp-encoding.ll Wed Oct 20 22:40:16 2010<br>@@ -269,7 +269,7 @@<br> define float @f91(float %a, float %b, float %c) nounwind readnone {<br> entry:<br> ; CHECK: f91<br>-; CHECK: vmla.f32 s2, s1, s0 @ encoding: [0x80,0x1a,0x00,0xee]<br>+; CHECK: vmla.f32 s1, s2, s0 @ encoding: [0x00,0x0a,0x41,0xee]<br> %mul = fmul float %a, %b<br> %add = fadd float %mul, %c<br> ret float %add<br>@@ -287,7 +287,7 @@<br> define float @f93(float %a, float %b, float %c) nounwind readnone {<br> entry:<br> ; CHECK: f93<br>-; CHECK: vmls.f32 s2, s1, s0 @ encoding: [0xc0,0x1a,0x00,0xee]<br>+; CHECK: vmls.f32 s1, s2, s0 @ encoding: [0x40,0x0a,0x41,0xee]<br> %mul = fmul float %a, %b<br> %sub = fsub float %c, %mul<br> ret float %sub<br>@@ -306,7 +306,7 @@<br> define float @f95(float %a, float %b, float %c) nounwind readnone {<br> entry:<br> ; CHECK: f95<br>-; CHECK: vnmla.f32 s2, s1, s0 @ encoding: [0xc0,0x1a,0x10,0xee]<br>+; CHECK: vnmla.f32 s1, s2, s0 @ encoding: [0x40,0x0a,0x51,0xee]<br> %mul = fmul float %a, %b<br> %sub = fsub float -0.000000e+00, %mul<br> %sub3 = fsub float %sub, %c<br>@@ -325,7 +325,7 @@<br> define float @f97(float %a, float %b, float %c) nounwind readnone {<br> entry:<br> ; CHECK: f97<br>-; CHECK: vnmls.f32 s2, s1, s0 @ encoding: [0x80,0x1a,0x10,0xee]<br>+; CHECK: vnmls.f32 s1, s2, s0 @ encoding: [0x00,0x0a,0x51,0xee]<br> %mul = fmul float %a, %b<br> %sub = fsub float %mul, %c<br> ret float %sub<br>@@ -404,10 +404,10 @@<br> define void @f104(float %a, float %b, float %c, float %d, float %e, float %f) nounwind {<br> entry:<br> ; CHECK: f104<br>-; CHECK: vmov s2, r0 @ encoding: [0x10,0x0a,0x01,0xee]<br>-; CHECK: vmov s3, r1 @ encoding: [0x90,0x1a,0x01,0xee]<br>-; CHECK: vmov s4, r2 @ encoding: [0x10,0x2a,0x02,0xee]<br>-; CHECK: vmov s5, r3 @ encoding: [0x90,0x3a,0x02,0xee]<br>+; CHECK: vmov<span class="Apple-tab-span" style="white-space:pre"> </span>s0, r0 @ encoding: [0x10,0x0a,0x00,0xee]<br>+; CHECK: vmov<span class="Apple-tab-span" style="white-space:pre"> </span>s1, r1 @ encoding: [0x90,0x1a,0x00,0xee]<br>+; CHECK: vmov<span class="Apple-tab-span" style="white-space:pre"> </span>s2, r2 @ encoding: [0x10,0x2a,0x01,0xee]<br>+; CHECK: vmov<span class="Apple-tab-span" style="white-space:pre"> </span>s3, r3 @ encoding: [0x90,0x3a,0x01,0xee]<br> %conv = fptosi float %a to i32<br> %conv2 = fptosi float %b to i32<br> %conv4 = fptosi float %c to i32<br>@@ -415,10 +415,10 @@<br> %conv8 = fptosi float %e to i32<br> %conv10 = fptosi float %f to i32<br> tail call void @g104(i32 %conv, i32 %conv2, i32 %conv4, i32 %conv6, i32 %conv8, i32 %conv10) nounwind<br>-; CHECK: vmov r0, s2 @ encoding: [0x10,0x0a,0x11,0xee]<br>-; CHECK: vmov r1, s3 @ encoding: [0x90,0x1a,0x11,0xee]<br>-; CHECK: vmov r2, s4 @ encoding: [0x10,0x2a,0x12,0xee]<br>-; CHECK: vmov r3, s5 @ encoding: [0x90,0x3a,0x12,0xee]<br>+; CHECK: vmov<span class="Apple-tab-span" style="white-space:pre"> </span>r0, s0<span class="Apple-tab-span" style="white-space:pre"> </span><span class="Apple-tab-span" style="white-space:pre"> </span><span class="Apple-tab-span" style="white-space:pre"> </span>@ encoding: [0x10,0x0a,0x10,0xee]<br>+; CHECK: vmov<span class="Apple-tab-span" style="white-space:pre"> </span>r1, s1<span class="Apple-tab-span" style="white-space:pre"> </span><span class="Apple-tab-span" style="white-space:pre"> </span><span class="Apple-tab-span" style="white-space:pre"> </span>@ encoding: [0x90,0x1a,0x10,0xee]<br>+; CHECK: vmov<span class="Apple-tab-span" style="white-space:pre"> </span>r2, s2<span class="Apple-tab-span" style="white-space:pre"> </span><span class="Apple-tab-span" style="white-space:pre"> </span><span class="Apple-tab-span" style="white-space:pre"> </span>@ encoding: [0x10,0x2a,0x11,0xee]<br>+; CHECK: vmov<span class="Apple-tab-span" style="white-space:pre"> </span>r3, s3 @ encoding: [0x90,0x3a,0x11,0xee]<br> ret void<br> }<br><br><br><br>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits<br></div></blockquote></div><br></div></body></html>