[llvm-commits] [llvm] r108735 - in /llvm/trunk: include/llvm/Target/TargetLowering.h lib/CodeGen/SelectionDAG/TargetLowering.cpp

[Evan Cheng]

On Jul 19, 2010, at 3:22 PM, Jakob Stoklund Olesen wrote:

> 
> On Jul 19, 2010, at 3:09 PM, Evan Cheng wrote:
> 
>> 
>> On Jul 19, 2010, at 1:22 PM, Jakob Stoklund Olesen wrote:
>>> 
>>> Can you use some kind of scaling so a DPR counts as 0.5 QPR?
>>> 
>> 
>> No, I don't like that. I was hoping to avoid having targets provide findRepresentativeClass(). But I think it cannot be avoided.
> 
> I don't think overriding findRepresentativeClass() solves the problem. There is no 'correct' representative register class.
> 
> Whenever you allocate a QPR, you block two DPRs.
> Whenever you allocate a DPR, you block one (half) QPR.
> 
> I think you need to model that asymmetry somehow.
> 

We'll see. Register pressure is "estimated" during instruction scheduling. I think we'll get away with the current scheme because it's relatively rare for vector and non-vector to mix in a way for this to be an issue. I want to keep it simple for now.

Evan