[llvm-commits] [llvm] r108735 - in /llvm/trunk: include/llvm/Target/TargetLowering.h lib/CodeGen/SelectionDAG/TargetLowering.cpp

[Eric Christopher]

On Jul 19, 2010, at 3:52 PM, Jakob Stoklund Olesen wrote:

> 
> On Jul 19, 2010, at 3:41 PM, Eric Christopher wrote:
> 
>> 
>> On Jul 19, 2010, at 3:38 PM, Jakob Stoklund Olesen wrote:
>> 
>>> QPR has 16 registers, DPR has 32.
>>> 
>>> If each DPR counts as a QPR, the scheduler is going to behave as if there were only 16 DPR registers available. That is almost as bad as scheduling purely for register pressure.
>>> 
>> 
>> True, but you could maybe count each QPR as two dprs and if you run into an occasion where that matters it'd suck, but I bet it'd be infrequent.
> 
> Right. That's what I meant by scaling. I think it is necessary.
> 

Ah.  Yes.

> Evan is probably right that QPRs and DPRs won't be live at the same time.
> 
> But we should at least get the number of registers right.
> 
> Overriding findRepresentativeClass for ARM does get the register counts right, though.

Right.  Violent agreement. :)

-eric