[llvm-commits] [llvm] r85355 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

[Evan Cheng]

On Oct 27, 2009, at 7:19 PM, Bob Wilson wrote:

> OK.  I didn't know about all of those.  I also need to add a Thumb  
> version, I think.

Right.

Evan

>
> On Oct 27, 2009, at 6:22 PM, Evan Cheng wrote:
>
>> Nice. Don't forget to update ARMInstrInfo. e.g.  
>> ARMInstrInfo::BlockHasNoFallThrough,  
>> ARMBaseInstrInfo::AnalyzeBranch, etc.
>>
>> Evan
>>
>> On Oct 27, 2009, at 5:37 PM, Bob Wilson wrote:
>>
>>> Author: bwilson
>>> Date: Tue Oct 27 19:37:03 2009
>>> New Revision: 85355
>>>
>>> URL: http://llvm.org/viewvc/llvm-project?rev=85355&view=rev
>>> Log:
>>> Add an indirect branch pattern for ARM.  Testcase will be coming  
>>> soon.
>>>
>>> Modified:
>>>  llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
>>>
>>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=85355&r1=85354&r2=85355&view=diff
>>>
>>> = 
>>> = 
>>> = 
>>> = 
>>> = 
>>> = 
>>> = 
>>> = 
>>> = 
>>> = 
>>> ====================================================================
>>> --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
>>> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Oct 27 19:37:03  
>>> 2009
>>> @@ -657,6 +657,16 @@
>>> let Inst{27-20} = 0b00010010;
>>> }
>>>
>>> +// Indirect branches
>>> +let isBranch = 1, isTerminator = 1, isBarrier = 1,  
>>> isIndirectBranch = 1 in {
>>> +  def BRIND : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx  
>>> $dst",
>>> +                  [(brind GPR:$dst)]> {
>>> +    let Inst{7-4}   = 0b0001;
>>> +    let Inst{19-8}  = 0b111111111111;
>>> +    let Inst{27-20} = 0b00010010;
>>> +  }
>>> +}
>>> +
>>> // FIXME: remove when we have a way to marking a MI with these  
>>> properties.
>>> // FIXME: Should pc be an implicit operand like PICADD, etc?
>>> let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
>>>
>>>
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>>
>