[llvm-commits] [llvm] r85357 - in /llvm/trunk/lib/Target/SystemZ: SystemZISelLowering.cpp SystemZInstrFP.td SystemZInstrInfo.td
Dan Gohman
gohman at apple.com
Tue Oct 27 17:55:58 PDT 2009
Author: djg
Date: Tue Oct 27 19:55:57 2009
New Revision: 85357
URL: http://llvm.org/viewvc/llvm-project?rev=85357&view=rev
Log:
Update SystemZ to use PSW following the way x86 uses EFLAGS. Besides
eliminating a use of MVT::Flag, this is needed for an upcoming CodeGen
change.
This unfortunately requires SystemZ to switch to the list-burr
scheduler, in order to handle the physreg defs properly, however
that's what LLVM has available at this time.
Modified:
llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
llvm/trunk/lib/Target/SystemZ/SystemZInstrFP.td
llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp?rev=85357&r1=85356&r2=85357&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp Tue Oct 27 19:55:57 2009
@@ -75,7 +75,13 @@
setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
setStackPointerRegisterToSaveRestore(SystemZ::R15D);
- setSchedulingPreference(SchedulingForLatency);
+
+ // TODO: It may be better to default to latency-oriented scheduling, however
+ // LLVM's current latency-oriented scheduler can't handle physreg definitions
+ // such as SystemZ has with PSW, so set this to the register-pressure
+ // scheduler, because it can.
+ setSchedulingPreference(SchedulingForRegPressure);
+
setBooleanContents(ZeroOrOneBooleanContent);
setOperationAction(ISD::BR_JT, MVT::Other, Expand);
@@ -663,7 +669,7 @@
DebugLoc dl = LHS.getDebugLoc();
return DAG.getNode((isUnsigned ? SystemZISD::UCMP : SystemZISD::CMP),
- dl, MVT::Flag, LHS, RHS);
+ dl, MVT::i64, LHS, RHS);
}
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrFP.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrFP.td?rev=85357&r1=85356&r2=85357&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrFP.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrFP.td Tue Oct 27 19:55:57 2009
@@ -25,15 +25,15 @@
return N->isExactlyValue(-0.0);
}]>;
-let usesCustomDAGSchedInserter = 1 in {
+let Uses = [PSW], usesCustomDAGSchedInserter = 1 in {
def SelectF32 : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, i8imm:$cc),
"# SelectF32 PSEUDO",
[(set FP32:$dst,
- (SystemZselect FP32:$src1, FP32:$src2, imm:$cc))]>;
+ (SystemZselect FP32:$src1, FP32:$src2, imm:$cc, PSW))]>;
def SelectF64 : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2, i8imm:$cc),
"# SelectF64 PSEUDO",
[(set FP64:$dst,
- (SystemZselect FP64:$src1, FP64:$src2, imm:$cc))]>;
+ (SystemZselect FP64:$src1, FP64:$src2, imm:$cc, PSW))]>;
}
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td?rev=85357&r1=85356&r2=85357&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td Tue Oct 27 19:55:57 2009
@@ -32,12 +32,12 @@
def SDT_SystemZCallSeqStart : SDCallSeqStart<[SDTCisI64<0>]>;
def SDT_SystemZCallSeqEnd : SDCallSeqEnd<[SDTCisI64<0>, SDTCisI64<1>]>;
def SDT_CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
-def SDT_BrCond : SDTypeProfile<0, 2,
+def SDT_BrCond : SDTypeProfile<0, 3,
[SDTCisVT<0, OtherVT>,
- SDTCisI8<1>]>;
-def SDT_SelectCC : SDTypeProfile<1, 3,
+ SDTCisI8<1>, SDTCisVT<2, i64>]>;
+def SDT_SelectCC : SDTypeProfile<1, 4,
[SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
- SDTCisI8<3>]>;
+ SDTCisI8<3>, SDTCisVT<4, i64>]>;
def SDT_Address : SDTypeProfile<1, 1,
[SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
@@ -54,11 +54,11 @@
def SystemZcallseq_end :
SDNode<"ISD::CALLSEQ_END", SDT_SystemZCallSeqEnd,
[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
-def SystemZcmp : SDNode<"SystemZISD::CMP", SDT_CmpTest, [SDNPOutFlag]>;
-def SystemZucmp : SDNode<"SystemZISD::UCMP", SDT_CmpTest, [SDNPOutFlag]>;
+def SystemZcmp : SDNode<"SystemZISD::CMP", SDT_CmpTest>;
+def SystemZucmp : SDNode<"SystemZISD::UCMP", SDT_CmpTest>;
def SystemZbrcond : SDNode<"SystemZISD::BRCOND", SDT_BrCond,
- [SDNPHasChain, SDNPInFlag]>;
-def SystemZselect : SDNode<"SystemZISD::SELECT", SDT_SelectCC, [SDNPInFlag]>;
+ [SDNPHasChain]>;
+def SystemZselect : SDNode<"SystemZISD::SELECT", SDT_SelectCC>;
def SystemZpcrelwrapper : SDNode<"SystemZISD::PCRelativeWrapper", SDT_Address, []>;
@@ -74,15 +74,15 @@
"#ADJCALLSTACKUP",
[(SystemZcallseq_end timm:$amt1, timm:$amt2)]>;
-let usesCustomDAGSchedInserter = 1 in {
+let Uses = [PSW], usesCustomDAGSchedInserter = 1 in {
def Select32 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cc),
"# Select32 PSEUDO",
[(set GR32:$dst,
- (SystemZselect GR32:$src1, GR32:$src2, imm:$cc))]>;
+ (SystemZselect GR32:$src1, GR32:$src2, imm:$cc, PSW))]>;
def Select64 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$cc),
"# Select64 PSEUDO",
[(set GR64:$dst,
- (SystemZselect GR64:$src1, GR64:$src2, imm:$cc))]>;
+ (SystemZselect GR64:$src1, GR64:$src2, imm:$cc, PSW))]>;
}
@@ -106,46 +106,46 @@
let Uses = [PSW] in {
def JO : Pseudo<(outs), (ins brtarget:$dst),
"jo\t$dst",
- [(SystemZbrcond bb:$dst, SYSTEMZ_COND_O)]>;
+ [(SystemZbrcond bb:$dst, SYSTEMZ_COND_O, PSW)]>;
def JH : Pseudo<(outs), (ins brtarget:$dst),
"jh\t$dst",
- [(SystemZbrcond bb:$dst, SYSTEMZ_COND_H)]>;
+ [(SystemZbrcond bb:$dst, SYSTEMZ_COND_H, PSW)]>;
def JNLE: Pseudo<(outs), (ins brtarget:$dst),
"jnle\t$dst",
- [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NLE)]>;
+ [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NLE, PSW)]>;
def JL : Pseudo<(outs), (ins brtarget:$dst),
"jl\t$dst",
- [(SystemZbrcond bb:$dst, SYSTEMZ_COND_L)]>;
+ [(SystemZbrcond bb:$dst, SYSTEMZ_COND_L, PSW)]>;
def JNHE: Pseudo<(outs), (ins brtarget:$dst),
"jnhe\t$dst",
- [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NHE)]>;
+ [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NHE, PSW)]>;
def JLH : Pseudo<(outs), (ins brtarget:$dst),
"jlh\t$dst",
- [(SystemZbrcond bb:$dst, SYSTEMZ_COND_LH)]>;
+ [(SystemZbrcond bb:$dst, SYSTEMZ_COND_LH, PSW)]>;
def JNE : Pseudo<(outs), (ins brtarget:$dst),
"jne\t$dst",
- [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NE)]>;
+ [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NE, PSW)]>;
def JE : Pseudo<(outs), (ins brtarget:$dst),
"je\t$dst",
- [(SystemZbrcond bb:$dst, SYSTEMZ_COND_E)]>;
+ [(SystemZbrcond bb:$dst, SYSTEMZ_COND_E, PSW)]>;
def JNLH: Pseudo<(outs), (ins brtarget:$dst),
"jnlh\t$dst",
- [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NLH)]>;
+ [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NLH, PSW)]>;
def JHE : Pseudo<(outs), (ins brtarget:$dst),
"jhe\t$dst",
- [(SystemZbrcond bb:$dst, SYSTEMZ_COND_HE)]>;
+ [(SystemZbrcond bb:$dst, SYSTEMZ_COND_HE, PSW)]>;
def JNL : Pseudo<(outs), (ins brtarget:$dst),
"jnl\t$dst",
- [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NL)]>;
+ [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NL, PSW)]>;
def JLE : Pseudo<(outs), (ins brtarget:$dst),
"jle\t$dst",
- [(SystemZbrcond bb:$dst, SYSTEMZ_COND_LE)]>;
+ [(SystemZbrcond bb:$dst, SYSTEMZ_COND_LE, PSW)]>;
def JNH : Pseudo<(outs), (ins brtarget:$dst),
"jnh\t$dst",
- [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NH)]>;
+ [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NH, PSW)]>;
def JNO : Pseudo<(outs), (ins brtarget:$dst),
"jno\t$dst",
- [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NO)]>;
+ [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NO, PSW)]>;
} // Uses = [PSW]
} // isBranch = 1
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