[llvm-commits] [llvm] r79676 - in /llvm/trunk/lib/Target/ARM: ARMInstrInfo.td ARMInstrNEON.td ARMInstrThumb.td ARMInstrThumb2.td AsmPrinter/ARMAsmPrinter.cpp
Bob Wilson
bob.wilson at apple.com
Fri Aug 21 15:01:57 PDT 2009
Author: bwilson
Date: Fri Aug 21 16:58:55 2009
New Revision: 79676
URL: http://llvm.org/viewvc/llvm-project?rev=79676&view=rev
Log:
Rename ARM "lane_cst" operands to "nohash_imm" since they are used for
several things other than Neon vector lane numbers. For inline assembly
operands with a "c" print code, check that they really are immediates.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=79676&r1=79675&r2=79676&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Fri Aug 21 16:58:55 2009
@@ -327,8 +327,8 @@
let MIOperandInfo = (ops GPR, i32imm);
}
-def lane_cst : Operand<i32> {
- let PrintMethod = "printLaneOperand";
+def nohash_imm : Operand<i32> {
+ let PrintMethod = "printNoHashImmediate";
}
//===----------------------------------------------------------------------===//
@@ -581,7 +581,7 @@
[]>;
def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
- (ins i32imm:$label, lane_cst:$id, pred:$p),
+ (ins i32imm:$label, nohash_imm:$id, pred:$p),
Pseudo, IIC_iALUi,
!strconcat(!strconcat(".set ${:private}PCRELV${:uid}, "
"(${label}_${id}-(",
Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=79676&r1=79675&r2=79676&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Fri Aug 21 16:58:55 2009
@@ -1658,27 +1658,27 @@
// VMOV : Vector Get Lane (move scalar to ARM core register)
def VGETLNs8 : NVGetLane<0b11100101, 0b1011, 0b00,
- (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
+ (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
NoItinerary, "vmov", ".s8\t$dst, $src[$lane]",
[(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
imm:$lane))]>;
def VGETLNs16 : NVGetLane<0b11100001, 0b1011, 0b01,
- (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
+ (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
NoItinerary, "vmov", ".s16\t$dst, $src[$lane]",
[(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
imm:$lane))]>;
def VGETLNu8 : NVGetLane<0b11101101, 0b1011, 0b00,
- (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
+ (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
NoItinerary, "vmov", ".u8\t$dst, $src[$lane]",
[(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
imm:$lane))]>;
def VGETLNu16 : NVGetLane<0b11101001, 0b1011, 0b01,
- (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
+ (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
NoItinerary, "vmov", ".u16\t$dst, $src[$lane]",
[(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
imm:$lane))]>;
def VGETLNi32 : NVGetLane<0b11100001, 0b1011, 0b00,
- (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
+ (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
NoItinerary, "vmov", ".32\t$dst, $src[$lane]",
[(set GPR:$dst, (extractelt (v2i32 DPR:$src),
imm:$lane))]>;
@@ -1715,17 +1715,17 @@
let Constraints = "$src1 = $dst" in {
def VSETLNi8 : NVSetLane<0b11100100, 0b1011, 0b00, (outs DPR:$dst),
- (ins DPR:$src1, GPR:$src2, lane_cst:$lane),
+ (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
NoItinerary, "vmov", ".8\t$dst[$lane], $src2",
[(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
GPR:$src2, imm:$lane))]>;
def VSETLNi16 : NVSetLane<0b11100000, 0b1011, 0b01, (outs DPR:$dst),
- (ins DPR:$src1, GPR:$src2, lane_cst:$lane),
+ (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
NoItinerary, "vmov", ".16\t$dst[$lane], $src2",
[(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
GPR:$src2, imm:$lane))]>;
def VSETLNi32 : NVSetLane<0b11100000, 0b1011, 0b00, (outs DPR:$dst),
- (ins DPR:$src1, GPR:$src2, lane_cst:$lane),
+ (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
NoItinerary, "vmov", ".32\t$dst[$lane], $src2",
[(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
GPR:$src2, imm:$lane))]>;
@@ -1788,14 +1788,14 @@
class VDUPLND<bits<2> op19_18, bits<2> op17_16, string OpcodeStr, ValueType Ty>
: N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0,
- (outs DPR:$dst), (ins DPR:$src, lane_cst:$lane), NoItinerary,
+ (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane), NoItinerary,
!strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
[(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>;
class VDUPLNQ<bits<2> op19_18, bits<2> op17_16, string OpcodeStr,
ValueType ResTy, ValueType OpTy>
: N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0,
- (outs QPR:$dst), (ins DPR:$src, lane_cst:$lane), NoItinerary,
+ (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane), NoItinerary,
!strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
[(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src), imm:$lane)))]>;
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=79676&r1=79675&r2=79676&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Fri Aug 21 16:58:55 2009
@@ -632,7 +632,7 @@
"adr$p $dst, #$label", []>;
def tLEApcrelJT : T1I<(outs tGPR:$dst),
- (ins i32imm:$label, lane_cst:$id, pred:$p),
+ (ins i32imm:$label, nohash_imm:$id, pred:$p),
IIC_iALUi, "adr$p $dst, #${label}_${id}", []>;
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=79676&r1=79675&r2=79676&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Fri Aug 21 16:58:55 2009
@@ -431,7 +431,7 @@
"adr$p.w $dst, #$label", []>;
def t2LEApcrelJT : T2XI<(outs GPR:$dst),
- (ins i32imm:$label, lane_cst:$id, pred:$p), IIC_iALUi,
+ (ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi,
"adr$p.w $dst, #${label}_${id}", []>;
// ADD r, sp, {so_imm|i12}
Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=79676&r1=79675&r2=79676&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Fri Aug 21 16:58:55 2009
@@ -164,7 +164,7 @@
void printJTBlockOperand(const MachineInstr *MI, int OpNum);
void printJT2BlockOperand(const MachineInstr *MI, int OpNum);
void printTBAddrMode(const MachineInstr *MI, int OpNum);
- void printLaneOperand(const MachineInstr *MI, int OpNum);
+ void printNoHashImmediate(const MachineInstr *MI, int OpNum);
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
unsigned AsmVariant, const char *ExtraCode);
@@ -1010,7 +1010,7 @@
O << ']';
}
-void ARMAsmPrinter::printLaneOperand(const MachineInstr *MI, int OpNum) {
+void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum) {
O << MI->getOperand(OpNum).getImm();
}
@@ -1029,7 +1029,9 @@
}
// Fallthrough
case 'c': // Don't print "#" before an immediate operand.
- printLaneOperand(MI, OpNum);
+ if (!MI->getOperand(OpNum).isImm())
+ return true;
+ printNoHashImmediate(MI, OpNum);
return false;
case 'P': // Print a VFP double precision register.
printOperand(MI, OpNum);
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