[llvm-commits] [llvm] r61603 - in /llvm/trunk/lib/Target/X86: X86.td X86Subtarget.cpp

[Evan Cheng]

Author: evancheng
Date: Fri Jan  2 22:24:44 2009
New Revision: 61603

URL: http://llvm.org/viewvc/llvm-project?rev=61603&view=rev
Log:
Add Intel processors core i7 and atom.

Modified:
    llvm/trunk/lib/Target/X86/X86.td
    llvm/trunk/lib/Target/X86/X86Subtarget.cpp

Modified: llvm/trunk/lib/Target/X86/X86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=61603&r1=61602&r2=61603&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86.td (original)
+++ llvm/trunk/lib/Target/X86/X86.td Fri Jan  2 22:24:44 2009
@@ -76,6 +76,8 @@
 def : Proc<"nocona",          [FeatureSSE3,   Feature64Bit, FeatureSlowBTMem]>;
 def : Proc<"core2",           [FeatureSSSE3,  Feature64Bit, FeatureSlowBTMem]>;
 def : Proc<"penryn",          [FeatureSSE41,  Feature64Bit, FeatureSlowBTMem]>;
+def : Proc<"atom",            [FeatureSSE3,   Feature64Bit, FeatureSlowBTMem]>;
+def : Proc<"corei7",          [FeatureSSE42,  Feature64Bit, FeatureSlowBTMem]>;
 
 def : Proc<"k6",              [FeatureMMX]>;
 def : Proc<"k6-2",            [FeatureMMX,    Feature3DNow]>;

Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=61603&r1=61602&r2=61603&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Fri Jan  2 22:24:44 2009
@@ -204,6 +204,7 @@
   unsigned Family = 0;
   unsigned Model  = 0;
   DetectFamilyModel(EAX, Family, Model);
+  bool HasSSE42 = (ECX >> 19) & 0x1;
 
   X86::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
   bool Em64T = (EDX >> 29) & 0x1;
@@ -254,7 +255,7 @@
         case 28:
           // Intel Atom, and Core i7 both have this model.
           // Atom has SSSE3, Core i7 has SSE4.2
-          return "core2";
+          return (HasSSE42) ? "corei7" : "atom";
         default:
           return (Em64T) ? "x86-64" : "pentium4";
         }