[llvm-commits] [llvm] r59756 - /llvm/trunk/include/llvm/Intrinsics.td

[Evan Cheng]

Yes, we'll add the equivalents for subtraction.

Evan

On Nov 21, 2008, at 2:16 AM, Richard Osborne wrote:

>>
> Having the carry bit explicitly modelled would be useful for the XCore
> target. On the XCore there is no carry flag but there is a ladd
> instruction where is carry bit is written back to a genral purpose
> register. The XCore backend currently has to custom expand 64bit
> addition / subtraction, but it if addition was expanded to multiple
> UADDO when the target does not support ADDC the XCore backend could
> match the resulting UADDO nodes directly.
>
> Would it make sense to add equivalents for subtraction?
>
> -- 
> Richard Osborne | XMOS
> http://www.xmos.com
>
>>> Ciao,
>>>
>>> Duncan.
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