[llvm-commits] [llvm] r59756 - /llvm/trunk/include/llvm/Intrinsics.td
richard at xmos.com
Fri Nov 21 02:16:46 PST 2008
Evan Cheng wrote:
> On Nov 21, 2008, at 12:42 AM, Duncan Sands wrote:
>> Hi Bill,
>>> Introduce two new "add" intrinsics. These return the sum plus a bit
>>> that an overflow/carry occured. These are converted into ISD::
>>> [SU]ADDO nodes,
>>> which are lowered in a target-independent way into something sane.
>>> each target can implement their own method of checking the overflow/
>>> carry flags.
>> are these really needed? Suppose you want to do 32 bit addition of
>> x and y.
>> Zero extend x and y to i33. Do the addition in i33 and check the
>> top bit.
>> If it is non-zero then there was a carry/overflow. In codegen this
>> gets turned
>> into an ADDC node (sounds a lot like your ADDO node...), and on x86
>> at least
>> turns by magic into a check on the carry flag. So at first glance
>> it seems that
>> everything is already supported.
> Can codegen really handle i33 arithmetic? Even if it does,
> transforming it the ADDC / ADDO + check probably requires quite a bit
> of work in dag combine. We'd also like to support it in fast-isel. I
> think the intrinsics are needed, at least in the short term.
> As for ADDC vs ADDO. I think we have come to the same conclusion. I
> like to explicitly modeled the carry bit. In the end one of them
> probably should be eliminated. But that may take a bit of effort.
Having the carry bit explicitly modelled would be useful for the XCore
target. On the XCore there is no carry flag but there is a ladd
instruction where is carry bit is written back to a genral purpose
register. The XCore backend currently has to custom expand 64bit
addition / subtraction, but it if addition was expanded to multiple
UADDO when the target does not support ADDC the XCore backend could
match the resulting UADDO nodes directly.
Would it make sense to add equivalents for subtraction?
Richard Osborne | XMOS
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