[llvm-commits] [llvm] r54128 [1/2] - in /llvm/trunk: docs/ include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/CellSPU/ lib/Target/IA64/ lib/Target/Mips/ lib/Target/PIC16/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/X86/ lib/Transforms/Scalar/ utils/TableGen/
Dan Gohman
gohman at apple.com
Sun Jul 27 14:46:05 PDT 2008
Author: djg
Date: Sun Jul 27 16:46:04 2008
New Revision: 54128
URL: http://llvm.org/viewvc/llvm-project?rev=54128&view=rev
Log:
Rename SDOperand to SDValue.
Modified:
llvm/trunk/docs/CodeGenerator.html
llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h
llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h
llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
llvm/trunk/include/llvm/Target/TargetLowering.h
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/trunk/lib/Target/ARM/ARMAddressingModes.h
llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
llvm/trunk/lib/Target/ARM/ARMISelLowering.h
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp
llvm/trunk/lib/Target/Alpha/AlphaISelLowering.h
llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td
llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h
llvm/trunk/lib/Target/CellSPU/SPUOperands.td
llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp
llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp
llvm/trunk/lib/Target/IA64/IA64ISelLowering.h
llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
llvm/trunk/lib/Target/Mips/MipsISelLowering.h
llvm/trunk/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp
llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h
llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.cpp
llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.h
llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp
llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
llvm/trunk/lib/Target/Sparc/SparcISelLowering.h
llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.h
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp
llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
Modified: llvm/trunk/docs/CodeGenerator.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CodeGenerator.html?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/docs/CodeGenerator.html (original)
+++ llvm/trunk/docs/CodeGenerator.html Sun Jul 27 16:46:04 2008
@@ -787,7 +787,7 @@
both the dividend and the remainder. Many other situations require multiple
values as well. Each node also has some number of operands, which are edges
to the node defining the used value. Because nodes may define multiple values,
-edges are represented by instances of the <tt>SDOperand</tt> class, which is
+edges are represented by instances of the <tt>SDValue</tt> class, which is
a <tt><SDNode, unsigned></tt> pair, indicating the node and result
value being used, respectively. Each value produced by an <tt>SDNode</tt> has
an associated <tt>MVT</tt> (Machine Value Type) indicating what the type of the
Modified: llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h (original)
+++ llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h Sun Jul 27 16:46:04 2008
@@ -35,7 +35,7 @@
else if (Chain->getOpcode() == ISD::TokenFactor)
return false;
else if (Chain->getNumOperands() > 0) {
- SDOperand C0 = Chain->getOperand(0);
+ SDValue C0 = Chain->getOperand(0);
if (C0.getValueType() == MVT::Other)
return C0.Val != Op && IsChainCompatible(C0.Val, Op);
}
@@ -75,7 +75,7 @@
/// AddToISelQueue - adds a node to the instruction
/// selection queue.
-void AddToISelQueue(SDOperand N) DISABLE_INLINE {
+void AddToISelQueue(SDValue N) DISABLE_INLINE {
int Id = N.Val->getNodeId();
if (Id != -1 && !isQueued(Id)) {
ISelQueue.push_back(N.Val);
@@ -117,7 +117,7 @@
/// ReplaceUses - replace all uses of the old node F with the use
/// of the new node T.
-void ReplaceUses(SDOperand F, SDOperand T) DISABLE_INLINE {
+void ReplaceUses(SDValue F, SDValue T) DISABLE_INLINE {
ISelQueueUpdater ISQU(ISelQueue);
CurDAG->ReplaceAllUsesOfValueWith(F, T, &ISQU);
setSelected(F.Val->getNodeId());
@@ -126,7 +126,7 @@
/// ReplaceUses - replace all uses of the old nodes F with the use
/// of the new nodes T.
-void ReplaceUses(const SDOperand *F, const SDOperand *T,
+void ReplaceUses(const SDValue *F, const SDValue *T,
unsigned Num) DISABLE_INLINE {
ISelQueueUpdater ISQU(ISelQueue);
CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num, &ISQU);
@@ -143,7 +143,7 @@
ISelQueueUpdater ISQU(ISelQueue);
if (FNumVals != TNumVals) {
for (unsigned i = 0, e = std::min(FNumVals, TNumVals); i < e; ++i)
- CurDAG->ReplaceAllUsesOfValueWith(SDOperand(F, i), SDOperand(T, i), &ISQU);
+ CurDAG->ReplaceAllUsesOfValueWith(SDValue(F, i), SDValue(T, i), &ISQU);
} else {
CurDAG->ReplaceAllUsesWith(F, T, &ISQU);
}
@@ -153,7 +153,7 @@
/// SelectRoot - Top level entry to DAG instruction selector.
/// Selects instructions starting at the root of the current DAG.
-SDOperand SelectRoot(SDOperand Root) {
+SDValue SelectRoot(SDValue Root) {
SelectRootInit();
unsigned NumBytes = (DAGSize + 7) / 8;
ISelQueued = new unsigned char[NumBytes];
@@ -176,7 +176,7 @@
// Skip already selected nodes.
if (isSelected(Node->getNodeId()))
continue;
- SDNode *ResNode = Select(SDOperand(Node, 0));
+ SDNode *ResNode = Select(SDValue(Node, 0));
// If node should not be replaced,
// continue with the next one.
if (ResNode == Node)
Modified: llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h Sun Jul 27 16:46:04 2008
@@ -330,7 +330,7 @@
/// register number for the results of the node.
///
void EmitNode(SDNode *Node, bool IsClone,
- DenseMap<SDOperand, unsigned> &VRBaseMap);
+ DenseMap<SDValue, unsigned> &VRBaseMap);
/// EmitNoop - Emit a noop instruction.
///
@@ -349,19 +349,19 @@
/// EmitSubregNode - Generate machine code for subreg nodes.
///
void EmitSubregNode(SDNode *Node,
- DenseMap<SDOperand, unsigned> &VRBaseMap);
+ DenseMap<SDValue, unsigned> &VRBaseMap);
/// getVR - Return the virtual register corresponding to the specified result
/// of the specified node.
- unsigned getVR(SDOperand Op, DenseMap<SDOperand, unsigned> &VRBaseMap);
+ unsigned getVR(SDValue Op, DenseMap<SDValue, unsigned> &VRBaseMap);
/// getDstOfCopyToRegUse - If the only use of the specified result number of
/// node is a CopyToReg, return its destination register. Return 0 otherwise.
unsigned getDstOfOnlyCopyToRegUse(SDNode *Node, unsigned ResNo) const;
- void AddOperand(MachineInstr *MI, SDOperand Op, unsigned IIOpNum,
+ void AddOperand(MachineInstr *MI, SDValue Op, unsigned IIOpNum,
const TargetInstrDesc *II,
- DenseMap<SDOperand, unsigned> &VRBaseMap);
+ DenseMap<SDValue, unsigned> &VRBaseMap);
void AddMemOperand(MachineInstr *MI, const MachineMemOperand &MO);
@@ -371,11 +371,11 @@
/// implicit physical register output.
void EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone,
unsigned SrcReg,
- DenseMap<SDOperand, unsigned> &VRBaseMap);
+ DenseMap<SDValue, unsigned> &VRBaseMap);
void CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
const TargetInstrDesc &II,
- DenseMap<SDOperand, unsigned> &VRBaseMap);
+ DenseMap<SDValue, unsigned> &VRBaseMap);
/// EmitLiveInCopy - Emit a copy for a live in physical register. If the
/// physical register has only a single copy use, then coalesced the copy
Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Sun Jul 27 16:46:04 2008
@@ -52,7 +52,7 @@
MachineModuleInfo *MMI;
/// Root - The root of the entire DAG. EntryNode - The starting token.
- SDOperand Root, EntryNode;
+ SDValue Root, EntryNode;
/// AllNodes - A linked list of nodes in the current DAG.
alist<SDNode, LargestSDNode> &AllNodes;
@@ -120,15 +120,15 @@
/// getRoot - Return the root tag of the SelectionDAG.
///
- const SDOperand &getRoot() const { return Root; }
+ const SDValue &getRoot() const { return Root; }
/// getEntryNode - Return the token chain corresponding to the entry of the
/// function.
- const SDOperand &getEntryNode() const { return EntryNode; }
+ const SDValue &getEntryNode() const { return EntryNode; }
/// setRoot - Set the current root tag of the SelectionDAG.
///
- const SDOperand &setRoot(SDOperand N) {
+ const SDValue &setRoot(SDValue N) {
assert((!N.Val || N.getValueType() == MVT::Other) &&
"DAG root value is not a chain!");
return Root = N;
@@ -188,61 +188,61 @@
//===--------------------------------------------------------------------===//
// Node creation methods.
//
- SDOperand getConstant(uint64_t Val, MVT VT, bool isTarget = false);
- SDOperand getConstant(const APInt &Val, MVT VT, bool isTarget = false);
- SDOperand getIntPtrConstant(uint64_t Val, bool isTarget = false);
- SDOperand getTargetConstant(uint64_t Val, MVT VT) {
+ SDValue getConstant(uint64_t Val, MVT VT, bool isTarget = false);
+ SDValue getConstant(const APInt &Val, MVT VT, bool isTarget = false);
+ SDValue getIntPtrConstant(uint64_t Val, bool isTarget = false);
+ SDValue getTargetConstant(uint64_t Val, MVT VT) {
return getConstant(Val, VT, true);
}
- SDOperand getTargetConstant(const APInt &Val, MVT VT) {
+ SDValue getTargetConstant(const APInt &Val, MVT VT) {
return getConstant(Val, VT, true);
}
- SDOperand getConstantFP(double Val, MVT VT, bool isTarget = false);
- SDOperand getConstantFP(const APFloat& Val, MVT VT, bool isTarget = false);
- SDOperand getTargetConstantFP(double Val, MVT VT) {
+ SDValue getConstantFP(double Val, MVT VT, bool isTarget = false);
+ SDValue getConstantFP(const APFloat& Val, MVT VT, bool isTarget = false);
+ SDValue getTargetConstantFP(double Val, MVT VT) {
return getConstantFP(Val, VT, true);
}
- SDOperand getTargetConstantFP(const APFloat& Val, MVT VT) {
+ SDValue getTargetConstantFP(const APFloat& Val, MVT VT) {
return getConstantFP(Val, VT, true);
}
- SDOperand getGlobalAddress(const GlobalValue *GV, MVT VT,
+ SDValue getGlobalAddress(const GlobalValue *GV, MVT VT,
int offset = 0, bool isTargetGA = false);
- SDOperand getTargetGlobalAddress(const GlobalValue *GV, MVT VT,
+ SDValue getTargetGlobalAddress(const GlobalValue *GV, MVT VT,
int offset = 0) {
return getGlobalAddress(GV, VT, offset, true);
}
- SDOperand getFrameIndex(int FI, MVT VT, bool isTarget = false);
- SDOperand getTargetFrameIndex(int FI, MVT VT) {
+ SDValue getFrameIndex(int FI, MVT VT, bool isTarget = false);
+ SDValue getTargetFrameIndex(int FI, MVT VT) {
return getFrameIndex(FI, VT, true);
}
- SDOperand getJumpTable(int JTI, MVT VT, bool isTarget = false);
- SDOperand getTargetJumpTable(int JTI, MVT VT) {
+ SDValue getJumpTable(int JTI, MVT VT, bool isTarget = false);
+ SDValue getTargetJumpTable(int JTI, MVT VT) {
return getJumpTable(JTI, VT, true);
}
- SDOperand getConstantPool(Constant *C, MVT VT,
+ SDValue getConstantPool(Constant *C, MVT VT,
unsigned Align = 0, int Offs = 0, bool isT=false);
- SDOperand getTargetConstantPool(Constant *C, MVT VT,
+ SDValue getTargetConstantPool(Constant *C, MVT VT,
unsigned Align = 0, int Offset = 0) {
return getConstantPool(C, VT, Align, Offset, true);
}
- SDOperand getConstantPool(MachineConstantPoolValue *C, MVT VT,
+ SDValue getConstantPool(MachineConstantPoolValue *C, MVT VT,
unsigned Align = 0, int Offs = 0, bool isT=false);
- SDOperand getTargetConstantPool(MachineConstantPoolValue *C,
+ SDValue getTargetConstantPool(MachineConstantPoolValue *C,
MVT VT, unsigned Align = 0,
int Offset = 0) {
return getConstantPool(C, VT, Align, Offset, true);
}
- SDOperand getBasicBlock(MachineBasicBlock *MBB);
- SDOperand getExternalSymbol(const char *Sym, MVT VT);
- SDOperand getTargetExternalSymbol(const char *Sym, MVT VT);
- SDOperand getArgFlags(ISD::ArgFlagsTy Flags);
- SDOperand getValueType(MVT);
- SDOperand getRegister(unsigned Reg, MVT VT);
- SDOperand getDbgStopPoint(SDOperand Root, unsigned Line, unsigned Col,
+ SDValue getBasicBlock(MachineBasicBlock *MBB);
+ SDValue getExternalSymbol(const char *Sym, MVT VT);
+ SDValue getTargetExternalSymbol(const char *Sym, MVT VT);
+ SDValue getArgFlags(ISD::ArgFlagsTy Flags);
+ SDValue getValueType(MVT);
+ SDValue getRegister(unsigned Reg, MVT VT);
+ SDValue getDbgStopPoint(SDValue Root, unsigned Line, unsigned Col,
const CompileUnitDesc *CU);
- SDOperand getLabel(unsigned Opcode, SDOperand Root, unsigned LabelID);
+ SDValue getLabel(unsigned Opcode, SDValue Root, unsigned LabelID);
- SDOperand getCopyToReg(SDOperand Chain, unsigned Reg, SDOperand N) {
+ SDValue getCopyToReg(SDValue Chain, unsigned Reg, SDValue N) {
return getNode(ISD::CopyToReg, MVT::Other, Chain,
getRegister(Reg, N.getValueType()), N);
}
@@ -250,57 +250,57 @@
// This version of the getCopyToReg method takes an extra operand, which
// indicates that there is potentially an incoming flag value (if Flag is not
// null) and that there should be a flag result.
- SDOperand getCopyToReg(SDOperand Chain, unsigned Reg, SDOperand N,
- SDOperand Flag) {
+ SDValue getCopyToReg(SDValue Chain, unsigned Reg, SDValue N,
+ SDValue Flag) {
const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag);
- SDOperand Ops[] = { Chain, getRegister(Reg, N.getValueType()), N, Flag };
+ SDValue Ops[] = { Chain, getRegister(Reg, N.getValueType()), N, Flag };
return getNode(ISD::CopyToReg, VTs, 2, Ops, Flag.Val ? 4 : 3);
}
- // Similar to last getCopyToReg() except parameter Reg is a SDOperand
- SDOperand getCopyToReg(SDOperand Chain, SDOperand Reg, SDOperand N,
- SDOperand Flag) {
+ // Similar to last getCopyToReg() except parameter Reg is a SDValue
+ SDValue getCopyToReg(SDValue Chain, SDValue Reg, SDValue N,
+ SDValue Flag) {
const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag);
- SDOperand Ops[] = { Chain, Reg, N, Flag };
+ SDValue Ops[] = { Chain, Reg, N, Flag };
return getNode(ISD::CopyToReg, VTs, 2, Ops, Flag.Val ? 4 : 3);
}
- SDOperand getCopyFromReg(SDOperand Chain, unsigned Reg, MVT VT) {
+ SDValue getCopyFromReg(SDValue Chain, unsigned Reg, MVT VT) {
const MVT *VTs = getNodeValueTypes(VT, MVT::Other);
- SDOperand Ops[] = { Chain, getRegister(Reg, VT) };
+ SDValue Ops[] = { Chain, getRegister(Reg, VT) };
return getNode(ISD::CopyFromReg, VTs, 2, Ops, 2);
}
// This version of the getCopyFromReg method takes an extra operand, which
// indicates that there is potentially an incoming flag value (if Flag is not
// null) and that there should be a flag result.
- SDOperand getCopyFromReg(SDOperand Chain, unsigned Reg, MVT VT,
- SDOperand Flag) {
+ SDValue getCopyFromReg(SDValue Chain, unsigned Reg, MVT VT,
+ SDValue Flag) {
const MVT *VTs = getNodeValueTypes(VT, MVT::Other, MVT::Flag);
- SDOperand Ops[] = { Chain, getRegister(Reg, VT), Flag };
+ SDValue Ops[] = { Chain, getRegister(Reg, VT), Flag };
return getNode(ISD::CopyFromReg, VTs, 3, Ops, Flag.Val ? 3 : 2);
}
- SDOperand getCondCode(ISD::CondCode Cond);
+ SDValue getCondCode(ISD::CondCode Cond);
/// getZeroExtendInReg - Return the expression required to zero extend the Op
/// value assuming it was the smaller SrcTy value.
- SDOperand getZeroExtendInReg(SDOperand Op, MVT SrcTy);
+ SDValue getZeroExtendInReg(SDValue Op, MVT SrcTy);
/// getCALLSEQ_START - Return a new CALLSEQ_START node, which always must have
/// a flag result (to ensure it's not CSE'd).
- SDOperand getCALLSEQ_START(SDOperand Chain, SDOperand Op) {
+ SDValue getCALLSEQ_START(SDValue Chain, SDValue Op) {
const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag);
- SDOperand Ops[] = { Chain, Op };
+ SDValue Ops[] = { Chain, Op };
return getNode(ISD::CALLSEQ_START, VTs, 2, Ops, 2);
}
/// getCALLSEQ_END - Return a new CALLSEQ_END node, which always must have a
/// flag result (to ensure it's not CSE'd).
- SDOperand getCALLSEQ_END(SDOperand Chain, SDOperand Op1, SDOperand Op2,
- SDOperand InFlag) {
+ SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2,
+ SDValue InFlag) {
SDVTList NodeTys = getVTList(MVT::Other, MVT::Flag);
- SmallVector<SDOperand, 4> Ops;
+ SmallVector<SDValue, 4> Ops;
Ops.push_back(Chain);
Ops.push_back(Op1);
Ops.push_back(Op2);
@@ -311,103 +311,103 @@
/// getNode - Gets or creates the specified node.
///
- SDOperand getNode(unsigned Opcode, MVT VT);
- SDOperand getNode(unsigned Opcode, MVT VT, SDOperand N);
- SDOperand getNode(unsigned Opcode, MVT VT, SDOperand N1, SDOperand N2);
- SDOperand getNode(unsigned Opcode, MVT VT,
- SDOperand N1, SDOperand N2, SDOperand N3);
- SDOperand getNode(unsigned Opcode, MVT VT,
- SDOperand N1, SDOperand N2, SDOperand N3, SDOperand N4);
- SDOperand getNode(unsigned Opcode, MVT VT,
- SDOperand N1, SDOperand N2, SDOperand N3, SDOperand N4,
- SDOperand N5);
- SDOperand getNode(unsigned Opcode, MVT VT,
- const SDOperand *Ops, unsigned NumOps);
- SDOperand getNode(unsigned Opcode, MVT VT,
+ SDValue getNode(unsigned Opcode, MVT VT);
+ SDValue getNode(unsigned Opcode, MVT VT, SDValue N);
+ SDValue getNode(unsigned Opcode, MVT VT, SDValue N1, SDValue N2);
+ SDValue getNode(unsigned Opcode, MVT VT,
+ SDValue N1, SDValue N2, SDValue N3);
+ SDValue getNode(unsigned Opcode, MVT VT,
+ SDValue N1, SDValue N2, SDValue N3, SDValue N4);
+ SDValue getNode(unsigned Opcode, MVT VT,
+ SDValue N1, SDValue N2, SDValue N3, SDValue N4,
+ SDValue N5);
+ SDValue getNode(unsigned Opcode, MVT VT,
+ const SDValue *Ops, unsigned NumOps);
+ SDValue getNode(unsigned Opcode, MVT VT,
const SDUse *Ops, unsigned NumOps);
- SDOperand getNode(unsigned Opcode, const std::vector<MVT> &ResultTys,
- const SDOperand *Ops, unsigned NumOps);
- SDOperand getNode(unsigned Opcode, const MVT *VTs, unsigned NumVTs,
- const SDOperand *Ops, unsigned NumOps);
- SDOperand getNode(unsigned Opcode, SDVTList VTs);
- SDOperand getNode(unsigned Opcode, SDVTList VTs, SDOperand N);
- SDOperand getNode(unsigned Opcode, SDVTList VTs, SDOperand N1, SDOperand N2);
- SDOperand getNode(unsigned Opcode, SDVTList VTs,
- SDOperand N1, SDOperand N2, SDOperand N3);
- SDOperand getNode(unsigned Opcode, SDVTList VTs,
- SDOperand N1, SDOperand N2, SDOperand N3, SDOperand N4);
- SDOperand getNode(unsigned Opcode, SDVTList VTs,
- SDOperand N1, SDOperand N2, SDOperand N3, SDOperand N4,
- SDOperand N5);
- SDOperand getNode(unsigned Opcode, SDVTList VTs,
- const SDOperand *Ops, unsigned NumOps);
+ SDValue getNode(unsigned Opcode, const std::vector<MVT> &ResultTys,
+ const SDValue *Ops, unsigned NumOps);
+ SDValue getNode(unsigned Opcode, const MVT *VTs, unsigned NumVTs,
+ const SDValue *Ops, unsigned NumOps);
+ SDValue getNode(unsigned Opcode, SDVTList VTs);
+ SDValue getNode(unsigned Opcode, SDVTList VTs, SDValue N);
+ SDValue getNode(unsigned Opcode, SDVTList VTs, SDValue N1, SDValue N2);
+ SDValue getNode(unsigned Opcode, SDVTList VTs,
+ SDValue N1, SDValue N2, SDValue N3);
+ SDValue getNode(unsigned Opcode, SDVTList VTs,
+ SDValue N1, SDValue N2, SDValue N3, SDValue N4);
+ SDValue getNode(unsigned Opcode, SDVTList VTs,
+ SDValue N1, SDValue N2, SDValue N3, SDValue N4,
+ SDValue N5);
+ SDValue getNode(unsigned Opcode, SDVTList VTs,
+ const SDValue *Ops, unsigned NumOps);
- SDOperand getMemcpy(SDOperand Chain, SDOperand Dst, SDOperand Src,
- SDOperand Size, unsigned Align,
+ SDValue getMemcpy(SDValue Chain, SDValue Dst, SDValue Src,
+ SDValue Size, unsigned Align,
bool AlwaysInline,
const Value *DstSV, uint64_t DstSVOff,
const Value *SrcSV, uint64_t SrcSVOff);
- SDOperand getMemmove(SDOperand Chain, SDOperand Dst, SDOperand Src,
- SDOperand Size, unsigned Align,
+ SDValue getMemmove(SDValue Chain, SDValue Dst, SDValue Src,
+ SDValue Size, unsigned Align,
const Value *DstSV, uint64_t DstOSVff,
const Value *SrcSV, uint64_t SrcSVOff);
- SDOperand getMemset(SDOperand Chain, SDOperand Dst, SDOperand Src,
- SDOperand Size, unsigned Align,
+ SDValue getMemset(SDValue Chain, SDValue Dst, SDValue Src,
+ SDValue Size, unsigned Align,
const Value *DstSV, uint64_t DstSVOff);
/// getSetCC - Helper function to make it easier to build SetCC's if you just
- /// have an ISD::CondCode instead of an SDOperand.
+ /// have an ISD::CondCode instead of an SDValue.
///
- SDOperand getSetCC(MVT VT, SDOperand LHS, SDOperand RHS,
+ SDValue getSetCC(MVT VT, SDValue LHS, SDValue RHS,
ISD::CondCode Cond) {
return getNode(ISD::SETCC, VT, LHS, RHS, getCondCode(Cond));
}
/// getVSetCC - Helper function to make it easier to build VSetCC's nodes
- /// if you just have an ISD::CondCode instead of an SDOperand.
+ /// if you just have an ISD::CondCode instead of an SDValue.
///
- SDOperand getVSetCC(MVT VT, SDOperand LHS, SDOperand RHS,
+ SDValue getVSetCC(MVT VT, SDValue LHS, SDValue RHS,
ISD::CondCode Cond) {
return getNode(ISD::VSETCC, VT, LHS, RHS, getCondCode(Cond));
}
/// getSelectCC - Helper function to make it easier to build SelectCC's if you
- /// just have an ISD::CondCode instead of an SDOperand.
+ /// just have an ISD::CondCode instead of an SDValue.
///
- SDOperand getSelectCC(SDOperand LHS, SDOperand RHS,
- SDOperand True, SDOperand False, ISD::CondCode Cond) {
+ SDValue getSelectCC(SDValue LHS, SDValue RHS,
+ SDValue True, SDValue False, ISD::CondCode Cond) {
return getNode(ISD::SELECT_CC, True.getValueType(), LHS, RHS, True, False,
getCondCode(Cond));
}
/// getVAArg - VAArg produces a result and token chain, and takes a pointer
/// and a source value as input.
- SDOperand getVAArg(MVT VT, SDOperand Chain, SDOperand Ptr,
- SDOperand SV);
+ SDValue getVAArg(MVT VT, SDValue Chain, SDValue Ptr,
+ SDValue SV);
/// getAtomic - Gets a node for an atomic op, produces result and chain, takes
/// 3 operands
- SDOperand getAtomic(unsigned Opcode, SDOperand Chain, SDOperand Ptr,
- SDOperand Cmp, SDOperand Swp, const Value* PtrVal,
+ SDValue getAtomic(unsigned Opcode, SDValue Chain, SDValue Ptr,
+ SDValue Cmp, SDValue Swp, const Value* PtrVal,
unsigned Alignment=0);
/// getAtomic - Gets a node for an atomic op, produces result and chain, takes
/// 2 operands
- SDOperand getAtomic(unsigned Opcode, SDOperand Chain, SDOperand Ptr,
- SDOperand Val, const Value* PtrVal,
+ SDValue getAtomic(unsigned Opcode, SDValue Chain, SDValue Ptr,
+ SDValue Val, const Value* PtrVal,
unsigned Alignment = 0);
/// getMergeValues - Create a MERGE_VALUES node from the given operands.
/// Allowed to return something different (and simpler) if Simplify is true.
- SDOperand getMergeValues(const SDOperand *Ops, unsigned NumOps,
+ SDValue getMergeValues(const SDValue *Ops, unsigned NumOps,
bool Simplify = true);
/// getMergeValues - Create a MERGE_VALUES node from the given types and ops.
/// Allowed to return something different (and simpler) if Simplify is true.
/// May be faster than the above version if VTs is known and NumOps is large.
- SDOperand getMergeValues(SDVTList VTs, const SDOperand *Ops, unsigned NumOps,
+ SDValue getMergeValues(SDVTList VTs, const SDValue *Ops, unsigned NumOps,
bool Simplify = true) {
if (Simplify && NumOps == 1)
return Ops[0];
@@ -417,38 +417,38 @@
/// getLoad - Loads are not normal binary operators: their result type is not
/// determined by their operands, and they produce a value AND a token chain.
///
- SDOperand getLoad(MVT VT, SDOperand Chain, SDOperand Ptr,
+ SDValue getLoad(MVT VT, SDValue Chain, SDValue Ptr,
const Value *SV, int SVOffset, bool isVolatile=false,
unsigned Alignment=0);
- SDOperand getExtLoad(ISD::LoadExtType ExtType, MVT VT,
- SDOperand Chain, SDOperand Ptr, const Value *SV,
+ SDValue getExtLoad(ISD::LoadExtType ExtType, MVT VT,
+ SDValue Chain, SDValue Ptr, const Value *SV,
int SVOffset, MVT EVT, bool isVolatile=false,
unsigned Alignment=0);
- SDOperand getIndexedLoad(SDOperand OrigLoad, SDOperand Base,
- SDOperand Offset, ISD::MemIndexedMode AM);
- SDOperand getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
- MVT VT, SDOperand Chain,
- SDOperand Ptr, SDOperand Offset,
+ SDValue getIndexedLoad(SDValue OrigLoad, SDValue Base,
+ SDValue Offset, ISD::MemIndexedMode AM);
+ SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
+ MVT VT, SDValue Chain,
+ SDValue Ptr, SDValue Offset,
const Value *SV, int SVOffset, MVT EVT,
bool isVolatile=false, unsigned Alignment=0);
/// getStore - Helper function to build ISD::STORE nodes.
///
- SDOperand getStore(SDOperand Chain, SDOperand Val, SDOperand Ptr,
+ SDValue getStore(SDValue Chain, SDValue Val, SDValue Ptr,
const Value *SV, int SVOffset, bool isVolatile=false,
unsigned Alignment=0);
- SDOperand getTruncStore(SDOperand Chain, SDOperand Val, SDOperand Ptr,
+ SDValue getTruncStore(SDValue Chain, SDValue Val, SDValue Ptr,
const Value *SV, int SVOffset, MVT TVT,
bool isVolatile=false, unsigned Alignment=0);
- SDOperand getIndexedStore(SDOperand OrigStoe, SDOperand Base,
- SDOperand Offset, ISD::MemIndexedMode AM);
+ SDValue getIndexedStore(SDValue OrigStoe, SDValue Base,
+ SDValue Offset, ISD::MemIndexedMode AM);
// getSrcValue - Construct a node to track a Value* through the backend.
- SDOperand getSrcValue(const Value *v);
+ SDValue getSrcValue(const Value *v);
// getMemOperand - Construct a node to track a memory reference
// through the backend.
- SDOperand getMemOperand(const MachineMemOperand &MO);
+ SDValue getMemOperand(const MachineMemOperand &MO);
/// UpdateNodeOperands - *Mutate* the specified node in-place to have the
/// specified operands. If the resultant node already exists in the DAG,
@@ -456,66 +456,66 @@
/// already exists. If the resultant node does not exist in the DAG, the
/// input node is returned. As a degenerate case, if you specify the same
/// input operands as the node already has, the input node is returned.
- SDOperand UpdateNodeOperands(SDOperand N, SDOperand Op);
- SDOperand UpdateNodeOperands(SDOperand N, SDOperand Op1, SDOperand Op2);
- SDOperand UpdateNodeOperands(SDOperand N, SDOperand Op1, SDOperand Op2,
- SDOperand Op3);
- SDOperand UpdateNodeOperands(SDOperand N, SDOperand Op1, SDOperand Op2,
- SDOperand Op3, SDOperand Op4);
- SDOperand UpdateNodeOperands(SDOperand N, SDOperand Op1, SDOperand Op2,
- SDOperand Op3, SDOperand Op4, SDOperand Op5);
- SDOperand UpdateNodeOperands(SDOperand N,
- const SDOperand *Ops, unsigned NumOps);
+ SDValue UpdateNodeOperands(SDValue N, SDValue Op);
+ SDValue UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2);
+ SDValue UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2,
+ SDValue Op3);
+ SDValue UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2,
+ SDValue Op3, SDValue Op4);
+ SDValue UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2,
+ SDValue Op3, SDValue Op4, SDValue Op5);
+ SDValue UpdateNodeOperands(SDValue N,
+ const SDValue *Ops, unsigned NumOps);
/// SelectNodeTo - These are used for target selectors to *mutate* the
/// specified node to have the specified return type, Target opcode, and
/// operands. Note that target opcodes are stored as
/// ~TargetOpcode in the node opcode field. The resultant node is returned.
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT);
- SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT, SDOperand Op1);
+ SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT, SDValue Op1);
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT,
- SDOperand Op1, SDOperand Op2);
+ SDValue Op1, SDValue Op2);
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT,
- SDOperand Op1, SDOperand Op2, SDOperand Op3);
+ SDValue Op1, SDValue Op2, SDValue Op3);
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT,
- const SDOperand *Ops, unsigned NumOps);
+ const SDValue *Ops, unsigned NumOps);
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT1, MVT VT2);
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT1,
- MVT VT2, const SDOperand *Ops, unsigned NumOps);
+ MVT VT2, const SDValue *Ops, unsigned NumOps);
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT1,
- MVT VT2, MVT VT3, const SDOperand *Ops, unsigned NumOps);
+ MVT VT2, MVT VT3, const SDValue *Ops, unsigned NumOps);
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT1,
- MVT VT2, SDOperand Op1);
+ MVT VT2, SDValue Op1);
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT1,
- MVT VT2, SDOperand Op1, SDOperand Op2);
+ MVT VT2, SDValue Op1, SDValue Op2);
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT1,
- MVT VT2, SDOperand Op1, SDOperand Op2, SDOperand Op3);
+ MVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, SDVTList VTs,
- const SDOperand *Ops, unsigned NumOps);
+ const SDValue *Ops, unsigned NumOps);
/// MorphNodeTo - These *mutate* the specified node to have the specified
/// return type, opcode, and operands.
SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT);
- SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT, SDOperand Op1);
+ SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT, SDValue Op1);
SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT,
- SDOperand Op1, SDOperand Op2);
+ SDValue Op1, SDValue Op2);
SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT,
- SDOperand Op1, SDOperand Op2, SDOperand Op3);
+ SDValue Op1, SDValue Op2, SDValue Op3);
SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT,
- const SDOperand *Ops, unsigned NumOps);
+ const SDValue *Ops, unsigned NumOps);
SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT1, MVT VT2);
SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT1,
- MVT VT2, const SDOperand *Ops, unsigned NumOps);
+ MVT VT2, const SDValue *Ops, unsigned NumOps);
SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT1,
- MVT VT2, MVT VT3, const SDOperand *Ops, unsigned NumOps);
+ MVT VT2, MVT VT3, const SDValue *Ops, unsigned NumOps);
SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT1,
- MVT VT2, SDOperand Op1);
+ MVT VT2, SDValue Op1);
SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT1,
- MVT VT2, SDOperand Op1, SDOperand Op2);
+ MVT VT2, SDValue Op1, SDValue Op2);
SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT1,
- MVT VT2, SDOperand Op1, SDOperand Op2, SDOperand Op3);
+ MVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
SDNode *MorphNodeTo(SDNode *N, unsigned Opc, SDVTList VTs,
- const SDOperand *Ops, unsigned NumOps);
+ const SDValue *Ops, unsigned NumOps);
/// getTargetNode - These are used for target selectors to create a new node
/// with specified return type(s), target opcode, and operands.
@@ -524,35 +524,35 @@
/// node of the specified opcode and operands, it returns that node instead of
/// the current one.
SDNode *getTargetNode(unsigned Opcode, MVT VT);
- SDNode *getTargetNode(unsigned Opcode, MVT VT, SDOperand Op1);
- SDNode *getTargetNode(unsigned Opcode, MVT VT, SDOperand Op1, SDOperand Op2);
+ SDNode *getTargetNode(unsigned Opcode, MVT VT, SDValue Op1);
+ SDNode *getTargetNode(unsigned Opcode, MVT VT, SDValue Op1, SDValue Op2);
SDNode *getTargetNode(unsigned Opcode, MVT VT,
- SDOperand Op1, SDOperand Op2, SDOperand Op3);
+ SDValue Op1, SDValue Op2, SDValue Op3);
SDNode *getTargetNode(unsigned Opcode, MVT VT,
- const SDOperand *Ops, unsigned NumOps);
+ const SDValue *Ops, unsigned NumOps);
SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2);
- SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, SDOperand Op1);
+ SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, SDValue Op1);
SDNode *getTargetNode(unsigned Opcode, MVT VT1,
- MVT VT2, SDOperand Op1, SDOperand Op2);
+ MVT VT2, SDValue Op1, SDValue Op2);
SDNode *getTargetNode(unsigned Opcode, MVT VT1,
- MVT VT2, SDOperand Op1, SDOperand Op2, SDOperand Op3);
+ MVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2,
- const SDOperand *Ops, unsigned NumOps);
+ const SDValue *Ops, unsigned NumOps);
SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
- SDOperand Op1, SDOperand Op2);
+ SDValue Op1, SDValue Op2);
SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
- SDOperand Op1, SDOperand Op2, SDOperand Op3);
+ SDValue Op1, SDValue Op2, SDValue Op3);
SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
- const SDOperand *Ops, unsigned NumOps);
+ const SDValue *Ops, unsigned NumOps);
SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, MVT VT4,
- const SDOperand *Ops, unsigned NumOps);
+ const SDValue *Ops, unsigned NumOps);
SDNode *getTargetNode(unsigned Opcode, const std::vector<MVT> &ResultTys,
- const SDOperand *Ops, unsigned NumOps);
+ const SDValue *Ops, unsigned NumOps);
/// getNodeIfExists - Get the specified node if it's already available, or
/// else return NULL.
SDNode *getNodeIfExists(unsigned Opcode, SDVTList VTs,
- const SDOperand *Ops, unsigned NumOps);
+ const SDValue *Ops, unsigned NumOps);
/// DAGUpdateListener - Clients of various APIs that cause global effects on
/// the DAG can optionally implement this interface. This allows the clients
@@ -588,22 +588,22 @@
/// informed about nodes that are deleted and modified due to recursive
/// changes in the dag.
///
- void ReplaceAllUsesWith(SDOperand From, SDOperand Op,
+ void ReplaceAllUsesWith(SDValue From, SDValue Op,
DAGUpdateListener *UpdateListener = 0);
void ReplaceAllUsesWith(SDNode *From, SDNode *To,
DAGUpdateListener *UpdateListener = 0);
- void ReplaceAllUsesWith(SDNode *From, const SDOperand *To,
+ void ReplaceAllUsesWith(SDNode *From, const SDValue *To,
DAGUpdateListener *UpdateListener = 0);
/// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving
/// uses of other values produced by From.Val alone.
- void ReplaceAllUsesOfValueWith(SDOperand From, SDOperand To,
+ void ReplaceAllUsesOfValueWith(SDValue From, SDValue To,
DAGUpdateListener *UpdateListener = 0);
/// ReplaceAllUsesOfValuesWith - Like ReplaceAllUsesOfValueWith, but
/// for multiple values at once. This correctly handles the case where
/// there is an overlap between the From values and the To values.
- void ReplaceAllUsesOfValuesWith(const SDOperand *From, const SDOperand *To,
+ void ReplaceAllUsesOfValuesWith(const SDValue *From, const SDValue *To,
unsigned Num,
DAGUpdateListener *UpdateListener = 0);
@@ -640,20 +640,20 @@
/// CreateStackTemporary - Create a stack temporary, suitable for holding the
/// specified value type. If minAlign is specified, the slot size will have
/// at least that alignment.
- SDOperand CreateStackTemporary(MVT VT, unsigned minAlign = 1);
+ SDValue CreateStackTemporary(MVT VT, unsigned minAlign = 1);
/// FoldSetCC - Constant fold a setcc to true or false.
- SDOperand FoldSetCC(MVT VT, SDOperand N1,
- SDOperand N2, ISD::CondCode Cond);
+ SDValue FoldSetCC(MVT VT, SDValue N1,
+ SDValue N2, ISD::CondCode Cond);
/// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We
/// use this predicate to simplify operations downstream.
- bool SignBitIsZero(SDOperand Op, unsigned Depth = 0) const;
+ bool SignBitIsZero(SDValue Op, unsigned Depth = 0) const;
/// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We
/// use this predicate to simplify operations downstream. Op and Mask are
/// known to be the same type.
- bool MaskedValueIsZero(SDOperand Op, const APInt &Mask, unsigned Depth = 0)
+ bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth = 0)
const;
/// ComputeMaskedBits - Determine which of the bits specified in Mask are
@@ -661,7 +661,7 @@
/// bitsets. This code only analyzes bits in Mask, in order to short-circuit
/// processing. Targets can implement the computeMaskedBitsForTargetNode
/// method in the TargetLowering class to allow target nodes to be understood.
- void ComputeMaskedBits(SDOperand Op, const APInt &Mask, APInt &KnownZero,
+ void ComputeMaskedBits(SDValue Op, const APInt &Mask, APInt &KnownZero,
APInt &KnownOne, unsigned Depth = 0) const;
/// ComputeNumSignBits - Return the number of times the sign bit of the
@@ -671,24 +671,24 @@
/// the top 3 bits are all equal to each other, so we return 3. Targets can
/// implement the ComputeNumSignBitsForTarget method in the TargetLowering
/// class to allow target nodes to be understood.
- unsigned ComputeNumSignBits(SDOperand Op, unsigned Depth = 0) const;
+ unsigned ComputeNumSignBits(SDValue Op, unsigned Depth = 0) const;
- /// isVerifiedDebugInfoDesc - Returns true if the specified SDOperand has
+ /// isVerifiedDebugInfoDesc - Returns true if the specified SDValue has
/// been verified as a debug information descriptor.
- bool isVerifiedDebugInfoDesc(SDOperand Op) const;
+ bool isVerifiedDebugInfoDesc(SDValue Op) const;
/// getShuffleScalarElt - Returns the scalar element that will make up the ith
/// element of the result of the vector shuffle.
- SDOperand getShuffleScalarElt(const SDNode *N, unsigned Idx);
+ SDValue getShuffleScalarElt(const SDNode *N, unsigned Idx);
private:
inline alist_traits<SDNode, LargestSDNode>::AllocatorType &getAllocator();
void RemoveNodeFromCSEMaps(SDNode *N);
SDNode *AddNonLeafNodeToCSEMaps(SDNode *N);
- SDNode *FindModifiedNodeSlot(SDNode *N, SDOperand Op, void *&InsertPos);
- SDNode *FindModifiedNodeSlot(SDNode *N, SDOperand Op1, SDOperand Op2,
+ SDNode *FindModifiedNodeSlot(SDNode *N, SDValue Op, void *&InsertPos);
+ SDNode *FindModifiedNodeSlot(SDNode *N, SDValue Op1, SDValue Op2,
void *&InsertPos);
- SDNode *FindModifiedNodeSlot(SDNode *N, const SDOperand *Ops, unsigned NumOps,
+ SDNode *FindModifiedNodeSlot(SDNode *N, const SDValue *Ops, unsigned NumOps,
void *&InsertPos);
void DeleteNodeNotInCSEMaps(SDNode *N);
Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h Sun Jul 27 16:46:04 2008
@@ -21,7 +21,7 @@
namespace llvm {
class SelectionDAGLowering;
- class SDOperand;
+ class SDValue;
class MachineRegisterInfo;
class MachineBasicBlock;
class MachineFunction;
@@ -70,9 +70,9 @@
/// not match or is not implemented, return true. The resultant operands
/// (which will appear in the machine instruction) should be added to the
/// OutOps vector.
- virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
+ virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
char ConstraintCode,
- std::vector<SDOperand> &OutOps,
+ std::vector<SDValue> &OutOps,
SelectionDAG &DAG) {
return true;
}
@@ -168,13 +168,13 @@
/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
/// by tblgen. Others should not call it.
- void SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops,
+ void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops,
SelectionDAG &DAG);
// Calls to these predicates are generated by tblgen.
- bool CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
+ bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
int64_t DesiredMaskS) const;
- bool CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
+ bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
int64_t DesiredMaskS) const;
private:
Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Sun Jul 27 16:46:04 2008
@@ -795,7 +795,7 @@
//===----------------------------------------------------------------------===//
-/// SDOperand - Unlike LLVM values, Selection DAG nodes may return multiple
+/// SDValue - Unlike LLVM values, Selection DAG nodes may return multiple
/// values as the result of a computation. Many nodes return multiple values,
/// from loads (which define a token and a return value) to ADDC (which returns
/// a result and a carry value), to calls (which may return an arbitrary number
@@ -803,28 +803,28 @@
///
/// As such, each use of a SelectionDAG computation must indicate the node that
/// computes it as well as which return value to use from that node. This pair
-/// of information is represented with the SDOperand value type.
+/// of information is represented with the SDValue value type.
///
-class SDOperand {
+class SDValue {
public:
SDNode *Val; // The node defining the value we are using.
unsigned ResNo; // Which return value of the node we are using.
- SDOperand() : Val(0), ResNo(0) {}
- SDOperand(SDNode *val, unsigned resno) : Val(val), ResNo(resno) {}
+ SDValue() : Val(0), ResNo(0) {}
+ SDValue(SDNode *val, unsigned resno) : Val(val), ResNo(resno) {}
- bool operator==(const SDOperand &O) const {
+ bool operator==(const SDValue &O) const {
return Val == O.Val && ResNo == O.ResNo;
}
- bool operator!=(const SDOperand &O) const {
+ bool operator!=(const SDValue &O) const {
return !operator==(O);
}
- bool operator<(const SDOperand &O) const {
+ bool operator<(const SDValue &O) const {
return Val < O.Val || (Val == O.Val && ResNo < O.ResNo);
}
- SDOperand getValue(unsigned R) const {
- return SDOperand(Val, R);
+ SDValue getValue(unsigned R) const {
+ return SDValue(Val, R);
}
// isOperandOf - Return true if this node is an operand of N.
@@ -843,7 +843,7 @@
// Forwarding methods - These forward to the corresponding methods in SDNode.
inline unsigned getOpcode() const;
inline unsigned getNumOperands() const;
- inline const SDOperand &getOperand(unsigned i) const;
+ inline const SDValue &getOperand(unsigned i) const;
inline uint64_t getConstantOperandVal(unsigned i) const;
inline bool isTargetOpcode() const;
inline bool isMachineOpcode() const;
@@ -855,7 +855,7 @@
/// side-effecting instructions. In practice, this looks through token
/// factors and non-volatile loads. In order to remain efficient, this only
/// looks a couple of nodes in, it does not do an exhaustive search.
- bool reachesChainWithoutSideEffects(SDOperand Dest,
+ bool reachesChainWithoutSideEffects(SDValue Dest,
unsigned Depth = 2) const;
/// use_empty - Return true if there are no nodes using value ResNo
@@ -870,42 +870,42 @@
};
-template<> struct DenseMapInfo<SDOperand> {
- static inline SDOperand getEmptyKey() {
- return SDOperand((SDNode*)-1, -1U);
+template<> struct DenseMapInfo<SDValue> {
+ static inline SDValue getEmptyKey() {
+ return SDValue((SDNode*)-1, -1U);
}
- static inline SDOperand getTombstoneKey() {
- return SDOperand((SDNode*)-1, 0);
+ static inline SDValue getTombstoneKey() {
+ return SDValue((SDNode*)-1, 0);
}
- static unsigned getHashValue(const SDOperand &Val) {
+ static unsigned getHashValue(const SDValue &Val) {
return ((unsigned)((uintptr_t)Val.Val >> 4) ^
(unsigned)((uintptr_t)Val.Val >> 9)) + Val.ResNo;
}
- static bool isEqual(const SDOperand &LHS, const SDOperand &RHS) {
+ static bool isEqual(const SDValue &LHS, const SDValue &RHS) {
return LHS == RHS;
}
static bool isPod() { return true; }
};
/// simplify_type specializations - Allow casting operators to work directly on
-/// SDOperands as if they were SDNode*'s.
-template<> struct simplify_type<SDOperand> {
+/// SDValues as if they were SDNode*'s.
+template<> struct simplify_type<SDValue> {
typedef SDNode* SimpleType;
- static SimpleType getSimplifiedValue(const SDOperand &Val) {
+ static SimpleType getSimplifiedValue(const SDValue &Val) {
return static_cast<SimpleType>(Val.Val);
}
};
-template<> struct simplify_type<const SDOperand> {
+template<> struct simplify_type<const SDValue> {
typedef SDNode* SimpleType;
- static SimpleType getSimplifiedValue(const SDOperand &Val) {
+ static SimpleType getSimplifiedValue(const SDValue &Val) {
return static_cast<SimpleType>(Val.Val);
}
};
/// SDUse - Represents a use of the SDNode referred by
-/// the SDOperand.
+/// the SDValue.
class SDUse {
- SDOperand Operand;
+ SDValue Operand;
/// User - Parent node of this operand.
SDNode *User;
/// Prev, next - Pointers to the uses list of the SDNode referred by
@@ -918,7 +918,7 @@
SDUse(SDNode *val, unsigned resno) :
Operand(val,resno), User(NULL), Prev(NULL), Next(NULL) {}
- SDUse& operator= (const SDOperand& Op) {
+ SDUse& operator= (const SDValue& Op) {
Operand = Op;
Next = NULL;
Prev = NULL;
@@ -938,21 +938,22 @@
void setUser(SDNode *p) { User = p; }
- operator SDOperand() const { return Operand; }
+ operator SDValue() const { return Operand; }
- const SDOperand& getSDOperand() const { return Operand; }
+ const SDValue& getSDValue() const { return Operand; }
SDNode *&getVal() { return Operand.Val; }
+ SDNode *const &getVal() const { return Operand.Val; }
- bool operator==(const SDOperand &O) const {
+ bool operator==(const SDValue &O) const {
return Operand == O;
}
- bool operator!=(const SDOperand &O) const {
+ bool operator!=(const SDValue &O) const {
return !(Operand == O);
}
- bool operator<(const SDOperand &O) const {
+ bool operator<(const SDValue &O) const {
return Operand < O;
}
@@ -972,56 +973,56 @@
/// simplify_type specializations - Allow casting operators to work directly on
-/// SDOperands as if they were SDNode*'s.
+/// SDValues as if they were SDNode*'s.
template<> struct simplify_type<SDUse> {
typedef SDNode* SimpleType;
static SimpleType getSimplifiedValue(const SDUse &Val) {
- return static_cast<SimpleType>(Val.getSDOperand().Val);
+ return static_cast<SimpleType>(Val.getVal());
}
};
template<> struct simplify_type<const SDUse> {
typedef SDNode* SimpleType;
static SimpleType getSimplifiedValue(const SDUse &Val) {
- return static_cast<SimpleType>(Val.getSDOperand().Val);
+ return static_cast<SimpleType>(Val.getVal());
}
};
-/// SDOperandPtr - A helper SDOperand pointer class, that can handle
-/// arrays of SDUse and arrays of SDOperand objects. This is required
+/// SDOperandPtr - A helper SDValue pointer class, that can handle
+/// arrays of SDUse and arrays of SDValue objects. This is required
/// in many places inside the SelectionDAG.
///
class SDOperandPtr {
- const SDOperand *ptr; // The pointer to the SDOperand object
- int object_size; // The size of the object containg the SDOperand
+ const SDValue *ptr; // The pointer to the SDValue object
+ int object_size; // The size of the object containg the SDValue
public:
SDOperandPtr() : ptr(0), object_size(0) {}
SDOperandPtr(SDUse * use_ptr) {
- ptr = &use_ptr->getSDOperand();
+ ptr = &use_ptr->getSDValue();
object_size = (int)sizeof(SDUse);
}
- SDOperandPtr(const SDOperand * op_ptr) {
+ SDOperandPtr(const SDValue * op_ptr) {
ptr = op_ptr;
- object_size = (int)sizeof(SDOperand);
+ object_size = (int)sizeof(SDValue);
}
- const SDOperand operator *() { return *ptr; }
- const SDOperand *operator ->() { return ptr; }
+ const SDValue operator *() { return *ptr; }
+ const SDValue *operator ->() { return ptr; }
SDOperandPtr operator ++ () {
- ptr = (SDOperand*)((char *)ptr + object_size);
+ ptr = (SDValue*)((char *)ptr + object_size);
return *this;
}
SDOperandPtr operator ++ (int) {
SDOperandPtr tmp = *this;
- ptr = (SDOperand*)((char *)ptr + object_size);
+ ptr = (SDValue*)((char *)ptr + object_size);
return tmp;
}
- SDOperand operator[] (int idx) const {
- return *(SDOperand*)((char*) ptr + object_size * idx);
+ SDValue operator[] (int idx) const {
+ return *(SDValue*)((char*) ptr + object_size * idx);
}
};
@@ -1215,9 +1216,9 @@
/// ConstantSDNode operand.
uint64_t getConstantOperandVal(unsigned Num) const;
- const SDOperand &getOperand(unsigned Num) const {
+ const SDValue &getOperand(unsigned Num) const {
assert(Num < NumOperands && "Invalid child # of SDNode!");
- return OperandList[Num].getSDOperand();
+ return OperandList[Num].getSDValue();
}
typedef SDUse* op_iterator;
@@ -1276,7 +1277,7 @@
return Ret;
}
- SDNode(unsigned Opc, SDVTList VTs, const SDOperand *Ops, unsigned NumOps)
+ SDNode(unsigned Opc, SDVTList VTs, const SDValue *Ops, unsigned NumOps)
: NodeType(Opc), OperandsNeedDelete(true), SubclassData(0),
NodeId(-1), Uses(NULL) {
NumOperands = NumOps;
@@ -1302,7 +1303,7 @@
for (unsigned i = 0; i != NumOps; ++i) {
OperandList[i] = Ops[i];
OperandList[i].setUser(this);
- Ops[i].getSDOperand().Val->addUse(OperandList[i]);
+ Ops[i].getVal()->addUse(OperandList[i]);
}
ValueList = VTs.VTs;
@@ -1352,36 +1353,36 @@
};
-// Define inline functions from the SDOperand class.
+// Define inline functions from the SDValue class.
-inline unsigned SDOperand::getOpcode() const {
+inline unsigned SDValue::getOpcode() const {
return Val->getOpcode();
}
-inline MVT SDOperand::getValueType() const {
+inline MVT SDValue::getValueType() const {
return Val->getValueType(ResNo);
}
-inline unsigned SDOperand::getNumOperands() const {
+inline unsigned SDValue::getNumOperands() const {
return Val->getNumOperands();
}
-inline const SDOperand &SDOperand::getOperand(unsigned i) const {
+inline const SDValue &SDValue::getOperand(unsigned i) const {
return Val->getOperand(i);
}
-inline uint64_t SDOperand::getConstantOperandVal(unsigned i) const {
+inline uint64_t SDValue::getConstantOperandVal(unsigned i) const {
return Val->getConstantOperandVal(i);
}
-inline bool SDOperand::isTargetOpcode() const {
+inline bool SDValue::isTargetOpcode() const {
return Val->isTargetOpcode();
}
-inline bool SDOperand::isMachineOpcode() const {
+inline bool SDValue::isMachineOpcode() const {
return Val->isMachineOpcode();
}
-inline unsigned SDOperand::getMachineOpcode() const {
+inline unsigned SDValue::getMachineOpcode() const {
return Val->getMachineOpcode();
}
-inline bool SDOperand::use_empty() const {
+inline bool SDValue::use_empty() const {
return !Val->hasAnyUseOfValue(ResNo);
}
-inline bool SDOperand::hasOneUse() const {
+inline bool SDValue::hasOneUse() const {
return Val->hasNUsesOfValue(1, ResNo);
}
@@ -1391,7 +1392,7 @@
virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
SDUse Op;
public:
- UnarySDNode(unsigned Opc, SDVTList VTs, SDOperand X)
+ UnarySDNode(unsigned Opc, SDVTList VTs, SDValue X)
: SDNode(Opc, VTs) {
Op = X;
InitOperands(&Op, 1);
@@ -1404,7 +1405,7 @@
virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
SDUse Ops[2];
public:
- BinarySDNode(unsigned Opc, SDVTList VTs, SDOperand X, SDOperand Y)
+ BinarySDNode(unsigned Opc, SDVTList VTs, SDValue X, SDValue Y)
: SDNode(Opc, VTs) {
Ops[0] = X;
Ops[1] = Y;
@@ -1418,8 +1419,8 @@
virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
SDUse Ops[3];
public:
- TernarySDNode(unsigned Opc, SDVTList VTs, SDOperand X, SDOperand Y,
- SDOperand Z)
+ TernarySDNode(unsigned Opc, SDVTList VTs, SDValue X, SDValue Y,
+ SDValue Z)
: SDNode(Opc, VTs) {
Ops[0] = X;
Ops[1] = Y;
@@ -1440,9 +1441,9 @@
// FIXME: Remove the "noinline" attribute once <rdar://problem/5852746> is
// fixed.
#ifdef __GNUC__
- explicit __attribute__((__noinline__)) HandleSDNode(SDOperand X)
+ explicit __attribute__((__noinline__)) HandleSDNode(SDValue X)
#else
- explicit HandleSDNode(SDOperand X)
+ explicit HandleSDNode(SDValue X)
#endif
: SDNode(ISD::HANDLENODE, getSDVTList(MVT::Other)) {
Op = X;
@@ -1490,8 +1491,8 @@
/// reference performed by operation.
MachineMemOperand getMemOperand() const;
- const SDOperand &getChain() const { return getOperand(0); }
- const SDOperand &getBasePtr() const {
+ const SDValue &getChain() const { return getOperand(0); }
+ const SDValue &getBasePtr() const {
return getOperand(getOpcode() == ISD::STORE ? 2 : 1);
}
@@ -1524,13 +1525,13 @@
// Opc: opcode for atomic
// VTL: value type list
// Chain: memory chain for operaand
- // Ptr: address to update as a SDOperand
+ // Ptr: address to update as a SDValue
// Cmp: compare value
// Swp: swap value
// SrcVal: address to update as a Value (used for MemOperand)
// Align: alignment of memory
- AtomicSDNode(unsigned Opc, SDVTList VTL, SDOperand Chain, SDOperand Ptr,
- SDOperand Cmp, SDOperand Swp, const Value* SrcVal,
+ AtomicSDNode(unsigned Opc, SDVTList VTL, SDValue Chain, SDValue Ptr,
+ SDValue Cmp, SDValue Swp, const Value* SrcVal,
unsigned Align=0)
: MemSDNode(Opc, VTL, Cmp.getValueType(), SrcVal, /*SVOffset=*/0,
Align, /*isVolatile=*/true) {
@@ -1540,8 +1541,8 @@
Ops[3] = Cmp;
InitOperands(Ops, 4);
}
- AtomicSDNode(unsigned Opc, SDVTList VTL, SDOperand Chain, SDOperand Ptr,
- SDOperand Val, const Value* SrcVal, unsigned Align=0)
+ AtomicSDNode(unsigned Opc, SDVTList VTL, SDValue Chain, SDValue Ptr,
+ SDValue Val, const Value* SrcVal, unsigned Align=0)
: MemSDNode(Opc, VTL, Val.getValueType(), SrcVal, /*SVOffset=*/0,
Align, /*isVolatile=*/true) {
Ops[0] = Chain;
@@ -1550,8 +1551,8 @@
InitOperands(Ops, 3);
}
- const SDOperand &getBasePtr() const { return getOperand(1); }
- const SDOperand &getVal() const { return getOperand(2); }
+ const SDValue &getBasePtr() const { return getOperand(1); }
+ const SDValue &getVal() const { return getOperand(2); }
bool isCompareAndSwap() const { return getOpcode() == ISD::ATOMIC_CMP_SWAP; }
@@ -1871,7 +1872,7 @@
virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
protected:
friend class SelectionDAG;
- DbgStopPointSDNode(SDOperand ch, unsigned l, unsigned c,
+ DbgStopPointSDNode(SDValue ch, unsigned l, unsigned c,
const CompileUnitDesc *cu)
: SDNode(ISD::DBG_STOPPOINT, getSDVTList(MVT::Other)),
Line(l), Column(c), CU(cu) {
@@ -1895,7 +1896,7 @@
virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
protected:
friend class SelectionDAG;
- LabelSDNode(unsigned NodeTy, SDOperand ch, unsigned id)
+ LabelSDNode(unsigned NodeTy, SDValue ch, unsigned id)
: SDNode(NodeTy, getSDVTList(MVT::Other)), LabelID(id) {
Chain = ch;
InitOperands(&Chain, 1);
@@ -2083,7 +2084,7 @@
*/
SDUse Ops[4];
public:
- LSBaseSDNode(ISD::NodeType NodeTy, SDOperand *Operands, unsigned numOperands,
+ LSBaseSDNode(ISD::NodeType NodeTy, SDValue *Operands, unsigned numOperands,
SDVTList VTs, ISD::MemIndexedMode AM, MVT VT,
const Value *SV, int SVO, unsigned Align, bool Vol)
: MemSDNode(NodeTy, VTs, VT, SV, SVO, Align, Vol) {
@@ -2096,7 +2097,7 @@
"Only indexed loads and stores have a non-undef offset operand");
}
- const SDOperand &getOffset() const {
+ const SDValue &getOffset() const {
return getOperand(getOpcode() == ISD::LOAD ? 2 : 3);
}
@@ -2125,7 +2126,7 @@
virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
protected:
friend class SelectionDAG;
- LoadSDNode(SDOperand *ChainPtrOff, SDVTList VTs,
+ LoadSDNode(SDValue *ChainPtrOff, SDVTList VTs,
ISD::MemIndexedMode AM, ISD::LoadExtType ETy, MVT LVT,
const Value *SV, int O=0, unsigned Align=0, bool Vol=false)
: LSBaseSDNode(ISD::LOAD, ChainPtrOff, 3,
@@ -2140,8 +2141,8 @@
return ISD::LoadExtType((SubclassData >> 3) & 3);
}
- const SDOperand &getBasePtr() const { return getOperand(1); }
- const SDOperand &getOffset() const { return getOperand(2); }
+ const SDValue &getBasePtr() const { return getOperand(1); }
+ const SDValue &getOffset() const { return getOperand(2); }
static bool classof(const LoadSDNode *) { return true; }
static bool classof(const SDNode *N) {
@@ -2155,7 +2156,7 @@
virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
protected:
friend class SelectionDAG;
- StoreSDNode(SDOperand *ChainValuePtrOff, SDVTList VTs,
+ StoreSDNode(SDValue *ChainValuePtrOff, SDVTList VTs,
ISD::MemIndexedMode AM, bool isTrunc, MVT SVT,
const Value *SV, int O=0, unsigned Align=0, bool Vol=false)
: LSBaseSDNode(ISD::STORE, ChainValuePtrOff, 4,
@@ -2169,9 +2170,9 @@
/// For floats, it is the same as doing an FP_ROUND and storing the result.
bool isTruncatingStore() const { return (SubclassData >> 3) & 1; }
- const SDOperand &getValue() const { return getOperand(1); }
- const SDOperand &getBasePtr() const { return getOperand(2); }
- const SDOperand &getOffset() const { return getOperand(3); }
+ const SDValue &getValue() const { return getOperand(1); }
+ const SDValue &getBasePtr() const { return getOperand(2); }
+ const SDValue &getOffset() const { return getOperand(3); }
static bool classof(const StoreSDNode *) { return true; }
static bool classof(const SDNode *N) {
Modified: llvm/trunk/include/llvm/Target/TargetLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetLowering.h (original)
+++ llvm/trunk/include/llvm/Target/TargetLowering.h Sun Jul 27 16:46:04 2008
@@ -37,7 +37,7 @@
class MachineFrameInfo;
class MachineInstr;
class SDNode;
- class SDOperand;
+ class SDValue;
class SelectionDAG;
class TargetData;
class TargetMachine;
@@ -112,7 +112,7 @@
/// getSetCCResultType - Return the ValueType of the result of setcc
/// operations.
- virtual MVT getSetCCResultType(const SDOperand &) const;
+ virtual MVT getSetCCResultType(const SDValue &) const;
/// getSetCCResultContents - For targets without boolean registers, this flag
/// returns information about the contents of the high-bits in the setcc
@@ -266,7 +266,7 @@
/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
/// are assumed to be legal.
- virtual bool isShuffleMaskLegal(SDOperand Mask, MVT VT) const {
+ virtual bool isShuffleMaskLegal(SDValue Mask, MVT VT) const {
return true;
}
@@ -274,7 +274,7 @@
/// used by Targets can use this to indicate if there is a suitable
/// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
/// pool entry.
- virtual bool isVectorClearMaskLegal(const std::vector<SDOperand> &BVOps,
+ virtual bool isVectorClearMaskLegal(const std::vector<SDValue> &BVOps,
MVT EVT,
SelectionDAG &DAG) const {
return false;
@@ -603,8 +603,8 @@
/// getPreIndexedAddressParts - returns true by value, base pointer and
/// offset pointer and addressing mode by reference if the node's address
/// can be legally represented as pre-indexed load / store address.
- virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
- SDOperand &Offset,
+ virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
+ SDValue &Offset,
ISD::MemIndexedMode &AM,
SelectionDAG &DAG) {
return false;
@@ -614,7 +614,7 @@
/// offset pointer and addressing mode by reference if this node can be
/// combined with a load / store to form a post-indexed load / store.
virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
- SDOperand &Base, SDOperand &Offset,
+ SDValue &Base, SDValue &Offset,
ISD::MemIndexedMode &AM,
SelectionDAG &DAG) {
return false;
@@ -622,7 +622,7 @@
/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
/// jumptable.
- virtual SDOperand getPICJumpTableRelocBase(SDOperand Table,
+ virtual SDValue getPICJumpTableRelocBase(SDValue Table,
SelectionDAG &DAG) const;
//===--------------------------------------------------------------------===//
@@ -630,18 +630,18 @@
//
/// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
- /// SDOperands for returning information from TargetLowering to its clients
+ /// SDValues for returning information from TargetLowering to its clients
/// that want to combine
struct TargetLoweringOpt {
SelectionDAG &DAG;
bool AfterLegalize;
- SDOperand Old;
- SDOperand New;
+ SDValue Old;
+ SDValue New;
explicit TargetLoweringOpt(SelectionDAG &InDAG, bool afterLegalize)
: DAG(InDAG), AfterLegalize(afterLegalize) {}
- bool CombineTo(SDOperand O, SDOperand N) {
+ bool CombineTo(SDValue O, SDValue N) {
Old = O;
New = N;
return true;
@@ -651,7 +651,7 @@
/// specified instruction is a constant integer. If so, check to see if
/// there are any bits set in the constant that are not demanded. If so,
/// shrink the constant and return true.
- bool ShrinkDemandedConstant(SDOperand Op, const APInt &Demanded);
+ bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
};
/// SimplifyDemandedBits - Look at Op. At this point, we know that only the
@@ -662,14 +662,14 @@
/// KnownZero bits for the expression (used to simplify the caller).
/// The KnownZero/One bits may only be accurate for those bits in the
/// DemandedMask.
- bool SimplifyDemandedBits(SDOperand Op, const APInt &DemandedMask,
+ bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
APInt &KnownZero, APInt &KnownOne,
TargetLoweringOpt &TLO, unsigned Depth = 0) const;
/// computeMaskedBitsForTargetNode - Determine which of the bits specified in
/// Mask are known to be either zero or one and return them in the
/// KnownZero/KnownOne bitsets.
- virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
+ virtual void computeMaskedBitsForTargetNode(const SDValue Op,
const APInt &Mask,
APInt &KnownZero,
APInt &KnownOne,
@@ -679,7 +679,7 @@
/// ComputeNumSignBitsForTargetNode - This method can be implemented by
/// targets that want to expose additional information about sign bits to the
/// DAG Combiner.
- virtual unsigned ComputeNumSignBitsForTargetNode(SDOperand Op,
+ virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
unsigned Depth = 0) const;
struct DAGCombinerInfo {
@@ -696,14 +696,14 @@
bool isCalledByLegalizer() const { return CalledByLegalizer; }
void AddToWorklist(SDNode *N);
- SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To);
- SDOperand CombineTo(SDNode *N, SDOperand Res);
- SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1);
+ SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To);
+ SDValue CombineTo(SDNode *N, SDValue Res);
+ SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1);
};
/// SimplifySetCC - Try to simplify a setcc built with the specified operands
- /// and cc. If it is unable to simplify it, return a null SDOperand.
- SDOperand SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1,
+ /// and cc. If it is unable to simplify it, return a null SDValue.
+ SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
ISD::CondCode Cond, bool foldBooleans,
DAGCombinerInfo &DCI) const;
@@ -724,14 +724,14 @@
///
/// The semantics are as follows:
/// Return Value:
- /// SDOperand.Val == 0 - No change was made
- /// SDOperand.Val == N - N was replaced, is dead, and is already handled.
+ /// SDValue.Val == 0 - No change was made
+ /// SDValue.Val == N - N was replaced, is dead, and is already handled.
/// otherwise - N should be replaced by the returned Operand.
///
/// In addition, methods provided by DAGCombinerInfo may be used to perform
/// more complex transformations.
///
- virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
+ virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
//===--------------------------------------------------------------------===//
// TargetLowering Configuration Methods - These methods should be invoked by
@@ -966,14 +966,14 @@
/// lower the arguments for the specified function, into the specified DAG.
virtual void
LowerArguments(Function &F, SelectionDAG &DAG,
- SmallVectorImpl<SDOperand>& ArgValues);
+ SmallVectorImpl<SDValue>& ArgValues);
/// LowerCallTo - This hook lowers an abstract call to a function into an
/// actual call. This returns a pair of operands. The first element is the
/// return value for the function (if RetTy is not VoidTy). The second
/// element is the outgoing token chain.
struct ArgListEntry {
- SDOperand Node;
+ SDValue Node;
const Type* Ty;
bool isSExt : 1;
bool isZExt : 1;
@@ -987,17 +987,17 @@
isSRet(false), isNest(false), isByVal(false), Alignment(0) { }
};
typedef std::vector<ArgListEntry> ArgListTy;
- virtual std::pair<SDOperand, SDOperand>
- LowerCallTo(SDOperand Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
+ virtual std::pair<SDValue, SDValue>
+ LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
bool isVarArg, unsigned CallingConv, bool isTailCall,
- SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
+ SDValue Callee, ArgListTy &Args, SelectionDAG &DAG);
/// EmitTargetCodeForMemcpy - Emit target-specific code that performs a
/// memcpy. This can be used by targets to provide code sequences for cases
/// that don't fit the target's parameters for simple loads/stores and can be
/// more efficient than using a library call. This function can return a null
- /// SDOperand if the target declines to use custom code and a different
+ /// SDValue if the target declines to use custom code and a different
/// lowering strategy should be used.
///
/// If AlwaysInline is true, the size is constant and the target should not
@@ -1006,46 +1006,46 @@
/// expanded in a place where calls are not feasible (e.g. within the prologue
/// for another call). If the target chooses to decline an AlwaysInline
/// request here, legalize will resort to using simple loads and stores.
- virtual SDOperand
+ virtual SDValue
EmitTargetCodeForMemcpy(SelectionDAG &DAG,
- SDOperand Chain,
- SDOperand Op1, SDOperand Op2,
- SDOperand Op3, unsigned Align,
+ SDValue Chain,
+ SDValue Op1, SDValue Op2,
+ SDValue Op3, unsigned Align,
bool AlwaysInline,
const Value *DstSV, uint64_t DstOff,
const Value *SrcSV, uint64_t SrcOff) {
- return SDOperand();
+ return SDValue();
}
/// EmitTargetCodeForMemmove - Emit target-specific code that performs a
/// memmove. This can be used by targets to provide code sequences for cases
/// that don't fit the target's parameters for simple loads/stores and can be
/// more efficient than using a library call. This function can return a null
- /// SDOperand if the target declines to use custom code and a different
+ /// SDValue if the target declines to use custom code and a different
/// lowering strategy should be used.
- virtual SDOperand
+ virtual SDValue
EmitTargetCodeForMemmove(SelectionDAG &DAG,
- SDOperand Chain,
- SDOperand Op1, SDOperand Op2,
- SDOperand Op3, unsigned Align,
+ SDValue Chain,
+ SDValue Op1, SDValue Op2,
+ SDValue Op3, unsigned Align,
const Value *DstSV, uint64_t DstOff,
const Value *SrcSV, uint64_t SrcOff) {
- return SDOperand();
+ return SDValue();
}
/// EmitTargetCodeForMemset - Emit target-specific code that performs a
/// memset. This can be used by targets to provide code sequences for cases
/// that don't fit the target's parameters for simple stores and can be more
/// efficient than using a library call. This function can return a null
- /// SDOperand if the target declines to use custom code and a different
+ /// SDValue if the target declines to use custom code and a different
/// lowering strategy should be used.
- virtual SDOperand
+ virtual SDValue
EmitTargetCodeForMemset(SelectionDAG &DAG,
- SDOperand Chain,
- SDOperand Op1, SDOperand Op2,
- SDOperand Op3, unsigned Align,
+ SDValue Chain,
+ SDValue Op1, SDValue Op2,
+ SDValue Op3, unsigned Align,
const Value *DstSV, uint64_t DstOff) {
- return SDOperand();
+ return SDValue();
}
/// LowerOperation - This callback is invoked for operations that are
@@ -1053,7 +1053,7 @@
/// and whose defined values are all legal.
/// If the target has no operations that require custom lowering, it need not
/// implement this. The default implementation of this aborts.
- virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
+ virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
/// ReplaceNodeResults - This callback is invoked for operations that are
/// unsupported by the target, which are registered to use 'custom' lowering,
@@ -1071,8 +1071,8 @@
/// IsEligibleForTailCallOptimization - Check whether the call is eligible for
/// tail call optimization. Targets which want to do tail call optimization
/// should override this function.
- virtual bool IsEligibleForTailCallOptimization(SDOperand Call,
- SDOperand Ret,
+ virtual bool IsEligibleForTailCallOptimization(SDValue Call,
+ SDValue Ret,
SelectionDAG &DAG) const {
return false;
}
@@ -1081,21 +1081,21 @@
/// preceeds the RET node and whether the return uses the result of the node
/// or is a void return. This function can be used by the target to determine
/// eligiblity of tail call optimization.
- static bool CheckTailCallReturnConstraints(SDOperand Call, SDOperand Ret) {
+ static bool CheckTailCallReturnConstraints(SDValue Call, SDValue Ret) {
unsigned NumOps = Ret.getNumOperands();
if ((NumOps == 1 &&
- (Ret.getOperand(0) == SDOperand(Call.Val,1) ||
- Ret.getOperand(0) == SDOperand(Call.Val,0))) ||
+ (Ret.getOperand(0) == SDValue(Call.Val,1) ||
+ Ret.getOperand(0) == SDValue(Call.Val,0))) ||
(NumOps > 1 &&
- Ret.getOperand(0) == SDOperand(Call.Val,Call.Val->getNumValues()-1) &&
- Ret.getOperand(1) == SDOperand(Call.Val,0)))
+ Ret.getOperand(0) == SDValue(Call.Val,Call.Val->getNumValues()-1) &&
+ Ret.getOperand(1) == SDValue(Call.Val,0)))
return true;
return false;
}
/// GetPossiblePreceedingTailCall - Get preceeding TailCallNodeOpCode node if
/// it exists skip possible ISD:TokenFactor.
- static SDOperand GetPossiblePreceedingTailCall(SDOperand Chain,
+ static SDValue GetPossiblePreceedingTailCall(SDValue Chain,
unsigned TailCallNodeOpCode) {
if (Chain.getOpcode() == TailCallNodeOpCode) {
return Chain;
@@ -1152,9 +1152,9 @@
/// type to use for the specific AsmOperandInfo, setting
/// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand
/// being passed in is available, it can be passed in as Op, otherwise an
- /// empty SDOperand can be passed.
+ /// empty SDValue can be passed.
virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
- SDOperand Op,
+ SDValue Op,
SelectionDAG *DAG = 0) const;
/// getConstraintType - Given a constraint, return the type of constraint it
@@ -1190,8 +1190,8 @@
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
/// vector. If it is invalid, don't add anything to Ops.
- virtual void LowerAsmOperandForConstraint(SDOperand Op, char ConstraintLetter,
- std::vector<SDOperand> &Ops,
+ virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
+ std::vector<SDValue> &Ops,
SelectionDAG &DAG) const;
//===--------------------------------------------------------------------===//
@@ -1245,9 +1245,9 @@
//===--------------------------------------------------------------------===//
// Div utility functions
//
- SDOperand BuildSDIV(SDNode *N, SelectionDAG &DAG,
+ SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG,
std::vector<SDNode*>* Created) const;
- SDOperand BuildUDIV(SDNode *N, SelectionDAG &DAG,
+ SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG,
std::vector<SDNode*>* Created) const;
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sun Jul 27 16:46:04 2008
@@ -70,7 +70,7 @@
/// visit - call the node-specific routine that knows how to fold each
/// particular type of node.
- SDOperand visit(SDNode *N);
+ SDValue visit(SDNode *N);
public:
/// AddToWorkList - Add to the work list making sure it's instance is at the
@@ -87,16 +87,16 @@
WorkList.end());
}
- SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo,
+ SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
bool AddTo = true);
- SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) {
+ SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
return CombineTo(N, &Res, 1, AddTo);
}
- SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1,
+ SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
bool AddTo = true) {
- SDOperand To[] = { Res0, Res1 };
+ SDValue To[] = { Res0, Res1 };
return CombineTo(N, To, 2, AddTo);
}
@@ -105,12 +105,12 @@
/// SimplifyDemandedBits - Check the specified integer node value to see if
/// it can be simplified or if things it uses can be simplified by bit
/// propagation. If so, return true.
- bool SimplifyDemandedBits(SDOperand Op) {
+ bool SimplifyDemandedBits(SDValue Op) {
APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits());
return SimplifyDemandedBits(Op, Demanded);
}
- bool SimplifyDemandedBits(SDOperand Op, const APInt &Demanded);
+ bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
bool CombineToPreIndexedLoadStore(SDNode *N);
bool CombineToPostIndexedLoadStore(SDNode *N);
@@ -119,122 +119,122 @@
/// combine - call the node-specific routine that knows how to fold each
/// particular type of node. If that doesn't do anything, try the
/// target-specific DAG combines.
- SDOperand combine(SDNode *N);
+ SDValue combine(SDNode *N);
// Visitation implementation - Implement dag node combining for different
// node types. The semantics are as follows:
// Return Value:
- // SDOperand.Val == 0 - No change was made
- // SDOperand.Val == N - N was replaced, is dead, and is already handled.
+ // SDValue.Val == 0 - No change was made
+ // SDValue.Val == N - N was replaced, is dead, and is already handled.
// otherwise - N should be replaced by the returned Operand.
//
- SDOperand visitTokenFactor(SDNode *N);
- SDOperand visitMERGE_VALUES(SDNode *N);
- SDOperand visitADD(SDNode *N);
- SDOperand visitSUB(SDNode *N);
- SDOperand visitADDC(SDNode *N);
- SDOperand visitADDE(SDNode *N);
- SDOperand visitMUL(SDNode *N);
- SDOperand visitSDIV(SDNode *N);
- SDOperand visitUDIV(SDNode *N);
- SDOperand visitSREM(SDNode *N);
- SDOperand visitUREM(SDNode *N);
- SDOperand visitMULHU(SDNode *N);
- SDOperand visitMULHS(SDNode *N);
- SDOperand visitSMUL_LOHI(SDNode *N);
- SDOperand visitUMUL_LOHI(SDNode *N);
- SDOperand visitSDIVREM(SDNode *N);
- SDOperand visitUDIVREM(SDNode *N);
- SDOperand visitAND(SDNode *N);
- SDOperand visitOR(SDNode *N);
- SDOperand visitXOR(SDNode *N);
- SDOperand SimplifyVBinOp(SDNode *N);
- SDOperand visitSHL(SDNode *N);
- SDOperand visitSRA(SDNode *N);
- SDOperand visitSRL(SDNode *N);
- SDOperand visitCTLZ(SDNode *N);
- SDOperand visitCTTZ(SDNode *N);
- SDOperand visitCTPOP(SDNode *N);
- SDOperand visitSELECT(SDNode *N);
- SDOperand visitSELECT_CC(SDNode *N);
- SDOperand visitSETCC(SDNode *N);
- SDOperand visitSIGN_EXTEND(SDNode *N);
- SDOperand visitZERO_EXTEND(SDNode *N);
- SDOperand visitANY_EXTEND(SDNode *N);
- SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
- SDOperand visitTRUNCATE(SDNode *N);
- SDOperand visitBIT_CONVERT(SDNode *N);
- SDOperand visitBUILD_PAIR(SDNode *N);
- SDOperand visitFADD(SDNode *N);
- SDOperand visitFSUB(SDNode *N);
- SDOperand visitFMUL(SDNode *N);
- SDOperand visitFDIV(SDNode *N);
- SDOperand visitFREM(SDNode *N);
- SDOperand visitFCOPYSIGN(SDNode *N);
- SDOperand visitSINT_TO_FP(SDNode *N);
- SDOperand visitUINT_TO_FP(SDNode *N);
- SDOperand visitFP_TO_SINT(SDNode *N);
- SDOperand visitFP_TO_UINT(SDNode *N);
- SDOperand visitFP_ROUND(SDNode *N);
- SDOperand visitFP_ROUND_INREG(SDNode *N);
- SDOperand visitFP_EXTEND(SDNode *N);
- SDOperand visitFNEG(SDNode *N);
- SDOperand visitFABS(SDNode *N);
- SDOperand visitBRCOND(SDNode *N);
- SDOperand visitBR_CC(SDNode *N);
- SDOperand visitLOAD(SDNode *N);
- SDOperand visitSTORE(SDNode *N);
- SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
- SDOperand visitEXTRACT_VECTOR_ELT(SDNode *N);
- SDOperand visitBUILD_VECTOR(SDNode *N);
- SDOperand visitCONCAT_VECTORS(SDNode *N);
- SDOperand visitVECTOR_SHUFFLE(SDNode *N);
-
- SDOperand XformToShuffleWithZero(SDNode *N);
- SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
-
- SDOperand visitShiftByConstant(SDNode *N, unsigned Amt);
-
- bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
- SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N);
- SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
- SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
- SDOperand N3, ISD::CondCode CC,
+ SDValue visitTokenFactor(SDNode *N);
+ SDValue visitMERGE_VALUES(SDNode *N);
+ SDValue visitADD(SDNode *N);
+ SDValue visitSUB(SDNode *N);
+ SDValue visitADDC(SDNode *N);
+ SDValue visitADDE(SDNode *N);
+ SDValue visitMUL(SDNode *N);
+ SDValue visitSDIV(SDNode *N);
+ SDValue visitUDIV(SDNode *N);
+ SDValue visitSREM(SDNode *N);
+ SDValue visitUREM(SDNode *N);
+ SDValue visitMULHU(SDNode *N);
+ SDValue visitMULHS(SDNode *N);
+ SDValue visitSMUL_LOHI(SDNode *N);
+ SDValue visitUMUL_LOHI(SDNode *N);
+ SDValue visitSDIVREM(SDNode *N);
+ SDValue visitUDIVREM(SDNode *N);
+ SDValue visitAND(SDNode *N);
+ SDValue visitOR(SDNode *N);
+ SDValue visitXOR(SDNode *N);
+ SDValue SimplifyVBinOp(SDNode *N);
+ SDValue visitSHL(SDNode *N);
+ SDValue visitSRA(SDNode *N);
+ SDValue visitSRL(SDNode *N);
+ SDValue visitCTLZ(SDNode *N);
+ SDValue visitCTTZ(SDNode *N);
+ SDValue visitCTPOP(SDNode *N);
+ SDValue visitSELECT(SDNode *N);
+ SDValue visitSELECT_CC(SDNode *N);
+ SDValue visitSETCC(SDNode *N);
+ SDValue visitSIGN_EXTEND(SDNode *N);
+ SDValue visitZERO_EXTEND(SDNode *N);
+ SDValue visitANY_EXTEND(SDNode *N);
+ SDValue visitSIGN_EXTEND_INREG(SDNode *N);
+ SDValue visitTRUNCATE(SDNode *N);
+ SDValue visitBIT_CONVERT(SDNode *N);
+ SDValue visitBUILD_PAIR(SDNode *N);
+ SDValue visitFADD(SDNode *N);
+ SDValue visitFSUB(SDNode *N);
+ SDValue visitFMUL(SDNode *N);
+ SDValue visitFDIV(SDNode *N);
+ SDValue visitFREM(SDNode *N);
+ SDValue visitFCOPYSIGN(SDNode *N);
+ SDValue visitSINT_TO_FP(SDNode *N);
+ SDValue visitUINT_TO_FP(SDNode *N);
+ SDValue visitFP_TO_SINT(SDNode *N);
+ SDValue visitFP_TO_UINT(SDNode *N);
+ SDValue visitFP_ROUND(SDNode *N);
+ SDValue visitFP_ROUND_INREG(SDNode *N);
+ SDValue visitFP_EXTEND(SDNode *N);
+ SDValue visitFNEG(SDNode *N);
+ SDValue visitFABS(SDNode *N);
+ SDValue visitBRCOND(SDNode *N);
+ SDValue visitBR_CC(SDNode *N);
+ SDValue visitLOAD(SDNode *N);
+ SDValue visitSTORE(SDNode *N);
+ SDValue visitINSERT_VECTOR_ELT(SDNode *N);
+ SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
+ SDValue visitBUILD_VECTOR(SDNode *N);
+ SDValue visitCONCAT_VECTORS(SDNode *N);
+ SDValue visitVECTOR_SHUFFLE(SDNode *N);
+
+ SDValue XformToShuffleWithZero(SDNode *N);
+ SDValue ReassociateOps(unsigned Opc, SDValue LHS, SDValue RHS);
+
+ SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
+
+ bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
+ SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
+ SDValue SimplifySelect(SDValue N0, SDValue N1, SDValue N2);
+ SDValue SimplifySelectCC(SDValue N0, SDValue N1, SDValue N2,
+ SDValue N3, ISD::CondCode CC,
bool NotExtCompare = false);
- SDOperand SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1,
+ SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
ISD::CondCode Cond, bool foldBooleans = true);
- SDOperand SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
+ SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
unsigned HiOp);
- SDOperand CombineConsecutiveLoads(SDNode *N, MVT VT);
- SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT);
- SDOperand BuildSDIV(SDNode *N);
- SDOperand BuildUDIV(SDNode *N);
- SDNode *MatchRotate(SDOperand LHS, SDOperand RHS);
- SDOperand ReduceLoadWidth(SDNode *N);
+ SDValue CombineConsecutiveLoads(SDNode *N, MVT VT);
+ SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT);
+ SDValue BuildSDIV(SDNode *N);
+ SDValue BuildUDIV(SDNode *N);
+ SDNode *MatchRotate(SDValue LHS, SDValue RHS);
+ SDValue ReduceLoadWidth(SDNode *N);
- SDOperand GetDemandedBits(SDOperand V, const APInt &Mask);
+ SDValue GetDemandedBits(SDValue V, const APInt &Mask);
/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
/// looking for aliasing nodes and adding them to the Aliases vector.
- void GatherAllAliases(SDNode *N, SDOperand OriginalChain,
- SmallVector<SDOperand, 8> &Aliases);
+ void GatherAllAliases(SDNode *N, SDValue OriginalChain,
+ SmallVector<SDValue, 8> &Aliases);
/// isAlias - Return true if there is any possibility that the two addresses
/// overlap.
- bool isAlias(SDOperand Ptr1, int64_t Size1,
+ bool isAlias(SDValue Ptr1, int64_t Size1,
const Value *SrcValue1, int SrcValueOffset1,
- SDOperand Ptr2, int64_t Size2,
+ SDValue Ptr2, int64_t Size2,
const Value *SrcValue2, int SrcValueOffset2);
/// FindAliasInfo - Extracts the relevant alias information from the memory
/// node. Returns true if the operand was a load.
bool FindAliasInfo(SDNode *N,
- SDOperand &Ptr, int64_t &Size,
+ SDValue &Ptr, int64_t &Size,
const Value *&SrcValue, int &SrcValueOffset);
/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
/// looking for a better chain (aliasing node.)
- SDOperand FindBetterChain(SDNode *N, SDOperand Chain);
+ SDValue FindBetterChain(SDNode *N, SDValue Chain);
public:
DAGCombiner(SelectionDAG &D, AliasAnalysis &A)
@@ -276,19 +276,19 @@
((DAGCombiner*)DC)->AddToWorkList(N);
}
-SDOperand TargetLowering::DAGCombinerInfo::
-CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
+SDValue TargetLowering::DAGCombinerInfo::
+CombineTo(SDNode *N, const std::vector<SDValue> &To) {
return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size());
}
-SDOperand TargetLowering::DAGCombinerInfo::
-CombineTo(SDNode *N, SDOperand Res) {
+SDValue TargetLowering::DAGCombinerInfo::
+CombineTo(SDNode *N, SDValue Res) {
return ((DAGCombiner*)DC)->CombineTo(N, Res);
}
-SDOperand TargetLowering::DAGCombinerInfo::
-CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
+SDValue TargetLowering::DAGCombinerInfo::
+CombineTo(SDNode *N, SDValue Res0, SDValue Res1) {
return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
}
@@ -300,7 +300,7 @@
/// isNegatibleForFree - Return 1 if we can compute the negated form of the
/// specified expression for the same cost as the expression itself, or 2 if we
/// can compute the negated form more cheaply than the expression itself.
-static char isNegatibleForFree(SDOperand Op, bool AfterLegalize,
+static char isNegatibleForFree(SDValue Op, bool AfterLegalize,
unsigned Depth = 0) {
// No compile time optimizations on this type.
if (Op.getValueType() == MVT::ppcf128)
@@ -356,7 +356,7 @@
/// GetNegatedExpression - If isNegatibleForFree returns true, this function
/// returns the newly negated expression.
-static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG,
+static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
bool AfterLegalize, unsigned Depth = 0) {
// fneg is removable even if it has multiple uses.
if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
@@ -436,8 +436,8 @@
// Also, set the incoming LHS, RHS, and CC references to the appropriate
// nodes based on the type of node we are checking. This simplifies life a
// bit for the callers.
-static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
- SDOperand &CC) {
+static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
+ SDValue &CC) {
if (N.getOpcode() == ISD::SETCC) {
LHS = N.getOperand(0);
RHS = N.getOperand(1);
@@ -460,24 +460,24 @@
// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
// one use. If this is true, it allows the users to invert the operation for
// free when it is profitable to do so.
-static bool isOneUseSetCC(SDOperand N) {
- SDOperand N0, N1, N2;
+static bool isOneUseSetCC(SDValue N) {
+ SDValue N0, N1, N2;
if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
return true;
return false;
}
-SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
+SDValue DAGCombiner::ReassociateOps(unsigned Opc, SDValue N0, SDValue N1){
MVT VT = N0.getValueType();
// reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
// reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
if (isa<ConstantSDNode>(N1)) {
- SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
+ SDValue OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
AddToWorkList(OpNode.Val);
return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
} else if (N0.hasOneUse()) {
- SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
+ SDValue OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
AddToWorkList(OpNode.Val);
return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
}
@@ -486,20 +486,20 @@
// reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
if (isa<ConstantSDNode>(N0)) {
- SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
+ SDValue OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
AddToWorkList(OpNode.Val);
return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
} else if (N1.hasOneUse()) {
- SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
+ SDValue OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
AddToWorkList(OpNode.Val);
return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
}
}
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo,
- bool AddTo) {
+SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
+ bool AddTo) {
assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
++NodesCombined;
DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG));
@@ -522,13 +522,13 @@
// Finally, since the node is now dead, remove it from the graph.
DAG.DeleteNode(N);
- return SDOperand(N, 0);
+ return SDValue(N, 0);
}
/// SimplifyDemandedBits - Check the specified integer node value to see if
/// it can be simplified or if things it uses can be simplified by bit
/// propagation. If so, return true.
-bool DAGCombiner::SimplifyDemandedBits(SDOperand Op, const APInt &Demanded) {
+bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
TargetLowering::TargetLoweringOpt TLO(DAG, AfterLegalize);
APInt KnownZero, KnownOne;
if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
@@ -590,7 +590,7 @@
// The root of the dag may dangle to deleted nodes until the dag combiner is
// done. Set it to null to avoid confusion.
- DAG.setRoot(SDOperand());
+ DAG.setRoot(SDValue());
// while the worklist isn't empty, inspect the node on the end of it and
// try and combine it.
@@ -609,7 +609,7 @@
continue;
}
- SDOperand RV = combine(N);
+ SDValue RV = combine(N);
if (RV.Val == 0)
continue;
@@ -636,7 +636,7 @@
else {
assert(N->getValueType(0) == RV.getValueType() &&
N->getNumValues() == 1 && "Type mismatch");
- SDOperand OpV = RV;
+ SDValue OpV = RV;
DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes);
}
@@ -662,7 +662,7 @@
DAG.setRoot(Dummy.getValue());
}
-SDOperand DAGCombiner::visit(SDNode *N) {
+SDValue DAGCombiner::visit(SDNode *N) {
switch(N->getOpcode()) {
default: break;
case ISD::TokenFactor: return visitTokenFactor(N);
@@ -726,12 +726,12 @@
case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
}
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::combine(SDNode *N) {
+SDValue DAGCombiner::combine(SDNode *N) {
- SDOperand RV = visit(N);
+ SDValue RV = visit(N);
// If nothing happened, try a target-specific DAG combine.
if (RV.Val == 0) {
@@ -754,15 +754,15 @@
if (RV.Val == 0 &&
SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
N->getNumValues() == 1) {
- SDOperand N0 = N->getOperand(0);
- SDOperand N1 = N->getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Constant operands are canonicalized to RHS.
if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
- SDOperand Ops[] = { N1, N0 };
+ SDValue Ops[] = { N1, N0 };
SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(),
Ops, 2);
if (CSENode)
- return SDOperand(CSENode, 0);
+ return SDValue(CSENode, 0);
}
}
@@ -771,7 +771,7 @@
/// getInputChainForNode - Given a node, return its input chain if it has one,
/// otherwise return a null sd operand.
-static SDOperand getInputChainForNode(SDNode *N) {
+static SDValue getInputChainForNode(SDNode *N) {
if (unsigned NumOps = N->getNumOperands()) {
if (N->getOperand(0).getValueType() == MVT::Other)
return N->getOperand(0);
@@ -781,10 +781,10 @@
if (N->getOperand(i).getValueType() == MVT::Other)
return N->getOperand(i);
}
- return SDOperand(0, 0);
+ return SDValue(0, 0);
}
-SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
+SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
// If N has two operands, where one has an input chain equal to the other,
// the 'other' chain is redundant.
if (N->getNumOperands() == 2) {
@@ -795,7 +795,7 @@
}
SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
- SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor.
+ SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
SmallPtrSet<SDNode*, 16> SeenOps;
bool Changed = false; // If we should replace this token factor.
@@ -809,7 +809,7 @@
// Check each of the operands.
for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
- SDOperand Op = TF->getOperand(i);
+ SDValue Op = TF->getOperand(i);
switch (Op.getOpcode()) {
case ISD::EntryToken:
@@ -841,7 +841,7 @@
}
}
- SDOperand Result;
+ SDValue Result;
// If we've change things around then replace token factor.
if (Changed) {
@@ -861,22 +861,22 @@
}
/// MERGE_VALUES can always be eliminated.
-SDOperand DAGCombiner::visitMERGE_VALUES(SDNode *N) {
+SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
WorkListRemover DeadNodes(*this);
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
- DAG.ReplaceAllUsesOfValueWith(SDOperand(N, i), N->getOperand(i),
+ DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i),
&DeadNodes);
removeFromWorkList(N);
DAG.DeleteNode(N);
- return SDOperand(N, 0); // Return N so it doesn't get rechecked!
+ return SDValue(N, 0); // Return N so it doesn't get rechecked!
}
static
-SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) {
+SDValue combineShlAddConstant(SDValue N0, SDValue N1, SelectionDAG &DAG) {
MVT VT = N0.getValueType();
- SDOperand N00 = N0.getOperand(0);
- SDOperand N01 = N0.getOperand(1);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() &&
isa<ConstantSDNode>(N00.getOperand(1))) {
@@ -885,22 +885,22 @@
DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01));
return DAG.getNode(ISD::ADD, VT, N0, N1);
}
- return SDOperand();
+ return SDValue();
}
static
-SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp,
- SelectionDAG &DAG) {
+SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
+ SelectionDAG &DAG) {
MVT VT = N->getValueType(0);
unsigned Opc = N->getOpcode();
bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
- SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
- SDOperand RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
+ SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
+ SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
ISD::CondCode CC = ISD::SETCC_INVALID;
if (isSlctCC)
CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
else {
- SDOperand CCOp = Slct.getOperand(0);
+ SDValue CCOp = Slct.getOperand(0);
if (CCOp.getOpcode() == ISD::SETCC)
CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
}
@@ -916,7 +916,7 @@
RHS.getOpcode() == ISD::Constant &&
cast<ConstantSDNode>(RHS)->isNullValue()) {
std::swap(LHS, RHS);
- SDOperand Op0 = Slct.getOperand(0);
+ SDValue Op0 = Slct.getOperand(0);
bool isInt = (isSlctCC ? Op0.getValueType() :
Op0.getOperand(0).getValueType()).isInteger();
CC = ISD::getSetCCInverse(CC, isInt);
@@ -925,29 +925,29 @@
}
if (DoXform) {
- SDOperand Result = DAG.getNode(Opc, VT, OtherOp, RHS);
+ SDValue Result = DAG.getNode(Opc, VT, OtherOp, RHS);
if (isSlctCC)
return DAG.getSelectCC(OtherOp, Result,
Slct.getOperand(0), Slct.getOperand(1), CC);
- SDOperand CCOp = Slct.getOperand(0);
+ SDValue CCOp = Slct.getOperand(0);
if (InvCC)
CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0),
CCOp.getOperand(1), CC);
return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result);
}
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitADD(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
- SDOperand N1 = N->getOperand(1);
+SDValue DAGCombiner::visitADD(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
MVT VT = N0.getValueType();
// fold vector ops
if (VT.isVector()) {
- SDOperand FoldedVOp = SimplifyVBinOp(N);
+ SDValue FoldedVOp = SimplifyVBinOp(N);
if (FoldedVOp.Val) return FoldedVOp;
}
@@ -973,7 +973,7 @@
N0C->getAPIntValue(), VT),
N0.getOperand(1));
// reassociate add
- SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1);
+ SDValue RADD = ReassociateOps(ISD::ADD, N0, N1);
if (RADD.Val != 0)
return RADD;
// fold ((0-A) + B) -> B-A
@@ -988,8 +988,8 @@
if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
return N1.getOperand(0);
- if (!VT.isVector() && SimplifyDemandedBits(SDOperand(N, 0)))
- return SDOperand(N, 0);
+ if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
+ return SDValue(N, 0);
// fold (a+b) -> (a|b) iff a and b share no bits.
if (VT.isInteger() && !VT.isVector()) {
@@ -1010,30 +1010,30 @@
// fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) {
- SDOperand Result = combineShlAddConstant(N0, N1, DAG);
+ SDValue Result = combineShlAddConstant(N0, N1, DAG);
if (Result.Val) return Result;
}
if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) {
- SDOperand Result = combineShlAddConstant(N1, N0, DAG);
+ SDValue Result = combineShlAddConstant(N1, N0, DAG);
if (Result.Val) return Result;
}
// fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) {
- SDOperand Result = combineSelectAndUse(N, N0, N1, DAG);
+ SDValue Result = combineSelectAndUse(N, N0, N1, DAG);
if (Result.Val) return Result;
}
if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) {
- SDOperand Result = combineSelectAndUse(N, N1, N0, DAG);
+ SDValue Result = combineSelectAndUse(N, N1, N0, DAG);
if (Result.Val) return Result;
}
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitADDC(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
- SDOperand N1 = N->getOperand(1);
+SDValue DAGCombiner::visitADDC(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
MVT VT = N0.getValueType();
@@ -1067,13 +1067,13 @@
DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
}
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitADDE(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
- SDOperand N1 = N->getOperand(1);
- SDOperand CarryIn = N->getOperand(2);
+SDValue DAGCombiner::visitADDE(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue CarryIn = N->getOperand(2);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
//MVT VT = N0.getValueType();
@@ -1086,21 +1086,21 @@
if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
return DAG.getNode(ISD::ADDC, N->getVTList(), N1, N0);
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitSUB(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
- SDOperand N1 = N->getOperand(1);
+SDValue DAGCombiner::visitSUB(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
MVT VT = N0.getValueType();
// fold vector ops
if (VT.isVector()) {
- SDOperand FoldedVOp = SimplifyVBinOp(N);
+ SDValue FoldedVOp = SimplifyVBinOp(N);
if (FoldedVOp.Val) return FoldedVOp;
}
@@ -1122,7 +1122,7 @@
return N0.getOperand(0);
// fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) {
- SDOperand Result = combineSelectAndUse(N, N1, N0, DAG);
+ SDValue Result = combineSelectAndUse(N, N1, N0, DAG);
if (Result.Val) return Result;
}
// If either operand of a sub is undef, the result is undef
@@ -1131,19 +1131,19 @@
if (N1.getOpcode() == ISD::UNDEF)
return N1;
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitMUL(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
- SDOperand N1 = N->getOperand(1);
+SDValue DAGCombiner::visitMUL(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
MVT VT = N0.getValueType();
// fold vector ops
if (VT.isVector()) {
- SDOperand FoldedVOp = SimplifyVBinOp(N);
+ SDValue FoldedVOp = SimplifyVBinOp(N);
if (FoldedVOp.Val) return FoldedVOp;
}
@@ -1180,7 +1180,7 @@
// (mul (shl X, c1), c2) -> (mul X, c2 << c1)
if (N1C && N0.getOpcode() == ISD::SHL &&
isa<ConstantSDNode>(N0.getOperand(1))) {
- SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
+ SDValue C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
AddToWorkList(C3.Val);
return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
}
@@ -1188,7 +1188,7 @@
// Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
// use.
{
- SDOperand Sh(0,0), Y(0,0);
+ SDValue Sh(0,0), Y(0,0);
// Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
N0.Val->hasOneUse()) {
@@ -1198,7 +1198,7 @@
Sh = N1; Y = N0;
}
if (Sh.Val) {
- SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
+ SDValue Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
}
}
@@ -1211,23 +1211,23 @@
}
// reassociate mul
- SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
+ SDValue RMUL = ReassociateOps(ISD::MUL, N0, N1);
if (RMUL.Val != 0)
return RMUL;
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitSDIV(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
- SDOperand N1 = N->getOperand(1);
+SDValue DAGCombiner::visitSDIV(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
MVT VT = N->getValueType(0);
// fold vector ops
if (VT.isVector()) {
- SDOperand FoldedVOp = SimplifyVBinOp(N);
+ SDValue FoldedVOp = SimplifyVBinOp(N);
if (FoldedVOp.Val) return FoldedVOp;
}
@@ -1253,23 +1253,23 @@
// If dividing by powers of two is cheap, then don't perform the following
// fold.
if (TLI.isPow2DivCheap())
- return SDOperand();
+ return SDValue();
int64_t pow2 = N1C->getSignExtended();
int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
unsigned lg2 = Log2_64(abs2);
// Splat the sign bit into the register
- SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
+ SDValue SGN = DAG.getNode(ISD::SRA, VT, N0,
DAG.getConstant(VT.getSizeInBits()-1,
TLI.getShiftAmountTy()));
AddToWorkList(SGN.Val);
// Add (N0 < 0) ? abs2 - 1 : 0;
- SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
+ SDValue SRL = DAG.getNode(ISD::SRL, VT, SGN,
DAG.getConstant(VT.getSizeInBits()-lg2,
TLI.getShiftAmountTy()));
- SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
+ SDValue ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
AddToWorkList(SRL.Val);
AddToWorkList(ADD.Val); // Divide by pow2
- SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD,
+ SDValue SRA = DAG.getNode(ISD::SRA, VT, ADD,
DAG.getConstant(lg2, TLI.getShiftAmountTy()));
// If we're dividing by a positive value, we're done. Otherwise, we must
// negate the result.
@@ -1282,7 +1282,7 @@
// alternate sequence.
if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
!TLI.isIntDivCheap()) {
- SDOperand Op = BuildSDIV(N);
+ SDValue Op = BuildSDIV(N);
if (Op.Val) return Op;
}
@@ -1293,19 +1293,19 @@
if (N1.getOpcode() == ISD::UNDEF)
return N1;
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitUDIV(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
- SDOperand N1 = N->getOperand(1);
+SDValue DAGCombiner::visitUDIV(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
MVT VT = N->getValueType(0);
// fold vector ops
if (VT.isVector()) {
- SDOperand FoldedVOp = SimplifyVBinOp(N);
+ SDValue FoldedVOp = SimplifyVBinOp(N);
if (FoldedVOp.Val) return FoldedVOp;
}
@@ -1322,7 +1322,7 @@
if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
if (SHC->getAPIntValue().isPowerOf2()) {
MVT ADDVT = N1.getOperand(1).getValueType();
- SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
+ SDValue Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
DAG.getConstant(SHC->getAPIntValue()
.logBase2(),
ADDVT));
@@ -1333,7 +1333,7 @@
}
// fold (udiv x, c) -> alternate
if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
- SDOperand Op = BuildUDIV(N);
+ SDValue Op = BuildUDIV(N);
if (Op.Val) return Op;
}
@@ -1344,12 +1344,12 @@
if (N1.getOpcode() == ISD::UNDEF)
return N1;
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitSREM(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
- SDOperand N1 = N->getOperand(1);
+SDValue DAGCombiner::visitSREM(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
MVT VT = N->getValueType(0);
@@ -1367,12 +1367,12 @@
// If X/C can be simplified by the division-by-constant logic, lower
// X%C to the equivalent of X-X/C*C.
if (N1C && !N1C->isNullValue()) {
- SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1);
+ SDValue Div = DAG.getNode(ISD::SDIV, VT, N0, N1);
AddToWorkList(Div.Val);
- SDOperand OptimizedDiv = combine(Div.Val);
+ SDValue OptimizedDiv = combine(Div.Val);
if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) {
- SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1);
- SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
+ SDValue Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1);
+ SDValue Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
AddToWorkList(Mul.Val);
return Sub;
}
@@ -1385,12 +1385,12 @@
if (N1.getOpcode() == ISD::UNDEF)
return N1;
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitUREM(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
- SDOperand N1 = N->getOperand(1);
+SDValue DAGCombiner::visitUREM(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
MVT VT = N->getValueType(0);
@@ -1406,7 +1406,7 @@
if (N1.getOpcode() == ISD::SHL) {
if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
if (SHC->getAPIntValue().isPowerOf2()) {
- SDOperand Add =
+ SDValue Add =
DAG.getNode(ISD::ADD, VT, N1,
DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
VT));
@@ -1419,11 +1419,11 @@
// If X/C can be simplified by the division-by-constant logic, lower
// X%C to the equivalent of X-X/C*C.
if (N1C && !N1C->isNullValue()) {
- SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1);
- SDOperand OptimizedDiv = combine(Div.Val);
+ SDValue Div = DAG.getNode(ISD::UDIV, VT, N0, N1);
+ SDValue OptimizedDiv = combine(Div.Val);
if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) {
- SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1);
- SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
+ SDValue Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1);
+ SDValue Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
AddToWorkList(Mul.Val);
return Sub;
}
@@ -1436,12 +1436,12 @@
if (N1.getOpcode() == ISD::UNDEF)
return N1;
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitMULHS(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
- SDOperand N1 = N->getOperand(1);
+SDValue DAGCombiner::visitMULHS(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
MVT VT = N->getValueType(0);
@@ -1457,12 +1457,12 @@
if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
return DAG.getConstant(0, VT);
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitMULHU(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
- SDOperand N1 = N->getOperand(1);
+SDValue DAGCombiner::visitMULHU(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
MVT VT = N->getValueType(0);
@@ -1476,21 +1476,21 @@
if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
return DAG.getConstant(0, VT);
- return SDOperand();
+ return SDValue();
}
/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
/// compute two values. LoOp and HiOp give the opcodes for the two computations
/// that are being performed. Return true if a simplification was made.
///
-SDOperand DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
- unsigned HiOp) {
+SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
+ unsigned HiOp) {
// If the high half is not needed, just compute the low half.
bool HiExists = N->hasAnyUseOfValue(1);
if (!HiExists &&
(!AfterLegalize ||
TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
- SDOperand Res = DAG.getNode(LoOp, N->getValueType(0), N->op_begin(),
+ SDValue Res = DAG.getNode(LoOp, N->getValueType(0), N->op_begin(),
N->getNumOperands());
return CombineTo(N, Res, Res);
}
@@ -1500,21 +1500,21 @@
if (!LoExists &&
(!AfterLegalize ||
TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
- SDOperand Res = DAG.getNode(HiOp, N->getValueType(1), N->op_begin(),
+ SDValue Res = DAG.getNode(HiOp, N->getValueType(1), N->op_begin(),
N->getNumOperands());
return CombineTo(N, Res, Res);
}
// If both halves are used, return as it is.
if (LoExists && HiExists)
- return SDOperand();
+ return SDValue();
// If the two computed results can be simplified separately, separate them.
if (LoExists) {
- SDOperand Lo = DAG.getNode(LoOp, N->getValueType(0),
+ SDValue Lo = DAG.getNode(LoOp, N->getValueType(0),
N->op_begin(), N->getNumOperands());
AddToWorkList(Lo.Val);
- SDOperand LoOpt = combine(Lo.Val);
+ SDValue LoOpt = combine(Lo.Val);
if (LoOpt.Val && LoOpt.Val != Lo.Val &&
(!AfterLegalize ||
TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
@@ -1522,50 +1522,50 @@
}
if (HiExists) {
- SDOperand Hi = DAG.getNode(HiOp, N->getValueType(1),
+ SDValue Hi = DAG.getNode(HiOp, N->getValueType(1),
N->op_begin(), N->getNumOperands());
AddToWorkList(Hi.Val);
- SDOperand HiOpt = combine(Hi.Val);
+ SDValue HiOpt = combine(Hi.Val);
if (HiOpt.Val && HiOpt != Hi &&
(!AfterLegalize ||
TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
return CombineTo(N, HiOpt, HiOpt);
}
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitSMUL_LOHI(SDNode *N) {
- SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
+SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
+ SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
if (Res.Val) return Res;
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitUMUL_LOHI(SDNode *N) {
- SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
+SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
+ SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
if (Res.Val) return Res;
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitSDIVREM(SDNode *N) {
- SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
+SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
+ SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
if (Res.Val) return Res;
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitUDIVREM(SDNode *N) {
- SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
+SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
+ SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
if (Res.Val) return Res;
- return SDOperand();
+ return SDValue();
}
/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
/// two operands of the same opcode, try to simplify it.
-SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
- SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1);
+SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
+ SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
MVT VT = N0.getValueType();
assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
@@ -1577,7 +1577,7 @@
if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
- SDOperand ORNode = DAG.getNode(N->getOpcode(),
+ SDValue ORNode = DAG.getNode(N->getOpcode(),
N0.getOperand(0).getValueType(),
N0.getOperand(0), N1.getOperand(0));
AddToWorkList(ORNode.Val);
@@ -1591,20 +1591,20 @@
if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
N0.getOperand(1) == N1.getOperand(1)) {
- SDOperand ORNode = DAG.getNode(N->getOpcode(),
+ SDValue ORNode = DAG.getNode(N->getOpcode(),
N0.getOperand(0).getValueType(),
N0.getOperand(0), N1.getOperand(0));
AddToWorkList(ORNode.Val);
return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
}
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitAND(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
- SDOperand N1 = N->getOperand(1);
- SDOperand LL, LR, RL, RR, CC0, CC1;
+SDValue DAGCombiner::visitAND(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue LL, LR, RL, RR, CC0, CC1;
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
MVT VT = N1.getValueType();
@@ -1612,7 +1612,7 @@
// fold vector ops
if (VT.isVector()) {
- SDOperand FoldedVOp = SimplifyVBinOp(N);
+ SDValue FoldedVOp = SimplifyVBinOp(N);
if (FoldedVOp.Val) return FoldedVOp;
}
@@ -1629,11 +1629,11 @@
if (N1C && N1C->isAllOnesValue())
return N0;
// if (and x, c) is known to be zero, return 0
- if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0),
+ if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
APInt::getAllOnesValue(BitWidth)))
return DAG.getConstant(0, VT);
// reassociate and
- SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
+ SDValue RAND = ReassociateOps(ISD::AND, N0, N1);
if (RAND.Val != 0)
return RAND;
// fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
@@ -1643,11 +1643,11 @@
return N1;
// fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
- SDOperand N0Op0 = N0.getOperand(0);
+ SDValue N0Op0 = N0.getOperand(0);
APInt Mask = ~N1C->getAPIntValue();
Mask.trunc(N0Op0.getValueSizeInBits());
if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
- SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
+ SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
N0Op0);
// Replace uses of the AND with uses of the Zero extend node.
@@ -1657,7 +1657,7 @@
// zero_extend, to avoid duplicating things. This will later cause this
// AND to be folded.
CombineTo(N0.Val, Zext);
- return SDOperand(N, 0); // Return N so it doesn't get rechecked!
+ return SDValue(N, 0); // Return N so it doesn't get rechecked!
}
}
// fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
@@ -1669,19 +1669,19 @@
LL.getValueType().isInteger()) {
// fold (X == 0) & (Y == 0) -> (X|Y == 0)
if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
- SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
+ SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
AddToWorkList(ORNode.Val);
return DAG.getSetCC(VT, ORNode, LR, Op1);
}
// fold (X == -1) & (Y == -1) -> (X&Y == -1)
if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
- SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
+ SDValue ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
AddToWorkList(ANDNode.Val);
return DAG.getSetCC(VT, ANDNode, LR, Op1);
}
// fold (X > -1) & (Y > -1) -> (X|Y > -1)
if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
- SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
+ SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
AddToWorkList(ORNode.Val);
return DAG.getSetCC(VT, ORNode, LR, Op1);
}
@@ -1701,15 +1701,15 @@
// Simplify: and (op x...), (op y...) -> (op (and x, y))
if (N0.getOpcode() == N1.getOpcode()) {
- SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
+ SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
if (Tmp.Val) return Tmp;
}
// fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
// fold (and (sra)) -> (and (srl)) when possible.
if (!VT.isVector() &&
- SimplifyDemandedBits(SDOperand(N, 0)))
- return SDOperand(N, 0);
+ SimplifyDemandedBits(SDValue(N, 0)))
+ return SDValue(N, 0);
// fold (zext_inreg (extload x)) -> (zextload x)
if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
@@ -1721,14 +1721,14 @@
BitWidth - EVT.getSizeInBits())) &&
((!AfterLegalize && !LN0->isVolatile()) ||
TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
- SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
+ SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
LN0->getSrcValueOffset(), EVT,
LN0->isVolatile(),
LN0->getAlignment());
AddToWorkList(N);
CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
- return SDOperand(N, 0); // Return N so it doesn't get rechecked!
+ return SDValue(N, 0); // Return N so it doesn't get rechecked!
}
}
// fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
@@ -1743,14 +1743,14 @@
BitWidth - EVT.getSizeInBits())) &&
((!AfterLegalize && !LN0->isVolatile()) ||
TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
- SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
+ SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
LN0->getSrcValueOffset(), EVT,
LN0->isVolatile(),
LN0->getAlignment());
AddToWorkList(N);
CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
- return SDOperand(N, 0); // Return N so it doesn't get rechecked!
+ return SDValue(N, 0); // Return N so it doesn't get rechecked!
}
}
@@ -1780,38 +1780,38 @@
unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8;
unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
unsigned Alignment = LN0->getAlignment();
- SDOperand NewPtr = LN0->getBasePtr();
+ SDValue NewPtr = LN0->getBasePtr();
if (TLI.isBigEndian()) {
NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
DAG.getConstant(PtrOff, PtrType));
Alignment = MinAlign(Alignment, PtrOff);
}
AddToWorkList(NewPtr.Val);
- SDOperand Load =
+ SDValue Load =
DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr,
LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT,
LN0->isVolatile(), Alignment);
AddToWorkList(N);
CombineTo(N0.Val, Load, Load.getValue(1));
- return SDOperand(N, 0); // Return N so it doesn't get rechecked!
+ return SDValue(N, 0); // Return N so it doesn't get rechecked!
}
}
}
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitOR(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
- SDOperand N1 = N->getOperand(1);
- SDOperand LL, LR, RL, RR, CC0, CC1;
+SDValue DAGCombiner::visitOR(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue LL, LR, RL, RR, CC0, CC1;
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
MVT VT = N1.getValueType();
// fold vector ops
if (VT.isVector()) {
- SDOperand FoldedVOp = SimplifyVBinOp(N);
+ SDValue FoldedVOp = SimplifyVBinOp(N);
if (FoldedVOp.Val) return FoldedVOp;
}
@@ -1834,7 +1834,7 @@
if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
return N1;
// reassociate or
- SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
+ SDValue ROR = ReassociateOps(ISD::OR, N0, N1);
if (ROR.Val != 0)
return ROR;
// Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
@@ -1857,7 +1857,7 @@
// fold (X < 0) | (Y < 0) -> (X|Y < 0)
if (cast<ConstantSDNode>(LR)->isNullValue() &&
(Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
- SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
+ SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
AddToWorkList(ORNode.Val);
return DAG.getSetCC(VT, ORNode, LR, Op1);
}
@@ -1865,7 +1865,7 @@
// fold (X > -1) | (Y > -1) -> (X&Y > -1)
if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
(Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
- SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
+ SDValue ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
AddToWorkList(ANDNode.Val);
return DAG.getSetCC(VT, ANDNode, LR, Op1);
}
@@ -1885,7 +1885,7 @@
// Simplify: or (op x...), (op y...) -> (op (or x, y))
if (N0.getOpcode() == N1.getOpcode()) {
- SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
+ SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
if (Tmp.Val) return Tmp;
}
@@ -1905,7 +1905,7 @@
if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
- SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0));
+ SDValue X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0));
return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT));
}
}
@@ -1913,14 +1913,14 @@
// See if this is some rotate idiom.
if (SDNode *Rot = MatchRotate(N0, N1))
- return SDOperand(Rot, 0);
+ return SDValue(Rot, 0);
- return SDOperand();
+ return SDValue();
}
/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
-static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) {
+static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
if (Op.getOpcode() == ISD::AND) {
if (isa<ConstantSDNode>(Op.getOperand(1))) {
Mask = Op.getOperand(1);
@@ -1941,7 +1941,7 @@
// MatchRotate - Handle an 'or' of two operands. If this is one of the many
// idioms for rotate, and if the target supports rotation instructions, generate
// a rot[lr].
-SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) {
+SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS) {
// Must be a legal type. Expanded 'n promoted things won't work with rotates.
MVT VT = LHS.getValueType();
if (!TLI.isTypeLegal(VT)) return 0;
@@ -1952,13 +1952,13 @@
if (!HasROTL && !HasROTR) return 0;
// Match "(X shl/srl V1) & V2" where V2 may not be present.
- SDOperand LHSShift; // The shift.
- SDOperand LHSMask; // AND value if any.
+ SDValue LHSShift; // The shift.
+ SDValue LHSMask; // AND value if any.
if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
return 0; // Not part of a rotate.
- SDOperand RHSShift; // The shift.
- SDOperand RHSMask; // AND value if any.
+ SDValue RHSShift; // The shift.
+ SDValue RHSMask; // AND value if any.
if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
return 0; // Not part of a rotate.
@@ -1976,9 +1976,9 @@
}
unsigned OpSizeInBits = VT.getSizeInBits();
- SDOperand LHSShiftArg = LHSShift.getOperand(0);
- SDOperand LHSShiftAmt = LHSShift.getOperand(1);
- SDOperand RHSShiftAmt = RHSShift.getOperand(1);
+ SDValue LHSShiftArg = LHSShift.getOperand(0);
+ SDValue LHSShiftAmt = LHSShift.getOperand(1);
+ SDValue RHSShiftAmt = RHSShift.getOperand(1);
// fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
// fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
@@ -1989,7 +1989,7 @@
if ((LShVal + RShVal) != OpSizeInBits)
return 0;
- SDOperand Rot;
+ SDValue Rot;
if (HasROTL)
Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt);
else
@@ -2056,8 +2056,8 @@
(RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
|| RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
|| RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) {
- SDOperand LExtOp0 = LHSShiftAmt.getOperand(0);
- SDOperand RExtOp0 = RHSShiftAmt.getOperand(0);
+ SDValue LExtOp0 = LHSShiftAmt.getOperand(0);
+ SDValue RExtOp0 = RHSShiftAmt.getOperand(0);
if (RExtOp0.getOpcode() == ISD::SUB &&
RExtOp0.getOperand(1) == LExtOp0) {
// fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
@@ -2093,17 +2093,17 @@
}
-SDOperand DAGCombiner::visitXOR(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
- SDOperand N1 = N->getOperand(1);
- SDOperand LHS, RHS, CC;
+SDValue DAGCombiner::visitXOR(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue LHS, RHS, CC;
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
MVT VT = N0.getValueType();
// fold vector ops
if (VT.isVector()) {
- SDOperand FoldedVOp = SimplifyVBinOp(N);
+ SDValue FoldedVOp = SimplifyVBinOp(N);
if (FoldedVOp.Val) return FoldedVOp;
}
@@ -2125,7 +2125,7 @@
if (N1C && N1C->isNullValue())
return N0;
// reassociate xor
- SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1);
+ SDValue RXOR = ReassociateOps(ISD::XOR, N0, N1);
if (RXOR.Val != 0)
return RXOR;
// fold !(x cc y) -> (x !cc y)
@@ -2143,7 +2143,7 @@
// fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
N0.Val->hasOneUse() && isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
- SDOperand V = N0.getOperand(0);
+ SDValue V = N0.getOperand(0);
V = DAG.getNode(ISD::XOR, V.getValueType(), V,
DAG.getConstant(1, V.getValueType()));
AddToWorkList(V.Val);
@@ -2153,7 +2153,7 @@
// fold !(x or y) -> (!x and !y) iff x or y are setcc
if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
(N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
- SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
+ SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
@@ -2165,7 +2165,7 @@
// fold !(x or y) -> (!x and !y) iff x or y are constants
if (N1C && N1C->isAllOnesValue() &&
(N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
- SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
+ SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
@@ -2193,31 +2193,31 @@
return DAG.getConstant(0, VT);
} else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
// Produce a vector of zeros.
- SDOperand El = DAG.getConstant(0, VT.getVectorElementType());
- std::vector<SDOperand> Ops(VT.getVectorNumElements(), El);
+ SDValue El = DAG.getConstant(0, VT.getVectorElementType());
+ std::vector<SDValue> Ops(VT.getVectorNumElements(), El);
return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
}
}
// Simplify: xor (op x...), (op y...) -> (op (xor x, y))
if (N0.getOpcode() == N1.getOpcode()) {
- SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
+ SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
if (Tmp.Val) return Tmp;
}
// Simplify the expression using non-local knowledge.
if (!VT.isVector() &&
- SimplifyDemandedBits(SDOperand(N, 0)))
- return SDOperand(N, 0);
+ SimplifyDemandedBits(SDValue(N, 0)))
+ return SDValue(N, 0);
- return SDOperand();
+ return SDValue();
}
/// visitShiftByConstant - Handle transforms common to the three shifts, when
/// the shift amount is a constant.
-SDOperand DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
+SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
SDNode *LHS = N->getOperand(0).Val;
- if (!LHS->hasOneUse()) return SDOperand();
+ if (!LHS->hasOneUse()) return SDValue();
// We want to pull some binops through shifts, so that we have (and (shift))
// instead of (shift (and)), likewise for add, or, xor, etc. This sort of
@@ -2226,7 +2226,7 @@
bool HighBitSet = false; // Can we transform this if the high bit is set?
switch (LHS->getOpcode()) {
- default: return SDOperand();
+ default: return SDValue();
case ISD::OR:
case ISD::XOR:
HighBitSet = false; // We can only transform sra if the high bit is clear.
@@ -2236,14 +2236,14 @@
break;
case ISD::ADD:
if (N->getOpcode() != ISD::SHL)
- return SDOperand(); // only shl(add) not sr[al](add).
+ return SDValue(); // only shl(add) not sr[al](add).
HighBitSet = false; // We can only transform sra if the high bit is clear.
break;
}
// We require the RHS of the binop to be a constant as well.
ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
- if (!BinOpCst) return SDOperand();
+ if (!BinOpCst) return SDValue();
// FIXME: disable this for unless the input to the binop is a shift by a
@@ -2256,7 +2256,7 @@
BinOpLHSVal->getOpcode() != ISD::SRA &&
BinOpLHSVal->getOpcode() != ISD::SRL) ||
!isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
- return SDOperand();
+ return SDValue();
MVT VT = N->getValueType(0);
@@ -2268,15 +2268,15 @@
if (N->getOpcode() == ISD::SRA) {
bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
if (BinOpRHSSignSet != HighBitSet)
- return SDOperand();
+ return SDValue();
}
// Fold the constants, shifting the binop RHS by the shift amount.
- SDOperand NewRHS = DAG.getNode(N->getOpcode(), N->getValueType(0),
+ SDValue NewRHS = DAG.getNode(N->getOpcode(), N->getValueType(0),
LHS->getOperand(1), N->getOperand(1));
// Create the new shift.
- SDOperand NewShift = DAG.getNode(N->getOpcode(), VT, LHS->getOperand(0),
+ SDValue NewShift = DAG.getNode(N->getOpcode(), VT, LHS->getOperand(0),
N->getOperand(1));
// Create the new binop.
@@ -2284,9 +2284,9 @@
}
-SDOperand DAGCombiner::visitSHL(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
- SDOperand N1 = N->getOperand(1);
+SDValue DAGCombiner::visitSHL(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
MVT VT = N0.getValueType();
@@ -2305,11 +2305,11 @@
if (N1C && N1C->isNullValue())
return N0;
// if (shl x, c) is known to be zero, return 0
- if (DAG.MaskedValueIsZero(SDOperand(N, 0),
+ if (DAG.MaskedValueIsZero(SDValue(N, 0),
APInt::getAllOnesValue(VT.getSizeInBits())))
return DAG.getConstant(0, VT);
- if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
- return SDOperand(N, 0);
+ if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
+ return SDValue(N, 0);
// fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
if (N1C && N0.getOpcode() == ISD::SHL &&
N0.getOperand(1).getOpcode() == ISD::Constant) {
@@ -2326,7 +2326,7 @@
N0.getOperand(1).getOpcode() == ISD::Constant) {
uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
uint64_t c2 = N1C->getValue();
- SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
+ SDValue Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
DAG.getConstant(~0ULL << c1, VT));
if (c2 > c1)
return DAG.getNode(ISD::SHL, VT, Mask,
@@ -2340,12 +2340,12 @@
return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
DAG.getConstant(~0ULL << N1C->getValue(), VT));
- return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand();
+ return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDValue();
}
-SDOperand DAGCombiner::visitSRA(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
- SDOperand N1 = N->getOperand(1);
+SDValue DAGCombiner::visitSRA(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
MVT VT = N0.getValueType();
@@ -2411,29 +2411,29 @@
TLI.isOperationLegal(ISD::TRUNCATE, VT) &&
TLI.isTruncateFree(VT, TruncVT)) {
- SDOperand Amt = DAG.getConstant(ShiftAmt, TLI.getShiftAmountTy());
- SDOperand Shift = DAG.getNode(ISD::SRL, VT, N0.getOperand(0), Amt);
- SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, TruncVT, Shift);
+ SDValue Amt = DAG.getConstant(ShiftAmt, TLI.getShiftAmountTy());
+ SDValue Shift = DAG.getNode(ISD::SRL, VT, N0.getOperand(0), Amt);
+ SDValue Trunc = DAG.getNode(ISD::TRUNCATE, TruncVT, Shift);
return DAG.getNode(ISD::SIGN_EXTEND, N->getValueType(0), Trunc);
}
}
}
// Simplify, based on bits shifted out of the LHS.
- if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
- return SDOperand(N, 0);
+ if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
+ return SDValue(N, 0);
// If the sign bit is known to be zero, switch this to a SRL.
if (DAG.SignBitIsZero(N0))
return DAG.getNode(ISD::SRL, VT, N0, N1);
- return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand();
+ return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDValue();
}
-SDOperand DAGCombiner::visitSRL(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
- SDOperand N1 = N->getOperand(1);
+SDValue DAGCombiner::visitSRL(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
MVT VT = N0.getValueType();
@@ -2452,7 +2452,7 @@
if (N1C && N1C->isNullValue())
return N0;
// if (srl x, c) is known to be zero, return 0
- if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0),
+ if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
APInt::getAllOnesValue(OpSizeInBits)))
return DAG.getConstant(0, VT);
@@ -2474,7 +2474,7 @@
if (N1C->getValue() >= SmallVT.getSizeInBits())
return DAG.getNode(ISD::UNDEF, VT);
- SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
+ SDValue SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
AddToWorkList(SmallShift.Val);
return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
}
@@ -2509,7 +2509,7 @@
// will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
// to an SRL,XOR pair, which is likely to simplify more.
unsigned ShAmt = UnknownBits.countTrailingZeros();
- SDOperand Op = N0.getOperand(0);
+ SDValue Op = N0.getOperand(0);
if (ShAmt) {
Op = DAG.getNode(ISD::SRL, VT, Op,
DAG.getConstant(ShAmt, TLI.getShiftAmountTy()));
@@ -2521,46 +2521,46 @@
// fold operands of srl based on knowledge that the low bits are not
// demanded.
- if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
- return SDOperand(N, 0);
+ if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
+ return SDValue(N, 0);
- return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand();
+ return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDValue();
}
-SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
+SDValue DAGCombiner::visitCTLZ(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
MVT VT = N->getValueType(0);
// fold (ctlz c1) -> c2
if (isa<ConstantSDNode>(N0))
return DAG.getNode(ISD::CTLZ, VT, N0);
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
+SDValue DAGCombiner::visitCTTZ(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
MVT VT = N->getValueType(0);
// fold (cttz c1) -> c2
if (isa<ConstantSDNode>(N0))
return DAG.getNode(ISD::CTTZ, VT, N0);
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
+SDValue DAGCombiner::visitCTPOP(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
MVT VT = N->getValueType(0);
// fold (ctpop c1) -> c2
if (isa<ConstantSDNode>(N0))
return DAG.getNode(ISD::CTPOP, VT, N0);
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitSELECT(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
- SDOperand N1 = N->getOperand(1);
- SDOperand N2 = N->getOperand(2);
+SDValue DAGCombiner::visitSELECT(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
@@ -2582,7 +2582,7 @@
// fold select C, 0, 1 -> ~C
if (VT.isInteger() && VT0.isInteger() &&
N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
- SDOperand XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0));
+ SDValue XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0));
if (VT == VT0)
return XORNode;
AddToWorkList(XORNode.Val);
@@ -2592,13 +2592,13 @@
}
// fold select C, 0, X -> ~C & X
if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
- SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
+ SDValue XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
AddToWorkList(XORNode.Val);
return DAG.getNode(ISD::AND, VT, XORNode, N2);
}
// fold select C, X, 1 -> ~C | X
if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
- SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
+ SDValue XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
AddToWorkList(XORNode.Val);
return DAG.getNode(ISD::OR, VT, XORNode, N1);
}
@@ -2615,7 +2615,7 @@
// If we can fold this based on the true/false value, do so.
if (SimplifySelectOps(N, N1, N2))
- return SDOperand(N, 0); // Don't revisit N.
+ return SDValue(N, 0); // Don't revisit N.
// fold selects based on a setcc into other things, such as min/max/abs
if (N0.getOpcode() == ISD::SETCC) {
@@ -2629,15 +2629,15 @@
else
return SimplifySelect(N0, N1, N2);
}
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
- SDOperand N1 = N->getOperand(1);
- SDOperand N2 = N->getOperand(2);
- SDOperand N3 = N->getOperand(3);
- SDOperand N4 = N->getOperand(4);
+SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ SDValue N4 = N->getOperand(4);
ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
// fold select_cc lhs, rhs, x, x, cc -> x
@@ -2645,7 +2645,7 @@
return N2;
// Determine if the condition we're dealing with is constant
- SDOperand SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false);
+ SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false);
if (SCC.Val) AddToWorkList(SCC.Val);
if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) {
@@ -2663,13 +2663,13 @@
// If we can fold this based on the true/false value, do so.
if (SimplifySelectOps(N, N2, N3))
- return SDOperand(N, 0); // Don't revisit N.
+ return SDValue(N, 0); // Don't revisit N.
// fold select_cc into other things, such as min/max/abs
return SimplifySelectCC(N0, N1, N2, N3, CC);
}
-SDOperand DAGCombiner::visitSETCC(SDNode *N) {
+SDValue DAGCombiner::visitSETCC(SDNode *N) {
return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
cast<CondCodeSDNode>(N->getOperand(2))->get());
}
@@ -2678,7 +2678,7 @@
// "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))"
// transformation. Returns true if extension are possible and the above
// mentioned transformation is profitable.
-static bool ExtendUsesToFormExtLoad(SDNode *N, SDOperand N0,
+static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
unsigned ExtOpc,
SmallVector<SDNode*, 4> &ExtendNodes,
TargetLowering &TLI) {
@@ -2697,7 +2697,7 @@
return false;
bool Add = false;
for (unsigned i = 0; i != 2; ++i) {
- SDOperand UseOp = User->getOperand(i);
+ SDValue UseOp = User->getOperand(i);
if (UseOp == N0)
continue;
if (!isa<ConstantSDNode>(UseOp))
@@ -2708,7 +2708,7 @@
ExtendNodes.push_back(User);
} else {
for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
- SDOperand UseOp = User->getOperand(i);
+ SDValue UseOp = User->getOperand(i);
if (UseOp == N0) {
// If truncate from extended type to original load type is free
// on this target, then it's ok to extend a CopyToReg.
@@ -2727,7 +2727,7 @@
UI != UE; ++UI) {
SDNode *User = *UI;
for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
- SDOperand UseOp = User->getOperand(i);
+ SDValue UseOp = User->getOperand(i);
if (UseOp.Val == N && UseOp.ResNo == 0) {
BothLiveOut = true;
break;
@@ -2742,8 +2742,8 @@
return true;
}
-SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
+SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
MVT VT = N->getValueType(0);
// fold (sext c1) -> c1
@@ -2758,7 +2758,7 @@
if (N0.getOpcode() == ISD::TRUNCATE) {
// fold (sext (truncate (load x))) -> (sext (smaller load x))
// fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
- SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
+ SDValue NarrowLoad = ReduceLoadWidth(N0.Val);
if (NarrowLoad.Val) {
if (NarrowLoad.Val != N0.Val)
CombineTo(N0.Val, NarrowLoad);
@@ -2767,7 +2767,7 @@
// See if the value being truncated is already sign extended. If so, just
// eliminate the trunc/sext pair.
- SDOperand Op = N0.getOperand(0);
+ SDValue Op = N0.getOperand(0);
unsigned OpBits = Op.getValueType().getSizeInBits();
unsigned MidBits = N0.getValueType().getSizeInBits();
unsigned DestBits = VT.getSizeInBits();
@@ -2812,21 +2812,21 @@
DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
if (DoXform) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
+ SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
LN0->getSrcValueOffset(),
N0.getValueType(),
LN0->isVolatile(),
LN0->getAlignment());
CombineTo(N, ExtLoad);
- SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad);
+ SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad);
CombineTo(N0.Val, Trunc, ExtLoad.getValue(1));
// Extend SetCC uses if necessary.
for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
SDNode *SetCC = SetCCs[i];
- SmallVector<SDOperand, 4> Ops;
+ SmallVector<SDValue, 4> Ops;
for (unsigned j = 0; j != 2; ++j) {
- SDOperand SOp = SetCC->getOperand(j);
+ SDValue SOp = SetCC->getOperand(j);
if (SOp == Trunc)
Ops.push_back(ExtLoad);
else
@@ -2836,7 +2836,7 @@
CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0),
&Ops[0], Ops.size()));
}
- return SDOperand(N, 0); // Return N so it doesn't get rechecked!
+ return SDValue(N, 0); // Return N so it doesn't get rechecked!
}
}
@@ -2848,7 +2848,7 @@
MVT EVT = LN0->getMemoryVT();
if ((!AfterLegalize && !LN0->isVolatile()) ||
TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) {
- SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
+ SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
LN0->getSrcValueOffset(), EVT,
LN0->isVolatile(),
@@ -2856,13 +2856,13 @@
CombineTo(N, ExtLoad);
CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
ExtLoad.getValue(1));
- return SDOperand(N, 0); // Return N so it doesn't get rechecked!
+ return SDValue(N, 0); // Return N so it doesn't get rechecked!
}
}
// sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc
if (N0.getOpcode() == ISD::SETCC) {
- SDOperand SCC =
+ SDValue SCC =
SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT),
cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
@@ -2874,11 +2874,11 @@
DAG.SignBitIsZero(N0))
return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
+SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
MVT VT = N->getValueType(0);
// fold (zext c1) -> c1
@@ -2892,7 +2892,7 @@
// fold (zext (truncate (load x))) -> (zext (smaller load x))
// fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
if (N0.getOpcode() == ISD::TRUNCATE) {
- SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
+ SDValue NarrowLoad = ReduceLoadWidth(N0.Val);
if (NarrowLoad.Val) {
if (NarrowLoad.Val != N0.Val)
CombineTo(N0.Val, NarrowLoad);
@@ -2903,7 +2903,7 @@
// fold (zext (truncate x)) -> (and x, mask)
if (N0.getOpcode() == ISD::TRUNCATE &&
(!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) {
- SDOperand Op = N0.getOperand(0);
+ SDValue Op = N0.getOperand(0);
if (Op.getValueType().bitsLT(VT)) {
Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
} else if (Op.getValueType().bitsGT(VT)) {
@@ -2916,7 +2916,7 @@
if (N0.getOpcode() == ISD::AND &&
N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
N0.getOperand(1).getOpcode() == ISD::Constant) {
- SDOperand X = N0.getOperand(0).getOperand(0);
+ SDValue X = N0.getOperand(0).getOperand(0);
if (X.getValueType().bitsLT(VT)) {
X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
} else if (X.getValueType().bitsGT(VT)) {
@@ -2937,21 +2937,21 @@
DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
if (DoXform) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
+ SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
LN0->getSrcValueOffset(),
N0.getValueType(),
LN0->isVolatile(),
LN0->getAlignment());
CombineTo(N, ExtLoad);
- SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad);
+ SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad);
CombineTo(N0.Val, Trunc, ExtLoad.getValue(1));
// Extend SetCC uses if necessary.
for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
SDNode *SetCC = SetCCs[i];
- SmallVector<SDOperand, 4> Ops;
+ SmallVector<SDValue, 4> Ops;
for (unsigned j = 0; j != 2; ++j) {
- SDOperand SOp = SetCC->getOperand(j);
+ SDValue SOp = SetCC->getOperand(j);
if (SOp == Trunc)
Ops.push_back(ExtLoad);
else
@@ -2961,7 +2961,7 @@
CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0),
&Ops[0], Ops.size()));
}
- return SDOperand(N, 0); // Return N so it doesn't get rechecked!
+ return SDValue(N, 0); // Return N so it doesn't get rechecked!
}
}
@@ -2973,7 +2973,7 @@
MVT EVT = LN0->getMemoryVT();
if ((!AfterLegalize && !LN0->isVolatile()) ||
TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT)) {
- SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
+ SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
LN0->getSrcValueOffset(), EVT,
LN0->isVolatile(),
@@ -2981,24 +2981,24 @@
CombineTo(N, ExtLoad);
CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
ExtLoad.getValue(1));
- return SDOperand(N, 0); // Return N so it doesn't get rechecked!
+ return SDValue(N, 0); // Return N so it doesn't get rechecked!
}
}
// zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
if (N0.getOpcode() == ISD::SETCC) {
- SDOperand SCC =
+ SDValue SCC =
SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
DAG.getConstant(1, VT), DAG.getConstant(0, VT),
cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
if (SCC.Val) return SCC;
}
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
+SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
MVT VT = N->getValueType(0);
// fold (aext c1) -> c1
@@ -3015,7 +3015,7 @@
// fold (aext (truncate (load x))) -> (aext (smaller load x))
// fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
if (N0.getOpcode() == ISD::TRUNCATE) {
- SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
+ SDValue NarrowLoad = ReduceLoadWidth(N0.Val);
if (NarrowLoad.Val) {
if (NarrowLoad.Val != N0.Val)
CombineTo(N0.Val, NarrowLoad);
@@ -3025,7 +3025,7 @@
// fold (aext (truncate x))
if (N0.getOpcode() == ISD::TRUNCATE) {
- SDOperand TruncOp = N0.getOperand(0);
+ SDValue TruncOp = N0.getOperand(0);
if (TruncOp.getValueType() == VT)
return TruncOp; // x iff x size == zext size.
if (TruncOp.getValueType().bitsGT(VT))
@@ -3037,7 +3037,7 @@
if (N0.getOpcode() == ISD::AND &&
N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
N0.getOperand(1).getOpcode() == ISD::Constant) {
- SDOperand X = N0.getOperand(0).getOperand(0);
+ SDValue X = N0.getOperand(0).getOperand(0);
if (X.getValueType().bitsLT(VT)) {
X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
} else if (X.getValueType().bitsGT(VT)) {
@@ -3053,7 +3053,7 @@
((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) ||
TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
+ SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
LN0->getSrcValueOffset(),
N0.getValueType(),
@@ -3062,7 +3062,7 @@
CombineTo(N, ExtLoad);
CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
ExtLoad.getValue(1));
- return SDOperand(N, 0); // Return N so it doesn't get rechecked!
+ return SDValue(N, 0); // Return N so it doesn't get rechecked!
}
// fold (aext (zextload x)) -> (aext (truncate (zextload x)))
@@ -3073,7 +3073,7 @@
N0.hasOneUse()) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
MVT EVT = LN0->getMemoryVT();
- SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
+ SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
LN0->getChain(), LN0->getBasePtr(),
LN0->getSrcValue(),
LN0->getSrcValueOffset(), EVT,
@@ -3082,12 +3082,12 @@
CombineTo(N, ExtLoad);
CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
ExtLoad.getValue(1));
- return SDOperand(N, 0); // Return N so it doesn't get rechecked!
+ return SDValue(N, 0); // Return N so it doesn't get rechecked!
}
// aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
if (N0.getOpcode() == ISD::SETCC) {
- SDOperand SCC =
+ SDValue SCC =
SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
DAG.getConstant(1, VT), DAG.getConstant(0, VT),
cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
@@ -3095,13 +3095,13 @@
return SCC;
}
- return SDOperand();
+ return SDValue();
}
/// GetDemandedBits - See if the specified operand can be simplified with the
/// knowledge that only the bits specified by Mask are used. If so, return the
-/// simpler operand, otherwise return a null SDOperand.
-SDOperand DAGCombiner::GetDemandedBits(SDOperand V, const APInt &Mask) {
+/// simpler operand, otherwise return a null SDValue.
+SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
switch (V.getOpcode()) {
default: break;
case ISD::OR:
@@ -3120,14 +3120,14 @@
// See if we can recursively simplify the LHS.
unsigned Amt = RHSC->getValue();
APInt NewMask = Mask << Amt;
- SDOperand SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
+ SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
if (SimplifyLHS.Val) {
return DAG.getNode(ISD::SRL, V.getValueType(),
SimplifyLHS, V.getOperand(1));
}
}
}
- return SDOperand();
+ return SDValue();
}
/// ReduceLoadWidth - If the result of a wider load is shifted to right of N
@@ -3135,10 +3135,10 @@
/// of number of bits of the narrower type, transform it to a narrower load
/// from address + N / num of bits of new type. If the result is to be
/// extended, also fold the extension to form a extending load.
-SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) {
+SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
unsigned Opc = N->getOpcode();
ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
- SDOperand N0 = N->getOperand(0);
+ SDValue N0 = N->getOperand(0);
MVT VT = N->getValueType(0);
MVT EVT = N->getValueType(0);
@@ -3148,7 +3148,7 @@
ExtType = ISD::SEXTLOAD;
EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))
- return SDOperand();
+ return SDValue();
}
unsigned EVTBits = EVT.getSizeInBits();
@@ -3161,7 +3161,7 @@
if ((ShAmt & (EVTBits-1)) == 0) {
N0 = N0.getOperand(0);
if (N0.getValueType().getSizeInBits() <= EVTBits)
- return SDOperand();
+ return SDValue();
CombineSRL = true;
}
}
@@ -3185,10 +3185,10 @@
}
uint64_t PtrOff = ShAmt / 8;
unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
- SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(),
+ SDValue NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(),
DAG.getConstant(PtrOff, PtrType));
AddToWorkList(NewPtr.Val);
- SDOperand Load = (ExtType == ISD::NON_EXTLOAD)
+ SDValue Load = (ExtType == ISD::NON_EXTLOAD)
? DAG.getLoad(VT, LN0->getChain(), NewPtr,
LN0->getSrcValue(), LN0->getSrcValueOffset(),
LN0->isVolatile(), NewAlign)
@@ -3209,16 +3209,16 @@
else
return DAG.getNode(Opc, VT, Load);
}
- return SDOperand(N, 0); // Return N so it doesn't get rechecked!
+ return SDValue(N, 0); // Return N so it doesn't get rechecked!
}
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
- SDOperand N1 = N->getOperand(1);
+SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
MVT VT = N->getValueType(0);
MVT EVT = cast<VTSDNode>(N1)->getVT();
unsigned VTBits = VT.getSizeInBits();
@@ -3244,12 +3244,12 @@
// fold operands of sext_in_reg based on knowledge that the top bits are not
// demanded.
- if (SimplifyDemandedBits(SDOperand(N, 0)))
- return SDOperand(N, 0);
+ if (SimplifyDemandedBits(SDValue(N, 0)))
+ return SDValue(N, 0);
// fold (sext_in_reg (load x)) -> (smaller sextload x)
// fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
- SDOperand NarrowLoad = ReduceLoadWidth(N);
+ SDValue NarrowLoad = ReduceLoadWidth(N);
if (NarrowLoad.Val)
return NarrowLoad;
@@ -3274,14 +3274,14 @@
((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) ||
TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
+ SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
LN0->getSrcValueOffset(), EVT,
LN0->isVolatile(),
LN0->getAlignment());
CombineTo(N, ExtLoad);
CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
- return SDOperand(N, 0); // Return N so it doesn't get rechecked!
+ return SDValue(N, 0); // Return N so it doesn't get rechecked!
}
// fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
@@ -3290,20 +3290,20 @@
((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) ||
TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
+ SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
LN0->getSrcValueOffset(), EVT,
LN0->isVolatile(),
LN0->getAlignment());
CombineTo(N, ExtLoad);
CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
- return SDOperand(N, 0); // Return N so it doesn't get rechecked!
+ return SDValue(N, 0); // Return N so it doesn't get rechecked!
}
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
+SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
MVT VT = N->getValueType(0);
// noop truncate
@@ -3333,7 +3333,7 @@
// See if we can simplify the input to this truncate through knowledge that
// only the low bits are being used. For example "trunc (or (shl x, 8), y)"
// -> trunc y
- SDOperand Shorter =
+ SDValue Shorter =
GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
VT.getSizeInBits()));
if (Shorter.Val)
@@ -3345,7 +3345,7 @@
}
static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
- SDOperand Elt = N->getOperand(i);
+ SDValue Elt = N->getOperand(i);
if (Elt.getOpcode() != ISD::MERGE_VALUES)
return Elt.Val;
return Elt.getOperand(Elt.ResNo).Val;
@@ -3353,12 +3353,12 @@
/// CombineConsecutiveLoads - build_pair (load, load) -> load
/// if load locations are consecutive.
-SDOperand DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) {
+SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) {
assert(N->getOpcode() == ISD::BUILD_PAIR);
SDNode *LD1 = getBuildPairElt(N, 0);
if (!ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse())
- return SDOperand();
+ return SDValue();
MVT LD1VT = LD1->getValueType(0);
SDNode *LD2 = getBuildPairElt(N, 1);
const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
@@ -3379,11 +3379,11 @@
LD->getSrcValue(), LD->getSrcValueOffset(),
false, Align);
}
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
+SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
MVT VT = N->getValueType(0);
// If the input is a BUILD_VECTOR with all constant elements, fold this now.
@@ -3412,7 +3412,7 @@
// If the input is a constant, let getNode() fold it.
if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
- SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
+ SDValue Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
if (Res.Val != N) return Res;
}
@@ -3430,7 +3430,7 @@
getABITypeAlignment(VT.getTypeForMVT());
unsigned OrigAlign = LN0->getAlignment();
if (Align <= OrigAlign) {
- SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(),
+ SDValue Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(),
LN0->getSrcValue(), LN0->getSrcValueOffset(),
LN0->isVolatile(), OrigAlign);
AddToWorkList(N);
@@ -3445,7 +3445,7 @@
// This often reduces constant pool loads.
if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) &&
N0.Val->hasOneUse() && VT.isInteger() && !VT.isVector()) {
- SDOperand NewConv = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
+ SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
AddToWorkList(NewConv.Val);
APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
@@ -3462,7 +3462,7 @@
isa<ConstantFPSDNode>(N0.getOperand(0)) &&
VT.isInteger() && !VT.isVector()) {
unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
- SDOperand X = DAG.getNode(ISD::BIT_CONVERT,
+ SDValue X = DAG.getNode(ISD::BIT_CONVERT,
MVT::getIntegerVT(OrigXWidth),
N0.getOperand(1));
AddToWorkList(X.Val);
@@ -3486,7 +3486,7 @@
X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT));
AddToWorkList(X.Val);
- SDOperand Cst = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
+ SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
Cst = DAG.getNode(ISD::AND, VT, Cst, DAG.getConstant(~SignBit, VT));
AddToWorkList(Cst.Val);
@@ -3495,15 +3495,15 @@
// bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
if (N0.getOpcode() == ISD::BUILD_PAIR) {
- SDOperand CombineLD = CombineConsecutiveLoads(N0.Val, VT);
+ SDValue CombineLD = CombineConsecutiveLoads(N0.Val, VT);
if (CombineLD.Val)
return CombineLD;
}
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitBUILD_PAIR(SDNode *N) {
+SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
MVT VT = N->getValueType(0);
return CombineConsecutiveLoads(N, VT);
}
@@ -3511,12 +3511,12 @@
/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector
/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
/// destination element value type.
-SDOperand DAGCombiner::
+SDValue DAGCombiner::
ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) {
MVT SrcEltVT = BV->getOperand(0).getValueType();
// If this is already the right type, we're done.
- if (SrcEltVT == DstEltVT) return SDOperand(BV, 0);
+ if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
unsigned SrcBitSize = SrcEltVT.getSizeInBits();
unsigned DstBitSize = DstEltVT.getSizeInBits();
@@ -3524,7 +3524,7 @@
// If this is a conversion of N elements of one type to N elements of another
// type, convert each element. This handles FP<->INT cases.
if (SrcBitSize == DstBitSize) {
- SmallVector<SDOperand, 8> Ops;
+ SmallVector<SDValue, 8> Ops;
for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
AddToWorkList(Ops.back().Val);
@@ -3563,7 +3563,7 @@
if (SrcBitSize < DstBitSize) {
unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
- SmallVector<SDOperand, 8> Ops;
+ SmallVector<SDValue, 8> Ops;
for (unsigned i = 0, e = BV->getNumOperands(); i != e;
i += NumInputsPerOutput) {
bool isLE = TLI.isLittleEndian();
@@ -3572,7 +3572,7 @@
for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
// Shift the previously computed bits over.
NewBits <<= SrcBitSize;
- SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
+ SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
if (Op.getOpcode() == ISD::UNDEF) continue;
EltIsUndef = false;
@@ -3595,7 +3595,7 @@
bool isS2V = ISD::isScalarToVector(BV);
unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands());
- SmallVector<SDOperand, 8> Ops;
+ SmallVector<SDValue, 8> Ops;
for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
for (unsigned j = 0; j != NumOutputsPerInput; ++j)
@@ -3621,16 +3621,16 @@
-SDOperand DAGCombiner::visitFADD(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
- SDOperand N1 = N->getOperand(1);
+SDValue DAGCombiner::visitFADD(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
MVT VT = N->getValueType(0);
// fold vector ops
if (VT.isVector()) {
- SDOperand FoldedVOp = SimplifyVBinOp(N);
+ SDValue FoldedVOp = SimplifyVBinOp(N);
if (FoldedVOp.Val) return FoldedVOp;
}
@@ -3655,19 +3655,19 @@
return DAG.getNode(ISD::FADD, VT, N0.getOperand(0),
DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1));
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitFSUB(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
- SDOperand N1 = N->getOperand(1);
+SDValue DAGCombiner::visitFSUB(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
MVT VT = N->getValueType(0);
// fold vector ops
if (VT.isVector()) {
- SDOperand FoldedVOp = SimplifyVBinOp(N);
+ SDValue FoldedVOp = SimplifyVBinOp(N);
if (FoldedVOp.Val) return FoldedVOp;
}
@@ -3685,19 +3685,19 @@
return DAG.getNode(ISD::FADD, VT, N0,
GetNegatedExpression(N1, DAG, AfterLegalize));
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitFMUL(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
- SDOperand N1 = N->getOperand(1);
+SDValue DAGCombiner::visitFMUL(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
MVT VT = N->getValueType(0);
// fold vector ops
if (VT.isVector()) {
- SDOperand FoldedVOp = SimplifyVBinOp(N);
+ SDValue FoldedVOp = SimplifyVBinOp(N);
if (FoldedVOp.Val) return FoldedVOp;
}
@@ -3732,19 +3732,19 @@
return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0),
DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1));
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitFDIV(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
- SDOperand N1 = N->getOperand(1);
+SDValue DAGCombiner::visitFDIV(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
MVT VT = N->getValueType(0);
// fold vector ops
if (VT.isVector()) {
- SDOperand FoldedVOp = SimplifyVBinOp(N);
+ SDValue FoldedVOp = SimplifyVBinOp(N);
if (FoldedVOp.Val) return FoldedVOp;
}
@@ -3765,12 +3765,12 @@
}
}
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitFREM(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
- SDOperand N1 = N->getOperand(1);
+SDValue DAGCombiner::visitFREM(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
MVT VT = N->getValueType(0);
@@ -3779,12 +3779,12 @@
if (N0CFP && N1CFP && VT != MVT::ppcf128)
return DAG.getNode(ISD::FREM, VT, N0, N1);
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
- SDOperand N1 = N->getOperand(1);
+SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
MVT VT = N->getValueType(0);
@@ -3822,13 +3822,13 @@
if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0));
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
+SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
MVT VT = N->getValueType(0);
MVT OpVT = N0.getValueType();
@@ -3847,11 +3847,11 @@
}
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
+SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
MVT VT = N->getValueType(0);
MVT OpVT = N0.getValueType();
@@ -3869,34 +3869,34 @@
return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
}
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
+SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
MVT VT = N->getValueType(0);
// fold (fp_to_sint c1fp) -> c1
if (N0CFP)
return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
+SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
MVT VT = N->getValueType(0);
// fold (fp_to_uint c1fp) -> c1
if (N0CFP && VT != MVT::ppcf128)
return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
- SDOperand N1 = N->getOperand(1);
+SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
MVT VT = N->getValueType(0);
@@ -3919,37 +3919,37 @@
// fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
- SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), N1);
+ SDValue Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), N1);
AddToWorkList(Tmp.Val);
return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
}
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
+SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
MVT VT = N->getValueType(0);
MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
// fold (fp_round_inreg c1fp) -> c1fp
if (N0CFP) {
- SDOperand Round = DAG.getConstantFP(N0CFP->getValueAPF(), EVT);
+ SDValue Round = DAG.getConstantFP(N0CFP->getValueAPF(), EVT);
return DAG.getNode(ISD::FP_EXTEND, VT, Round);
}
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
+SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
MVT VT = N->getValueType(0);
// If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
if (N->hasOneUse() &&
- N->use_begin().getUse().getSDOperand().getOpcode() == ISD::FP_ROUND)
- return SDOperand();
+ N->use_begin().getUse().getSDValue().getOpcode() == ISD::FP_ROUND)
+ return SDValue();
// fold (fp_extend c1fp) -> c1fp
if (N0CFP && VT != MVT::ppcf128)
@@ -3958,7 +3958,7 @@
// Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
// value of X.
if (N0.getOpcode() == ISD::FP_ROUND && N0.Val->getConstantOperandVal(1) == 1){
- SDOperand In = N0.getOperand(0);
+ SDValue In = N0.getOperand(0);
if (In.getValueType() == VT) return In;
if (VT.bitsLT(In.getValueType()))
return DAG.getNode(ISD::FP_ROUND, VT, In, N0.getOperand(1));
@@ -3970,7 +3970,7 @@
((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) ||
TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
+ SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
LN0->getSrcValueOffset(),
N0.getValueType(),
@@ -3980,14 +3980,14 @@
CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad,
DAG.getIntPtrConstant(1)),
ExtLoad.getValue(1));
- return SDOperand(N, 0); // Return N so it doesn't get rechecked!
+ return SDValue(N, 0); // Return N so it doesn't get rechecked!
}
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitFNEG(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
+SDValue DAGCombiner::visitFNEG(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
if (isNegatibleForFree(N0, AfterLegalize))
return GetNegatedExpression(N0, DAG, AfterLegalize);
@@ -3997,7 +3997,7 @@
if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() &&
N0.getOperand(0).getValueType().isInteger() &&
!N0.getOperand(0).getValueType().isVector()) {
- SDOperand Int = N0.getOperand(0);
+ SDValue Int = N0.getOperand(0);
MVT IntVT = Int.getValueType();
if (IntVT.isInteger() && !IntVT.isVector()) {
Int = DAG.getNode(ISD::XOR, IntVT, Int,
@@ -4007,11 +4007,11 @@
}
}
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitFABS(SDNode *N) {
- SDOperand N0 = N->getOperand(0);
+SDValue DAGCombiner::visitFABS(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
MVT VT = N->getValueType(0);
@@ -4031,7 +4031,7 @@
if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() &&
N0.getOperand(0).getValueType().isInteger() &&
!N0.getOperand(0).getValueType().isVector()) {
- SDOperand Int = N0.getOperand(0);
+ SDValue Int = N0.getOperand(0);
MVT IntVT = Int.getValueType();
if (IntVT.isInteger() && !IntVT.isVector()) {
Int = DAG.getNode(ISD::AND, IntVT, Int,
@@ -4041,13 +4041,13 @@
}
}
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
- SDOperand Chain = N->getOperand(0);
- SDOperand N1 = N->getOperand(1);
- SDOperand N2 = N->getOperand(2);
+SDValue DAGCombiner::visitBRCOND(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
// never taken branch, fold to chain
@@ -4063,17 +4063,17 @@
return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
N1.getOperand(0), N1.getOperand(1), N2);
}
- return SDOperand();
+ return SDValue();
}
// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
//
-SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
+SDValue DAGCombiner::visitBR_CC(SDNode *N) {
CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
- SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
+ SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
// Use SimplifySetCC to simplify SETCC's.
- SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
+ SDValue Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
if (Simp.Val) AddToWorkList(Simp.Val);
ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
@@ -4091,7 +4091,7 @@
return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
Simp.getOperand(2), Simp.getOperand(0),
Simp.getOperand(1), N->getOperand(4));
- return SDOperand();
+ return SDValue();
}
@@ -4106,7 +4106,7 @@
return false;
bool isLoad = true;
- SDOperand Ptr;
+ SDValue Ptr;
MVT VT;
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
if (LD->isIndexed())
@@ -4135,8 +4135,8 @@
return false;
// Ask the target to do addressing mode selection.
- SDOperand BasePtr;
- SDOperand Offset;
+ SDValue BasePtr;
+ SDValue Offset;
ISD::MemIndexedMode AM = ISD::UNINDEXED;
if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
return false;
@@ -4160,7 +4160,7 @@
// Check #2.
if (!isLoad) {
- SDOperand Val = cast<StoreSDNode>(N)->getValue();
+ SDValue Val = cast<StoreSDNode>(N)->getValue();
if (Val == BasePtr || BasePtr.Val->isPredecessorOf(Val.Val))
return false;
}
@@ -4184,11 +4184,11 @@
if (!RealUse)
return false;
- SDOperand Result;
+ SDValue Result;
if (isLoad)
- Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM);
+ Result = DAG.getIndexedLoad(SDValue(N,0), BasePtr, Offset, AM);
else
- Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
+ Result = DAG.getIndexedStore(SDValue(N,0), BasePtr, Offset, AM);
++PreIndexedNodes;
++NodesCombined;
DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG));
@@ -4196,12 +4196,12 @@
DOUT << '\n';
WorkListRemover DeadNodes(*this);
if (isLoad) {
- DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
+ DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
&DeadNodes);
- DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
+ DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
&DeadNodes);
} else {
- DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
+ DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
&DeadNodes);
}
@@ -4227,7 +4227,7 @@
return false;
bool isLoad = true;
- SDOperand Ptr;
+ SDValue Ptr;
MVT VT;
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
if (LD->isIndexed())
@@ -4259,8 +4259,8 @@
(Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
continue;
- SDOperand BasePtr;
- SDOperand Offset;
+ SDValue BasePtr;
+ SDValue Offset;
ISD::MemIndexedMode AM = ISD::UNINDEXED;
if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
if (Ptr == Offset)
@@ -4311,9 +4311,9 @@
// Check for #2
if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
- SDOperand Result = isLoad
- ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM)
- : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
+ SDValue Result = isLoad
+ ? DAG.getIndexedLoad(SDValue(N,0), BasePtr, Offset, AM)
+ : DAG.getIndexedStore(SDValue(N,0), BasePtr, Offset, AM);
++PostIndexedNodes;
++NodesCombined;
DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG));
@@ -4321,12 +4321,12 @@
DOUT << '\n';
WorkListRemover DeadNodes(*this);
if (isLoad) {
- DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
+ DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
&DeadNodes);
- DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
+ DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
&DeadNodes);
} else {
- DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
+ DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
&DeadNodes);
}
@@ -4334,7 +4334,7 @@
DAG.DeleteNode(N);
// Replace the uses of Use with uses of the updated base value.
- DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0),
+ DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
Result.getValue(isLoad ? 1 : 0),
&DeadNodes);
removeFromWorkList(Op);
@@ -4348,7 +4348,7 @@
/// InferAlignment - If we can infer some alignment information from this
/// pointer, return it.
-static unsigned InferAlignment(SDOperand Ptr, SelectionDAG &DAG) {
+static unsigned InferAlignment(SDValue Ptr, SelectionDAG &DAG) {
// If this is a direct reference to a stack slot, use information about the
// stack slot's alignment.
int FrameIdx = 1 << 31;
@@ -4389,10 +4389,10 @@
return 0;
}
-SDOperand DAGCombiner::visitLOAD(SDNode *N) {
+SDValue DAGCombiner::visitLOAD(SDNode *N) {
LoadSDNode *LD = cast<LoadSDNode>(N);
- SDOperand Chain = LD->getChain();
- SDOperand Ptr = LD->getBasePtr();
+ SDValue Chain = LD->getChain();
+ SDValue Ptr = LD->getBasePtr();
// Try to infer better alignment information than the load already has.
if (LD->isUnindexed()) {
@@ -4423,30 +4423,30 @@
DOUT << "\nWith chain: "; DEBUG(Chain.Val->dump(&DAG));
DOUT << "\n";
WorkListRemover DeadNodes(*this);
- DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Chain, &DeadNodes);
+ DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes);
if (N->use_empty()) {
removeFromWorkList(N);
DAG.DeleteNode(N);
}
- return SDOperand(N, 0); // Return N so it doesn't get rechecked!
+ return SDValue(N, 0); // Return N so it doesn't get rechecked!
}
} else {
// Indexed loads.
assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
- SDOperand Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0));
+ SDValue Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0));
DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
DOUT << "\nWith: "; DEBUG(Undef.Val->dump(&DAG));
DOUT << " and 2 other values\n";
WorkListRemover DeadNodes(*this);
- DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Undef, &DeadNodes);
- DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1),
+ DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes);
+ DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
DAG.getNode(ISD::UNDEF, N->getValueType(1)),
&DeadNodes);
- DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 2), Chain, &DeadNodes);
+ DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes);
removeFromWorkList(N);
DAG.DeleteNode(N);
- return SDOperand(N, 0); // Return N so it doesn't get rechecked!
+ return SDValue(N, 0); // Return N so it doesn't get rechecked!
}
}
}
@@ -4467,11 +4467,11 @@
if (CombinerAA) {
// Walk up chain skipping non-aliasing memory nodes.
- SDOperand BetterChain = FindBetterChain(N, Chain);
+ SDValue BetterChain = FindBetterChain(N, Chain);
// If there is a better chain.
if (Chain != BetterChain) {
- SDOperand ReplLoad;
+ SDValue ReplLoad;
// Replace the chain to void dependency.
if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
@@ -4489,7 +4489,7 @@
}
// Create token factor to keep old chain connected.
- SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other,
+ SDValue Token = DAG.getNode(ISD::TokenFactor, MVT::Other,
Chain, ReplLoad.getValue(1));
// Replace uses with load result and token factor. Don't add users
@@ -4500,17 +4500,17 @@
// Try transforming N to an indexed load.
if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
- return SDOperand(N, 0);
+ return SDValue(N, 0);
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitSTORE(SDNode *N) {
+SDValue DAGCombiner::visitSTORE(SDNode *N) {
StoreSDNode *ST = cast<StoreSDNode>(N);
- SDOperand Chain = ST->getChain();
- SDOperand Value = ST->getValue();
- SDOperand Ptr = ST->getBasePtr();
+ SDValue Chain = ST->getChain();
+ SDValue Value = ST->getValue();
+ SDValue Ptr = ST->getBasePtr();
// Try to infer better alignment information than the store already has.
if (ST->isUnindexed()) {
@@ -4544,7 +4544,7 @@
// processor operation but an i64 (which is not legal) requires two. So the
// transform should not be done in this case.
if (Value.getOpcode() != ISD::TargetConstantFP) {
- SDOperand Tmp;
+ SDValue Tmp;
switch (CFP->getValueType(0).getSimpleVT()) {
default: assert(0 && "Unknown FP type");
case MVT::f80: // We don't do this for these yet.
@@ -4575,22 +4575,22 @@
// argument passing. Since this is so common, custom legalize the
// 64-bit integer store into two 32-bit stores.
uint64_t Val = CFP->getValueAPF().convertToAPInt().getZExtValue();
- SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
- SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32);
+ SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
+ SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
if (TLI.isBigEndian()) std::swap(Lo, Hi);
int SVOffset = ST->getSrcValueOffset();
unsigned Alignment = ST->getAlignment();
bool isVolatile = ST->isVolatile();
- SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(),
+ SDValue St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(),
ST->getSrcValueOffset(),
isVolatile, ST->getAlignment());
Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
DAG.getConstant(4, Ptr.getValueType()));
SVOffset += 4;
Alignment = MinAlign(Alignment, 4U);
- SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(),
+ SDValue St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(),
SVOffset, isVolatile, Alignment);
return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1);
}
@@ -4601,12 +4601,12 @@
if (CombinerAA) {
// Walk up chain skipping non-aliasing memory nodes.
- SDOperand BetterChain = FindBetterChain(N, Chain);
+ SDValue BetterChain = FindBetterChain(N, Chain);
// If there is a better chain.
if (Chain != BetterChain) {
// Replace the chain to avoid dependency.
- SDOperand ReplStore;
+ SDValue ReplStore;
if (ST->isTruncatingStore()) {
ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr,
ST->getSrcValue(),ST->getSrcValueOffset(),
@@ -4619,7 +4619,7 @@
}
// Create token to keep both nodes around.
- SDOperand Token =
+ SDValue Token =
DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore);
// Don't add users to work list.
@@ -4629,7 +4629,7 @@
// Try transforming N to an indexed store.
if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
- return SDOperand(N, 0);
+ return SDValue(N, 0);
// FIXME: is there such a thing as a truncating indexed store?
if (ST->isTruncatingStore() && ST->isUnindexed() &&
@@ -4637,7 +4637,7 @@
// See if we can simplify the input to this truncstore with knowledge that
// only the low bits are being used. For example:
// "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
- SDOperand Shorter =
+ SDValue Shorter =
GetDemandedBits(Value,
APInt::getLowBitsSet(Value.getValueSizeInBits(),
ST->getMemoryVT().getSizeInBits()));
@@ -4653,7 +4653,7 @@
APInt::getLowBitsSet(
Value.getValueSizeInBits(),
ST->getMemoryVT().getSizeInBits())))
- return SDOperand(N, 0);
+ return SDValue(N, 0);
}
// If this is a load followed by a store to the same location, then the store
@@ -4663,7 +4663,7 @@
ST->isUnindexed() && !ST->isVolatile() &&
// There can't be any side effects between the load and store, such as
// a call or store.
- Chain.reachesChainWithoutSideEffects(SDOperand(Ld, 1))) {
+ Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
// The store is dead, remove it.
return Chain;
}
@@ -4680,39 +4680,39 @@
ST->isVolatile(), ST->getAlignment());
}
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
- SDOperand InVec = N->getOperand(0);
- SDOperand InVal = N->getOperand(1);
- SDOperand EltNo = N->getOperand(2);
+SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
+ SDValue InVec = N->getOperand(0);
+ SDValue InVal = N->getOperand(1);
+ SDValue EltNo = N->getOperand(2);
// If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
// vector with the inserted element.
if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
- SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
+ SmallVector<SDValue, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
if (Elt < Ops.size())
Ops[Elt] = InVal;
return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
&Ops[0], Ops.size());
}
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
+SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
// (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
// (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
// (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
// Perform only after legalization to ensure build_vector / vector_shuffle
// optimizations have already been done.
- if (!AfterLegalize) return SDOperand();
+ if (!AfterLegalize) return SDValue();
- SDOperand InVec = N->getOperand(0);
- SDOperand EltNo = N->getOperand(1);
+ SDValue InVec = N->getOperand(0);
+ SDValue EltNo = N->getOperand(1);
if (isa<ConstantSDNode>(EltNo)) {
unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
@@ -4723,7 +4723,7 @@
if (InVec.getOpcode() == ISD::BIT_CONVERT) {
MVT BCVT = InVec.getOperand(0).getValueType();
if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType()))
- return SDOperand();
+ return SDValue();
InVec = InVec.getOperand(0);
EVT = BCVT.getVectorElementType();
NewLoad = true;
@@ -4752,7 +4752,7 @@
}
}
if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile())
- return SDOperand();
+ return SDValue();
unsigned Align = LN0->getAlignment();
if (NewLoad) {
@@ -4761,11 +4761,11 @@
unsigned NewAlign = TLI.getTargetMachine().getTargetData()->
getABITypeAlignment(LVT.getTypeForMVT());
if (NewAlign > Align || !TLI.isOperationLegal(ISD::LOAD, LVT))
- return SDOperand();
+ return SDValue();
Align = NewAlign;
}
- SDOperand NewPtr = LN0->getBasePtr();
+ SDValue NewPtr = LN0->getBasePtr();
if (Elt) {
unsigned PtrOff = LVT.getSizeInBits() * Elt / 8;
MVT PtrType = NewPtr.getValueType();
@@ -4778,11 +4778,11 @@
LN0->getSrcValue(), LN0->getSrcValueOffset(),
LN0->isVolatile(), Align);
}
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
+SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
unsigned NumInScalars = N->getNumOperands();
MVT VT = N->getValueType(0);
unsigned NumElts = VT.getVectorNumElements();
@@ -4791,7 +4791,7 @@
// Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
// operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
// at most two distinct vectors, turn this into a shuffle node.
- SDOperand VecIn1, VecIn2;
+ SDValue VecIn1, VecIn2;
for (unsigned i = 0; i != NumInScalars; ++i) {
// Ignore undef inputs.
if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
@@ -4800,15 +4800,15 @@
// constant index, bail out.
if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
!isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
- VecIn1 = VecIn2 = SDOperand(0, 0);
+ VecIn1 = VecIn2 = SDValue(0, 0);
break;
}
// If the input vector type disagrees with the result of the build_vector,
// we can't make a shuffle.
- SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0);
+ SDValue ExtractedFromVec = N->getOperand(i).getOperand(0);
if (ExtractedFromVec.getValueType() != VT) {
- VecIn1 = VecIn2 = SDOperand(0, 0);
+ VecIn1 = VecIn2 = SDValue(0, 0);
break;
}
@@ -4822,21 +4822,21 @@
VecIn2 = ExtractedFromVec;
} else {
// Too many inputs.
- VecIn1 = VecIn2 = SDOperand(0, 0);
+ VecIn1 = VecIn2 = SDValue(0, 0);
break;
}
}
// If everything is good, we can make a shuffle operation.
if (VecIn1.Val) {
- SmallVector<SDOperand, 8> BuildVecIndices;
+ SmallVector<SDValue, 8> BuildVecIndices;
for (unsigned i = 0; i != NumInScalars; ++i) {
if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy()));
continue;
}
- SDOperand Extract = N->getOperand(i);
+ SDValue Extract = N->getOperand(i);
// If extracting from the first vector, just use the index directly.
if (Extract.getOperand(0) == VecIn1) {
@@ -4853,13 +4853,13 @@
MVT BuildVecVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts);
// Return the new VECTOR_SHUFFLE node.
- SDOperand Ops[5];
+ SDValue Ops[5];
Ops[0] = VecIn1;
if (VecIn2.Val) {
Ops[1] = VecIn2;
} else {
// Use an undef build_vector as input for the second operand.
- std::vector<SDOperand> UnOps(NumInScalars,
+ std::vector<SDValue> UnOps(NumInScalars,
DAG.getNode(ISD::UNDEF,
EltType));
Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT,
@@ -4871,10 +4871,10 @@
return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3);
}
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
+SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
// TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
// EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
// inputs come from at most two distinct vectors, turn this into a shuffle
@@ -4885,11 +4885,11 @@
return N->getOperand(0);
}
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
- SDOperand ShufMask = N->getOperand(2);
+SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
+ SDValue ShufMask = N->getOperand(2);
unsigned NumElts = ShufMask.getNumOperands();
// If the shuffle mask is an identity operation on the LHS, return the LHS.
@@ -4937,8 +4937,8 @@
}
}
- SDOperand N0 = N->getOperand(0);
- SDOperand N1 = N->getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Normalize unary shuffle so the RHS is undef.
if (isUnary && VecNum == 1)
std::swap(N0, N1);
@@ -4952,7 +4952,7 @@
// not the number of vector elements, look through it. Be careful not to
// look though conversions that change things like v4f32 to v2f64.
if (V->getOpcode() == ISD::BIT_CONVERT) {
- SDOperand ConvInput = V->getOperand(0);
+ SDValue ConvInput = V->getOperand(0);
if (ConvInput.getValueType().isVector() &&
ConvInput.getValueType().getVectorNumElements() == NumElts)
V = ConvInput.Val;
@@ -4961,7 +4961,7 @@
if (V->getOpcode() == ISD::BUILD_VECTOR) {
unsigned NumElems = V->getNumOperands();
if (NumElems > BaseIdx) {
- SDOperand Base;
+ SDValue Base;
bool AllSame = true;
for (unsigned i = 0; i != NumElems; ++i) {
if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
@@ -4990,7 +4990,7 @@
if (isUnary || N0 == N1) {
// Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
// first operand.
- SmallVector<SDOperand, 8> MappedOps;
+ SmallVector<SDValue, 8> MappedOps;
for (unsigned i = 0; i != NumElts; ++i) {
if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
@@ -5011,85 +5011,85 @@
ShufMask);
}
- return SDOperand();
+ return SDValue();
}
/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
/// an AND to a vector_shuffle with the destination vector and a zero vector.
/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
/// vector_shuffle V, Zero, <0, 4, 2, 4>
-SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) {
- SDOperand LHS = N->getOperand(0);
- SDOperand RHS = N->getOperand(1);
+SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
+ SDValue LHS = N->getOperand(0);
+ SDValue RHS = N->getOperand(1);
if (N->getOpcode() == ISD::AND) {
if (RHS.getOpcode() == ISD::BIT_CONVERT)
RHS = RHS.getOperand(0);
if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
- std::vector<SDOperand> IdxOps;
+ std::vector<SDValue> IdxOps;
unsigned NumOps = RHS.getNumOperands();
unsigned NumElts = NumOps;
MVT EVT = RHS.getValueType().getVectorElementType();
for (unsigned i = 0; i != NumElts; ++i) {
- SDOperand Elt = RHS.getOperand(i);
+ SDValue Elt = RHS.getOperand(i);
if (!isa<ConstantSDNode>(Elt))
- return SDOperand();
+ return SDValue();
else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
IdxOps.push_back(DAG.getConstant(i, EVT));
else if (cast<ConstantSDNode>(Elt)->isNullValue())
IdxOps.push_back(DAG.getConstant(NumElts, EVT));
else
- return SDOperand();
+ return SDValue();
}
// Let's see if the target supports this vector_shuffle.
if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG))
- return SDOperand();
+ return SDValue();
// Return the new VECTOR_SHUFFLE node.
MVT VT = MVT::getVectorVT(EVT, NumElts);
- std::vector<SDOperand> Ops;
+ std::vector<SDValue> Ops;
LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS);
Ops.push_back(LHS);
AddToWorkList(LHS.Val);
- std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT));
+ std::vector<SDValue> ZeroOps(NumElts, DAG.getConstant(0, EVT));
Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT,
&ZeroOps[0], ZeroOps.size()));
Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT,
&IdxOps[0], IdxOps.size()));
- SDOperand Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT,
+ SDValue Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT,
&Ops[0], Ops.size());
if (VT != N->getValueType(0))
Result = DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Result);
return Result;
}
}
- return SDOperand();
+ return SDValue();
}
/// SimplifyVBinOp - Visit a binary vector operation, like ADD.
-SDOperand DAGCombiner::SimplifyVBinOp(SDNode *N) {
+SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
// After legalize, the target may be depending on adds and other
// binary ops to provide legal ways to construct constants or other
// things. Simplifying them may result in a loss of legality.
- if (AfterLegalize) return SDOperand();
+ if (AfterLegalize) return SDValue();
MVT VT = N->getValueType(0);
assert(VT.isVector() && "SimplifyVBinOp only works on vectors!");
MVT EltType = VT.getVectorElementType();
- SDOperand LHS = N->getOperand(0);
- SDOperand RHS = N->getOperand(1);
- SDOperand Shuffle = XformToShuffleWithZero(N);
+ SDValue LHS = N->getOperand(0);
+ SDValue RHS = N->getOperand(1);
+ SDValue Shuffle = XformToShuffleWithZero(N);
if (Shuffle.Val) return Shuffle;
// If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
// this operation.
if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
RHS.getOpcode() == ISD::BUILD_VECTOR) {
- SmallVector<SDOperand, 8> Ops;
+ SmallVector<SDValue, 8> Ops;
for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
- SDOperand LHSOp = LHS.getOperand(i);
- SDOperand RHSOp = RHS.getOperand(i);
+ SDValue LHSOp = LHS.getOperand(i);
+ SDValue RHSOp = RHS.getOperand(i);
// If these two elements can't be folded, bail out.
if ((LHSOp.getOpcode() != ISD::UNDEF &&
LHSOp.getOpcode() != ISD::Constant &&
@@ -5121,13 +5121,13 @@
}
}
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
+SDValue DAGCombiner::SimplifySelect(SDValue N0, SDValue N1, SDValue N2){
assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
- SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
+ SDValue SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
cast<CondCodeSDNode>(N0.getOperand(2))->get());
// If we got a simplified select_cc node back from SimplifySelectCC, then
// break it down into a new SETCC node, and a new SELECT node, and then return
@@ -5136,7 +5136,7 @@
// Check to see if we got a select_cc back (to turn into setcc/select).
// Otherwise, just return whatever node we got back, like fabs.
if (SCC.getOpcode() == ISD::SELECT_CC) {
- SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
+ SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
SCC.getOperand(0), SCC.getOperand(1),
SCC.getOperand(4));
AddToWorkList(SETCC.Val);
@@ -5145,7 +5145,7 @@
}
return SCC;
}
- return SDOperand();
+ return SDValue();
}
/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
@@ -5155,8 +5155,8 @@
/// node) back to the top-level of the DAG combiner loop to avoid it being
/// looked at.
///
-bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
- SDOperand RHS) {
+bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
+ SDValue RHS) {
// If this is a select from two identical things, try to pull the operation
// through the select.
@@ -5179,7 +5179,7 @@
// FIXME: this conflates two src values, discarding one. This is not
// the right thing to do, but nothing uses srcvalues now. When they do,
// turn SrcValue into a list of locations.
- SDOperand Addr;
+ SDValue Addr;
if (TheSelect->getOpcode() == ISD::SELECT) {
// Check that the condition doesn't reach either load. If so, folding
// this will induce a cycle into the DAG.
@@ -5205,7 +5205,7 @@
}
if (Addr.Val) {
- SDOperand Load;
+ SDValue Load;
if (LLD->getExtensionType() == ISD::NON_EXTLOAD)
Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(),
Addr,LLD->getSrcValue(),
@@ -5237,9 +5237,9 @@
return false;
}
-SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
- SDOperand N2, SDOperand N3,
- ISD::CondCode CC, bool NotExtCompare) {
+SDValue DAGCombiner::SimplifySelectCC(SDValue N0, SDValue N1,
+ SDValue N2, SDValue N3,
+ ISD::CondCode CC, bool NotExtCompare) {
MVT VT = N2.getValueType();
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
@@ -5247,7 +5247,7 @@
ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
// Determine if the condition we're dealing with is constant
- SDOperand SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false);
+ SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false);
if (SCC.Val) AddToWorkList(SCC.Val);
ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
@@ -5291,8 +5291,8 @@
if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
unsigned ShCtV = N2C->getAPIntValue().logBase2();
ShCtV = XType.getSizeInBits()-ShCtV-1;
- SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
- SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
+ SDValue ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
+ SDValue Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
AddToWorkList(Shift.Val);
if (XType.bitsGT(AType)) {
Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
@@ -5300,7 +5300,7 @@
}
return DAG.getNode(ISD::AND, AType, Shift, N2);
}
- SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
+ SDValue Shift = DAG.getNode(ISD::SRA, XType, N0,
DAG.getConstant(XType.getSizeInBits()-1,
TLI.getShiftAmountTy()));
AddToWorkList(Shift.Val);
@@ -5319,12 +5319,12 @@
// If the caller doesn't want us to simplify this into a zext of a compare,
// don't do it.
if (NotExtCompare && N2C->getAPIntValue() == 1)
- return SDOperand();
+ return SDValue();
// Get a SetCC of the condition
// FIXME: Should probably make sure that setcc is legal if we ever have a
// target where it isn't.
- SDOperand Temp, SCC;
+ SDValue Temp, SCC;
// cast from setcc result type to select result type
if (AfterLegalize) {
SCC = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC);
@@ -5354,7 +5354,7 @@
MVT XType = N0.getValueType();
if (!AfterLegalize ||
TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(N0))) {
- SDOperand Res = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC);
+ SDValue Res = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC);
if (Res.getValueType() != VT)
Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
return Res;
@@ -5364,16 +5364,16 @@
if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
(!AfterLegalize ||
TLI.isOperationLegal(ISD::CTLZ, XType))) {
- SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
+ SDValue Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
return DAG.getNode(ISD::SRL, XType, Ctlz,
DAG.getConstant(Log2_32(XType.getSizeInBits()),
TLI.getShiftAmountTy()));
}
// setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
- SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
+ SDValue NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
N0);
- SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
+ SDValue NotN0 = DAG.getNode(ISD::XOR, XType, N0,
DAG.getConstant(~0ULL, XType));
return DAG.getNode(ISD::SRL, XType,
DAG.getNode(ISD::AND, XType, NegN0, NotN0),
@@ -5382,7 +5382,7 @@
}
// setgt X, -1 -> xor (srl (X, size(X)-1), 1)
if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
- SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
+ SDValue Sign = DAG.getNode(ISD::SRL, XType, N0,
DAG.getConstant(XType.getSizeInBits()-1,
TLI.getShiftAmountTy()));
return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
@@ -5395,10 +5395,10 @@
N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) &&
N2.getOperand(0) == N1 && N0.getValueType().isInteger()) {
MVT XType = N0.getValueType();
- SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
+ SDValue Shift = DAG.getNode(ISD::SRA, XType, N0,
DAG.getConstant(XType.getSizeInBits()-1,
TLI.getShiftAmountTy()));
- SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
+ SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
AddToWorkList(Shift.Val);
AddToWorkList(Add.Val);
return DAG.getNode(ISD::XOR, XType, Add, Shift);
@@ -5410,10 +5410,10 @@
if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) {
MVT XType = N0.getValueType();
if (SubC->isNullValue() && XType.isInteger()) {
- SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
+ SDValue Shift = DAG.getNode(ISD::SRA, XType, N0,
DAG.getConstant(XType.getSizeInBits()-1,
TLI.getShiftAmountTy()));
- SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
+ SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
AddToWorkList(Shift.Val);
AddToWorkList(Add.Val);
return DAG.getNode(ISD::XOR, XType, Add, Shift);
@@ -5421,13 +5421,13 @@
}
}
- return SDOperand();
+ return SDValue();
}
/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
-SDOperand DAGCombiner::SimplifySetCC(MVT VT, SDOperand N0,
- SDOperand N1, ISD::CondCode Cond,
- bool foldBooleans) {
+SDValue DAGCombiner::SimplifySetCC(MVT VT, SDValue N0,
+ SDValue N1, ISD::CondCode Cond,
+ bool foldBooleans) {
TargetLowering::DAGCombinerInfo
DagCombineInfo(DAG, !AfterLegalize, false, this);
return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo);
@@ -5437,9 +5437,9 @@
/// return a DAG expression to select that will generate the same value by
/// multiplying by a magic number. See:
/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
-SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
+SDValue DAGCombiner::BuildSDIV(SDNode *N) {
std::vector<SDNode*> Built;
- SDOperand S = TLI.BuildSDIV(N, DAG, &Built);
+ SDValue S = TLI.BuildSDIV(N, DAG, &Built);
for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
ii != ee; ++ii)
@@ -5451,9 +5451,9 @@
/// return a DAG expression to select that will generate the same value by
/// multiplying by a magic number. See:
/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
-SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
+SDValue DAGCombiner::BuildUDIV(SDNode *N) {
std::vector<SDNode*> Built;
- SDOperand S = TLI.BuildUDIV(N, DAG, &Built);
+ SDValue S = TLI.BuildUDIV(N, DAG, &Built);
for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
ii != ee; ++ii)
@@ -5463,7 +5463,7 @@
/// FindBaseOffset - Return true if base is known not to alias with anything
/// but itself. Provides base object and offset as results.
-static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) {
+static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset) {
// Assume it is a primitive operation.
Base = Ptr; Offset = 0;
@@ -5483,16 +5483,16 @@
/// isAlias - Return true if there is any possibility that the two addresses
/// overlap.
-bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1,
+bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
const Value *SrcValue1, int SrcValueOffset1,
- SDOperand Ptr2, int64_t Size2,
+ SDValue Ptr2, int64_t Size2,
const Value *SrcValue2, int SrcValueOffset2)
{
// If they are the same then they must be aliases.
if (Ptr1 == Ptr2) return true;
// Gather base node and offset information.
- SDOperand Base1, Base2;
+ SDValue Base1, Base2;
int64_t Offset1, Offset2;
bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1);
bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2);
@@ -5524,7 +5524,7 @@
/// FindAliasInfo - Extracts the relevant alias information from the memory
/// node. Returns true if the operand was a load.
bool DAGCombiner::FindAliasInfo(SDNode *N,
- SDOperand &Ptr, int64_t &Size,
+ SDValue &Ptr, int64_t &Size,
const Value *&SrcValue, int &SrcValueOffset) {
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
Ptr = LD->getBasePtr();
@@ -5546,13 +5546,13 @@
/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
/// looking for aliasing nodes and adding them to the Aliases vector.
-void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain,
- SmallVector<SDOperand, 8> &Aliases) {
- SmallVector<SDOperand, 8> Chains; // List of chains to visit.
+void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
+ SmallVector<SDValue, 8> &Aliases) {
+ SmallVector<SDValue, 8> Chains; // List of chains to visit.
std::set<SDNode *> Visited; // Visited node set.
// Get alias information for node.
- SDOperand Ptr;
+ SDValue Ptr;
int64_t Size;
const Value *SrcValue;
int SrcValueOffset;
@@ -5565,7 +5565,7 @@
// aliases list. If not, then continue up the chain looking for the next
// candidate.
while (!Chains.empty()) {
- SDOperand Chain = Chains.back();
+ SDValue Chain = Chains.back();
Chains.pop_back();
// Don't bother if we've been before.
@@ -5580,7 +5580,7 @@
case ISD::LOAD:
case ISD::STORE: {
// Get alias information for Chain.
- SDOperand OpPtr;
+ SDValue OpPtr;
int64_t OpSize;
const Value *OpSrcValue;
int OpSrcValueOffset;
@@ -5622,8 +5622,8 @@
/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
/// for a better chain (aliasing node.)
-SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) {
- SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor.
+SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
+ SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
// Accumulate all the aliases to this node.
GatherAllAliases(N, OldChain, Aliases);
@@ -5637,7 +5637,7 @@
}
// Construct a custom tailored token factor.
- SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
+ SDValue NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
&Aliases[0], Aliases.size());
// Make sure the old chain gets cleaned up.
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sun Jul 27 16:46:04 2008
@@ -57,7 +57,7 @@
/// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
/// legalized. We use this to ensure that calls are properly serialized
/// against each other, including inserted libcalls.
- SDOperand LastCALLSEQ_END;
+ SDValue LastCALLSEQ_END;
/// IsLegalizingCall - This member is used *only* for purposes of providing
/// helpful assertions that a libcall isn't created while another call is
@@ -78,35 +78,35 @@
/// LegalizedNodes - For nodes that are of legal width, and that have more
/// than one use, this map indicates what regularized operand to use. This
/// allows us to avoid legalizing the same thing more than once.
- DenseMap<SDOperand, SDOperand> LegalizedNodes;
+ DenseMap<SDValue, SDValue> LegalizedNodes;
/// PromotedNodes - For nodes that are below legal width, and that have more
/// than one use, this map indicates what promoted value to use. This allows
/// us to avoid promoting the same thing more than once.
- DenseMap<SDOperand, SDOperand> PromotedNodes;
+ DenseMap<SDValue, SDValue> PromotedNodes;
/// ExpandedNodes - For nodes that need to be expanded this map indicates
/// which which operands are the expanded version of the input. This allows
/// us to avoid expanding the same node more than once.
- DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
+ DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedNodes;
/// SplitNodes - For vector nodes that need to be split, this map indicates
/// which which operands are the split version of the input. This allows us
/// to avoid splitting the same node more than once.
- std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
+ std::map<SDValue, std::pair<SDValue, SDValue> > SplitNodes;
/// ScalarizedNodes - For nodes that need to be converted from vector types to
/// scalar types, this contains the mapping of ones we have already
/// processed to the result.
- std::map<SDOperand, SDOperand> ScalarizedNodes;
+ std::map<SDValue, SDValue> ScalarizedNodes;
- void AddLegalizedOperand(SDOperand From, SDOperand To) {
+ void AddLegalizedOperand(SDValue From, SDValue To) {
LegalizedNodes.insert(std::make_pair(From, To));
// If someone requests legalization of the new node, return itself.
if (From != To)
LegalizedNodes.insert(std::make_pair(To, To));
}
- void AddPromotedOperand(SDOperand From, SDOperand To) {
+ void AddPromotedOperand(SDValue From, SDValue To) {
bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
assert(isNew && "Got into the map somehow?");
// If someone requests legalization of the new node, return itself.
@@ -134,49 +134,49 @@
private:
/// HandleOp - Legalize, Promote, or Expand the specified operand as
/// appropriate for its type.
- void HandleOp(SDOperand Op);
+ void HandleOp(SDValue Op);
/// LegalizeOp - We know that the specified value has a legal type.
/// Recursively ensure that the operands have legal types, then return the
/// result.
- SDOperand LegalizeOp(SDOperand O);
+ SDValue LegalizeOp(SDValue O);
/// UnrollVectorOp - We know that the given vector has a legal type, however
/// the operation it performs is not legal and is an operation that we have
/// no way of lowering. "Unroll" the vector, splitting out the scalars and
/// operating on each element individually.
- SDOperand UnrollVectorOp(SDOperand O);
+ SDValue UnrollVectorOp(SDValue O);
/// PerformInsertVectorEltInMemory - Some target cannot handle a variable
/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
/// is necessary to spill the vector being inserted into to memory, perform
/// the insert there, and then read the result back.
- SDOperand PerformInsertVectorEltInMemory(SDOperand Vec, SDOperand Val,
- SDOperand Idx);
+ SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
+ SDValue Idx);
/// PromoteOp - Given an operation that produces a value in an invalid type,
/// promote it to compute the value into a larger type. The produced value
/// will have the correct bits for the low portion of the register, but no
/// guarantee is made about the top bits: it may be zero, sign-extended, or
/// garbage.
- SDOperand PromoteOp(SDOperand O);
+ SDValue PromoteOp(SDValue O);
- /// ExpandOp - Expand the specified SDOperand into its two component pieces
+ /// ExpandOp - Expand the specified SDValue into its two component pieces
/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
/// the LegalizeNodes map is filled in for any results that are not expanded,
/// the ExpandedNodes map is filled in for any results that are expanded, and
/// the Lo/Hi values are returned. This applies to integer types and Vector
/// types.
- void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
+ void ExpandOp(SDValue O, SDValue &Lo, SDValue &Hi);
/// SplitVectorOp - Given an operand of vector type, break it down into
/// two smaller values.
- void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
+ void SplitVectorOp(SDValue O, SDValue &Lo, SDValue &Hi);
/// ScalarizeVectorOp - Given an operand of single-element vector type
/// (e.g. v1f32), convert it into the equivalent operation that returns a
/// scalar (e.g. f32) value.
- SDOperand ScalarizeVectorOp(SDOperand O);
+ SDValue ScalarizeVectorOp(SDValue O);
/// isShuffleLegal - Return non-null if a vector shuffle is legal with the
/// specified mask and type. Targets can specify exactly which masks they
@@ -187,33 +187,33 @@
///
/// If this is a legal shuffle, this method returns the (possibly promoted)
/// build_vector Mask. If it's not a legal shuffle, it returns null.
- SDNode *isShuffleLegal(MVT VT, SDOperand Mask) const;
+ SDNode *isShuffleLegal(MVT VT, SDValue Mask) const;
bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
- void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
+ void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC);
- SDOperand ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned,
- SDOperand &Hi);
- SDOperand ExpandIntToFP(bool isSigned, MVT DestTy, SDOperand Source);
-
- SDOperand EmitStackConvert(SDOperand SrcOp, MVT SlotVT, MVT DestVT);
- SDOperand ExpandBUILD_VECTOR(SDNode *Node);
- SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
- SDOperand ExpandLegalINT_TO_FP(bool isSigned, SDOperand LegalOp, MVT DestVT);
- SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT DestVT, bool isSigned);
- SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT DestVT, bool isSigned);
-
- SDOperand ExpandBSWAP(SDOperand Op);
- SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
- bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
- SDOperand &Lo, SDOperand &Hi);
- void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
- SDOperand &Lo, SDOperand &Hi);
+ SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned,
+ SDValue &Hi);
+ SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source);
+
+ SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT);
+ SDValue ExpandBUILD_VECTOR(SDNode *Node);
+ SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
+ SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT);
+ SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned);
+ SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned);
+
+ SDValue ExpandBSWAP(SDValue Op);
+ SDValue ExpandBitCount(unsigned Opc, SDValue Op);
+ bool ExpandShift(unsigned Opc, SDValue Op, SDValue Amt,
+ SDValue &Lo, SDValue &Hi);
+ void ExpandShiftParts(unsigned NodeOp, SDValue Op, SDValue Amt,
+ SDValue &Lo, SDValue &Hi);
- SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op);
- SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
+ SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op);
+ SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op);
};
}
@@ -223,7 +223,7 @@
///
/// Note that this will also return true for shuffles that are promoted to a
/// different type.
-SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDOperand Mask) const {
+SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDValue Mask) const {
switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
default: return 0;
case TargetLowering::Legal:
@@ -241,9 +241,9 @@
assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
if (NumEltsGrowth > 1) {
// Renumber the elements.
- SmallVector<SDOperand, 8> Ops;
+ SmallVector<SDValue, 8> Ops;
for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
- SDOperand InOp = Mask.getOperand(i);
+ SDValue InOp = Mask.getOperand(i);
for (unsigned j = 0; j != NumEltsGrowth; ++j) {
if (InOp.getOpcode() == ISD::UNDEF)
Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
@@ -322,10 +322,10 @@
ComputeTopDownOrdering(DAG, Order);
for (unsigned i = 0, e = Order.size(); i != e; ++i)
- HandleOp(SDOperand(Order[i], 0));
+ HandleOp(SDValue(Order[i], 0));
// Finally, it's possible the root changed. Get the new root.
- SDOperand OldRoot = DAG.getRoot();
+ SDValue OldRoot = DAG.getRoot();
assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
DAG.setRoot(LegalizedNodes[OldRoot]);
@@ -349,15 +349,15 @@
return 0; // No CallSeqEnd
// The chain is usually at the end.
- SDOperand TheChain(Node, Node->getNumValues()-1);
+ SDValue TheChain(Node, Node->getNumValues()-1);
if (TheChain.getValueType() != MVT::Other) {
// Sometimes it's at the beginning.
- TheChain = SDOperand(Node, 0);
+ TheChain = SDValue(Node, 0);
if (TheChain.getValueType() != MVT::Other) {
// Otherwise, hunt for it.
for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
if (Node->getValueType(i) == MVT::Other) {
- TheChain = SDOperand(Node, i);
+ TheChain = SDValue(Node, i);
break;
}
@@ -410,13 +410,13 @@
// reach N.
switch (getTypeAction(N->getValueType(0))) {
case Legal:
- if (LegalizedNodes.count(SDOperand(N, 0))) return false;
+ if (LegalizedNodes.count(SDValue(N, 0))) return false;
break;
case Promote:
- if (PromotedNodes.count(SDOperand(N, 0))) return false;
+ if (PromotedNodes.count(SDValue(N, 0))) return false;
break;
case Expand:
- if (ExpandedNodes.count(SDOperand(N, 0))) return false;
+ if (ExpandedNodes.count(SDValue(N, 0))) return false;
break;
}
@@ -433,13 +433,13 @@
}
// Okay, this node looks safe, legalize it and return false.
- HandleOp(SDOperand(N, 0));
+ HandleOp(SDValue(N, 0));
return false;
}
/// HandleOp - Legalize, Promote, or Expand the specified operand as
/// appropriate for its type.
-void SelectionDAGLegalize::HandleOp(SDOperand Op) {
+void SelectionDAGLegalize::HandleOp(SDValue Op) {
MVT VT = Op.getValueType();
switch (getTypeAction(VT)) {
default: assert(0 && "Bad type action!");
@@ -449,7 +449,7 @@
if (!VT.isVector()) {
// If this is an illegal scalar, expand it into its two component
// pieces.
- SDOperand X, Y;
+ SDValue X, Y;
if (Op.getOpcode() == ISD::TargetConstant)
break; // Allow illegal target nodes.
ExpandOp(Op, X, Y);
@@ -460,7 +460,7 @@
} else {
// Otherwise, this is an illegal multiple element vector.
// Split it in half and legalize both parts.
- SDOperand X, Y;
+ SDValue X, Y;
SplitVectorOp(Op, X, Y);
}
break;
@@ -469,7 +469,7 @@
/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
/// a load from the constant pool.
-static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
+static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
SelectionDAG &DAG, TargetLowering &TLI) {
bool Extend = false;
@@ -504,7 +504,7 @@
}
}
- SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
+ SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
if (Extend)
return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(),
CPIdx, PseudoSourceValue::getConstantPool(),
@@ -517,8 +517,8 @@
/// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
/// operations.
static
-SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT,
- SelectionDAG &DAG, TargetLowering &TLI) {
+SDValue ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT,
+ SelectionDAG &DAG, TargetLowering &TLI) {
MVT VT = Node->getValueType(0);
MVT SrcVT = Node->getOperand(1).getValueType();
assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
@@ -526,11 +526,11 @@
MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
// First get the sign bit of second operand.
- SDOperand Mask1 = (SrcVT == MVT::f64)
+ SDValue Mask1 = (SrcVT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
: DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
- SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
+ SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
// Shift right or sign-extend it if the two operands have different types.
int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits();
@@ -545,11 +545,11 @@
}
// Clear the sign bit of first operand.
- SDOperand Mask2 = (VT == MVT::f64)
+ SDValue Mask2 = (VT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
: DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
- SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
+ SDValue Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
// Or the value with the sign bit.
@@ -559,11 +559,11 @@
/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
static
-SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
- TargetLowering &TLI) {
- SDOperand Chain = ST->getChain();
- SDOperand Ptr = ST->getBasePtr();
- SDOperand Val = ST->getValue();
+SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
+ TargetLowering &TLI) {
+ SDValue Chain = ST->getChain();
+ SDValue Ptr = ST->getBasePtr();
+ SDValue Val = ST->getValue();
MVT VT = Val.getValueType();
int Alignment = ST->getAlignment();
int SVOffset = ST->getSrcValueOffset();
@@ -581,7 +581,7 @@
else
assert(0 && "Unaligned store of unsupported type");
- SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
+ SDValue Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
SVOffset, ST->isVolatile(), Alignment);
}
@@ -595,12 +595,12 @@
int IncrementSize = NumBits / 8;
// Divide the stored value in two parts.
- SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
- SDOperand Lo = Val;
- SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
+ SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
+ SDValue Lo = Val;
+ SDValue Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
// Store the two parts
- SDOperand Store1, Store2;
+ SDValue Store1, Store2;
Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
ST->getSrcValue(), SVOffset, NewStoredVT,
ST->isVolatile(), Alignment);
@@ -616,11 +616,11 @@
/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
static
-SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
- TargetLowering &TLI) {
+SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
+ TargetLowering &TLI) {
int SVOffset = LD->getSrcValueOffset();
- SDOperand Chain = LD->getChain();
- SDOperand Ptr = LD->getBasePtr();
+ SDValue Chain = LD->getChain();
+ SDValue Ptr = LD->getBasePtr();
MVT VT = LD->getValueType(0);
MVT LoadedVT = LD->getMemoryVT();
if (VT.isFloatingPoint() || VT.isVector()) {
@@ -637,14 +637,14 @@
else
assert(0 && "Unaligned load of unsupported type");
- SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
+ SDValue newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
SVOffset, LD->isVolatile(),
LD->getAlignment());
- SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
+ SDValue Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
if (VT.isFloatingPoint() && LoadedVT != VT)
Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
- SDOperand Ops[] = { Result, Chain };
+ SDValue Ops[] = { Result, Chain };
return DAG.getMergeValues(Ops, 2);
}
assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
@@ -666,7 +666,7 @@
HiExtType = ISD::ZEXTLOAD;
// Load the value in two parts
- SDOperand Lo, Hi;
+ SDValue Lo, Hi;
if (TLI.isLittleEndian()) {
Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
@@ -686,14 +686,14 @@
}
// aggregate the two parts
- SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
- SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
+ SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
+ SDValue Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
Result = DAG.getNode(ISD::OR, VT, Result, Lo);
- SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
+ SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
Hi.getValue(1));
- SDOperand Ops[] = { Result, TF };
+ SDValue Ops[] = { Result, TF };
return DAG.getMergeValues(Ops, 2);
}
@@ -701,7 +701,7 @@
/// the operation it performs is not legal and is an operation that we have
/// no way of lowering. "Unroll" the vector, splitting out the scalars and
/// operating on each element individually.
-SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) {
+SDValue SelectionDAGLegalize::UnrollVectorOp(SDValue Op) {
MVT VT = Op.getValueType();
assert(isTypeLegal(VT) &&
"Caller should expand or promote operands that are not legal!");
@@ -710,11 +710,11 @@
unsigned NE = VT.getVectorNumElements();
MVT EltVT = VT.getVectorElementType();
- SmallVector<SDOperand, 8> Scalars;
- SmallVector<SDOperand, 4> Operands(Op.getNumOperands());
+ SmallVector<SDValue, 8> Scalars;
+ SmallVector<SDValue, 4> Operands(Op.getNumOperands());
for (unsigned i = 0; i != NE; ++i) {
for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
- SDOperand Operand = Op.getOperand(j);
+ SDValue Operand = Op.getOperand(j);
MVT OperandVT = Operand.getValueType();
if (OperandVT.isVector()) {
// A vector operand; extract a single element.
@@ -753,11 +753,11 @@
/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
/// is necessary to spill the vector being inserted into to memory, perform
/// the insert there, and then read the result back.
-SDOperand SelectionDAGLegalize::
-PerformInsertVectorEltInMemory(SDOperand Vec, SDOperand Val, SDOperand Idx) {
- SDOperand Tmp1 = Vec;
- SDOperand Tmp2 = Val;
- SDOperand Tmp3 = Idx;
+SDValue SelectionDAGLegalize::
+PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx) {
+ SDValue Tmp1 = Vec;
+ SDValue Tmp2 = Val;
+ SDValue Tmp3 = Idx;
// If the target doesn't support this, we have to spill the input vector
// to a temporary stack slot, update the element, then reload it. This is
@@ -769,12 +769,12 @@
MVT EltVT = VT.getVectorElementType();
MVT IdxVT = Tmp3.getValueType();
MVT PtrVT = TLI.getPointerTy();
- SDOperand StackPtr = DAG.CreateStackTemporary(VT);
+ SDValue StackPtr = DAG.CreateStackTemporary(VT);
int SPFI = cast<FrameIndexSDNode>(StackPtr.Val)->getIndex();
// Store the vector.
- SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
+ SDValue Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
PseudoSourceValue::getFixedStack(SPFI), 0);
// Truncate or zero extend offset to target pointer type.
@@ -783,7 +783,7 @@
// Add the offset to the index.
unsigned EltSize = EltVT.getSizeInBits()/8;
Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
- SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
+ SDValue StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
// Store the scalar value.
Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2,
PseudoSourceValue::getFixedStack(SPFI), 0, EltVT);
@@ -796,7 +796,7 @@
/// that its operands are legal. Now ensure that the operation itself
/// is legal, recursively ensuring that the operands' operations remain
/// legal.
-SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
+SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
return Op;
@@ -818,11 +818,11 @@
// Note that LegalizeOp may be reentered even from single-use nodes, which
// means that we always must cache transformed nodes.
- DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
+ DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
if (I != LegalizedNodes.end()) return I->second;
- SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
- SDOperand Result = Op;
+ SDValue Tmp1, Tmp2, Tmp3, Tmp4;
+ SDValue Result = Op;
bool isCustom = false;
switch (Node->getOpcode()) {
@@ -851,7 +851,7 @@
if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
// If this is a target node, legalize it by legalizing the operands then
// passing it through.
- SmallVector<SDOperand, 8> Ops;
+ SmallVector<SDValue, 8> Ops;
for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
Ops.push_back(LegalizeOp(Node->getOperand(i)));
@@ -922,7 +922,7 @@
if (Result.Val) break;
// Fall Thru
case TargetLowering::Legal: {
- SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
+ SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 };
Result = DAG.getMergeValues(Ops, 2);
break;
}
@@ -956,7 +956,7 @@
if (Result.Val) break;
// Fall Thru
case TargetLowering::Legal: {
- SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
+ SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 };
Result = DAG.getMergeValues(Ops, 2);
break;
}
@@ -1041,7 +1041,7 @@
case ISD::INTRINSIC_W_CHAIN:
case ISD::INTRINSIC_WO_CHAIN:
case ISD::INTRINSIC_VOID: {
- SmallVector<SDOperand, 8> Ops;
+ SmallVector<SDValue, 8> Ops;
for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
Ops.push_back(LegalizeOp(Node->getOperand(i)));
Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
@@ -1061,8 +1061,8 @@
// Since loads produce two values, make sure to remember that we
// legalized both of them.
- AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
- AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
+ AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
+ AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
return Result.getValue(Op.ResNo);
}
@@ -1087,7 +1087,7 @@
unsigned Col = DSP->getColumn();
if (useDEBUG_LOC) {
- SDOperand Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32),
+ SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32),
DAG.getConstant(Col, MVT::i32),
DAG.getConstant(SrcFile, MVT::i32) };
Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops, 4);
@@ -1105,7 +1105,7 @@
if (Action == Legal && Tmp1 == Node->getOperand(0))
break;
- SmallVector<SDOperand, 8> Ops;
+ SmallVector<SDValue, 8> Ops;
Ops.push_back(Tmp1);
if (Action == Legal) {
Ops.push_back(Node->getOperand(1)); // line # must be legal.
@@ -1201,7 +1201,7 @@
switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Legal: {
- SDOperand Ops[6];
+ SDValue Ops[6];
Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
for (int x = 1; x < 6; ++x) {
Ops[x] = Node->getOperand(x);
@@ -1222,7 +1222,7 @@
case ISD::ATOMIC_CMP_SWAP: {
unsigned int num_operands = 4;
assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
- SDOperand Ops[4];
+ SDValue Ops[4];
for (unsigned int x = 0; x < num_operands; ++x)
Ops[x] = LegalizeOp(Node->getOperand(x));
Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
@@ -1235,8 +1235,8 @@
case TargetLowering::Legal:
break;
}
- AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
- AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
+ AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
+ AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
return Result.getValue(Op.ResNo);
}
case ISD::ATOMIC_LOAD_ADD:
@@ -1252,7 +1252,7 @@
case ISD::ATOMIC_SWAP: {
unsigned int num_operands = 3;
assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
- SDOperand Ops[3];
+ SDValue Ops[3];
for (unsigned int x = 0; x < num_operands; ++x)
Ops[x] = LegalizeOp(Node->getOperand(x));
Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
@@ -1263,13 +1263,13 @@
Result = TLI.LowerOperation(Result, DAG);
break;
case TargetLowering::Expand:
- Result = SDOperand(TLI.ReplaceNodeResults(Op.Val, DAG),0);
+ Result = SDValue(TLI.ReplaceNodeResults(Op.Val, DAG),0);
break;
case TargetLowering::Legal:
break;
}
- AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
- AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
+ AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
+ AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
return Result.getValue(Op.ResNo);
}
case ISD::Constant: {
@@ -1334,7 +1334,7 @@
Tmp3 = LegalizeOp(Node->getOperand(2));
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
} else {
- SmallVector<SDOperand, 8> Ops;
+ SmallVector<SDValue, 8> Ops;
// Legalize the operands.
for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
Ops.push_back(LegalizeOp(Node->getOperand(i)));
@@ -1371,7 +1371,7 @@
Tmp1 = LegalizeOp(Tmp3.getValue(i));
if (Op.ResNo == i)
Tmp2 = Tmp1;
- AddLegalizedOperand(SDOperand(Node, i), Tmp1);
+ AddLegalizedOperand(SDValue(Node, i), Tmp1);
}
return Tmp2;
case ISD::EXTRACT_SUBREG: {
@@ -1440,7 +1440,7 @@
// match the element type of the vector being created.
if (Tmp2.getValueType() ==
Op.getValueType().getVectorElementType()) {
- SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
+ SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
Tmp1.getValueType(), Tmp2);
unsigned NumElts = Tmp1.getValueType().getVectorNumElements();
@@ -1451,14 +1451,14 @@
// We generate a shuffle of InVec and ScVec, so the shuffle mask
// should be 0,1,2,3,4,5... with the appropriate element replaced with
// elt 0 of the RHS.
- SmallVector<SDOperand, 8> ShufOps;
+ SmallVector<SDValue, 8> ShufOps;
for (unsigned i = 0; i != NumElts; ++i) {
if (i != InsertPos->getValue())
ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
else
ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
}
- SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
+ SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
&ShufOps[0], ShufOps.size());
Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
@@ -1520,11 +1520,11 @@
MVT VT = Node->getValueType(0);
MVT EltVT = VT.getVectorElementType();
MVT PtrVT = TLI.getPointerTy();
- SDOperand Mask = Node->getOperand(2);
+ SDValue Mask = Node->getOperand(2);
unsigned NumElems = Mask.getNumOperands();
- SmallVector<SDOperand,8> Ops;
+ SmallVector<SDValue,8> Ops;
for (unsigned i = 0; i != NumElems; ++i) {
- SDOperand Arg = Mask.getOperand(i);
+ SDValue Arg = Mask.getOperand(i);
if (Arg.getOpcode() == ISD::UNDEF) {
Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
} else {
@@ -1551,7 +1551,7 @@
Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
// Convert the shuffle mask to the right # elements.
- Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
+ Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0);
assert(Tmp3.Val && "Shuffle not legal?");
Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
@@ -1599,7 +1599,7 @@
// Do not try to legalize the target-specific arguments (#1+).
if (Tmp1 != Node->getOperand(0)) {
- SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
+ SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
Ops[0] = Tmp1;
Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
}
@@ -1615,7 +1615,7 @@
// can overlap.
assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
// Note that we are selecting this call!
- LastCALLSEQ_END = SDOperand(CallEnd, 0);
+ LastCALLSEQ_END = SDValue(CallEnd, 0);
IsLegalizingCall = true;
// Legalize the call, starting from the CALLSEQ_END.
@@ -1627,8 +1627,8 @@
// If the CALLSEQ_START node hasn't been legalized first, legalize it. This
// will cause this node to be legalized as well as handling libcalls right.
if (LastCALLSEQ_END.Val != Node) {
- LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
- DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
+ LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
+ DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
assert(I != LegalizedNodes.end() &&
"Legalizing the call start should have legalized this node!");
return I->second;
@@ -1641,7 +1641,7 @@
// an optional flag input.
if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
if (Tmp1 != Node->getOperand(0)) {
- SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
+ SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
Ops[0] = Tmp1;
Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
}
@@ -1649,7 +1649,7 @@
Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
if (Tmp1 != Node->getOperand(0) ||
Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
- SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
+ SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
Ops[0] = Tmp1;
Ops.back() = Tmp2;
Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
@@ -1660,9 +1660,9 @@
IsLegalizingCall = false;
// If the CALLSEQ_END node has a flag, remember that we legalized it.
- AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
+ AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
if (Node->getNumValues() == 2)
- AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
+ AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
return Result.getValue(Op.ResNo);
case ISD::DYNAMIC_STACKALLOC: {
MVT VT = Node->getValueType(0);
@@ -1679,15 +1679,15 @@
unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
" not tell us which reg is the stack pointer!");
- SDOperand Chain = Tmp1.getOperand(0);
+ SDValue Chain = Tmp1.getOperand(0);
// Chain the dynamic stack allocation so that it doesn't modify the stack
// pointer when other instructions are using the stack.
Chain = DAG.getCALLSEQ_START(Chain,
DAG.getConstant(0, TLI.getPointerTy()));
- SDOperand Size = Tmp2.getOperand(1);
- SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT);
+ SDValue Size = Tmp2.getOperand(1);
+ SDValue SP = DAG.getCopyFromReg(Chain, SPReg, VT);
Chain = SP.getValue(1);
unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue();
unsigned StackAlign =
@@ -1702,7 +1702,7 @@
DAG.getCALLSEQ_END(Chain,
DAG.getConstant(0, TLI.getPointerTy()),
DAG.getConstant(0, TLI.getPointerTy()),
- SDOperand());
+ SDValue());
Tmp1 = LegalizeOp(Tmp1);
Tmp2 = LegalizeOp(Tmp2);
@@ -1720,17 +1720,17 @@
}
// Since this op produce two values, make sure to remember that we
// legalized both of them.
- AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
- AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
+ AddLegalizedOperand(SDValue(Node, 0), Tmp1);
+ AddLegalizedOperand(SDValue(Node, 1), Tmp2);
return Op.ResNo ? Tmp2 : Tmp1;
}
case ISD::INLINEASM: {
- SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
+ SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
bool Changed = false;
// Legalize all of the operands of the inline asm, in case they are nodes
// that need to be expanded or something. Note we skip the asm string and
// all of the TargetConstant flags.
- SDOperand Op = LegalizeOp(Ops[0]);
+ SDValue Op = LegalizeOp(Ops[0]);
Changed = Op != Ops[0];
Ops[0] = Op;
@@ -1738,7 +1738,7 @@
for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
for (++i; NumVals; ++i, --NumVals) {
- SDOperand Op = LegalizeOp(Ops[i]);
+ SDValue Op = LegalizeOp(Ops[i]);
if (Op != Ops[i]) {
Changed = true;
Ops[i] = Op;
@@ -1756,8 +1756,8 @@
Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
// INLINE asm returns a chain and flag, make sure to add both to the map.
- AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
- AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
+ AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
+ AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
return Result.getValue(Op.ResNo);
}
case ISD::BR:
@@ -1802,17 +1802,17 @@
if (Tmp1.Val) Result = Tmp1;
break;
case TargetLowering::Expand: {
- SDOperand Chain = Result.getOperand(0);
- SDOperand Table = Result.getOperand(1);
- SDOperand Index = Result.getOperand(2);
+ SDValue Chain = Result.getOperand(0);
+ SDValue Table = Result.getOperand(1);
+ SDValue Index = Result.getOperand(2);
MVT PTy = TLI.getPointerTy();
MachineFunction &MF = DAG.getMachineFunction();
unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
- SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
+ SDValue Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
- SDOperand LD;
+ SDValue LD;
switch (EntrySize) {
default: assert(0 && "Size of jump table not supported yet."); break;
case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr,
@@ -1971,8 +1971,8 @@
}
// Since loads produce two values, make sure to remember that we
// legalized both of them.
- AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
- AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
+ AddLegalizedOperand(SDValue(Node, 0), Tmp3);
+ AddLegalizedOperand(SDValue(Node, 1), Tmp4);
return Op.ResNo ? Tmp4 : Tmp3;
} else {
MVT SrcVT = LD->getMemoryVT();
@@ -1995,7 +1995,7 @@
// bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
unsigned NewWidth = SrcVT.getStoreSizeInBits();
MVT NVT = MVT::getIntegerVT(NewWidth);
- SDOperand Ch;
+ SDValue Ch;
// The extra bits are guaranteed to be zero, since we stored them that
// way. A zext load from NVT thus automatically gives zext from SrcVT.
@@ -2032,7 +2032,7 @@
"Load size not an integral number of bytes!");
MVT RoundVT = MVT::getIntegerVT(RoundWidth);
MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
- SDOperand Lo, Hi, Ch;
+ SDValue Lo, Hi, Ch;
unsigned IncrementSize;
if (TLI.isLittleEndian()) {
@@ -2131,7 +2131,7 @@
case TargetLowering::Expand:
// f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
- SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
+ SDValue Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
LD->getSrcValueOffset(),
LD->isVolatile(), LD->getAlignment());
Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
@@ -2146,7 +2146,7 @@
Tmp1, Tmp2, LD->getSrcValue(),
LD->getSrcValueOffset(), SrcVT,
LD->isVolatile(), LD->getAlignment());
- SDOperand ValRes;
+ SDValue ValRes;
if (ExtType == ISD::SEXTLOAD)
ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
Result, DAG.getValueType(SrcVT));
@@ -2160,8 +2160,8 @@
// Since loads produce two values, make sure to remember that we legalized
// both of them.
- AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
- AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
+ AddLegalizedOperand(SDValue(Node, 0), Tmp1);
+ AddLegalizedOperand(SDValue(Node, 1), Tmp2);
return Op.ResNo ? Tmp2 : Tmp1;
}
}
@@ -2215,8 +2215,8 @@
// Since this produces two values, make sure to remember that we legalized
// both of them.
- AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
- AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
+ AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
+ AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
return Result;
}
break;
@@ -2239,7 +2239,7 @@
break;
case Expand:
if (!Tmp2.getValueType().isVector()) {
- SDOperand Lo, Hi;
+ SDValue Lo, Hi;
ExpandOp(Tmp2, Lo, Hi);
// Big endian systems want the hi reg first.
@@ -2279,7 +2279,7 @@
} else {
// FIXME: Returns of gcc generic vectors larger than a legal vector
// type should be returned by reference!
- SDOperand Lo, Hi;
+ SDValue Lo, Hi;
SplitVectorOp(Tmp2, Lo, Hi);
Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
Result = LegalizeOp(Result);
@@ -2297,7 +2297,7 @@
Result = DAG.UpdateNodeOperands(Result, Tmp1);
break;
default: { // ret <values>
- SmallVector<SDOperand, 8> NewValues;
+ SmallVector<SDValue, 8> NewValues;
NewValues.push_back(Tmp1);
for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
switch (getTypeAction(Node->getOperand(i).getValueType())) {
@@ -2306,7 +2306,7 @@
NewValues.push_back(Node->getOperand(i+1));
break;
case Expand: {
- SDOperand Lo, Hi;
+ SDValue Lo, Hi;
assert(!Node->getOperand(i).getValueType().isExtended() &&
"FIXME: TODO: implement returning non-legal vector types!");
ExpandOp(Node->getOperand(i), Lo, Hi);
@@ -2380,8 +2380,8 @@
// stores. If the target supports neither 32- nor 64-bits, this
// xform is certainly not worth it.
const APInt &IntVal =CFP->getValueAPF().convertToAPInt();
- SDOperand Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
- SDOperand Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
+ SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
+ SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
if (TLI.isBigEndian()) std::swap(Lo, Hi);
Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
@@ -2442,7 +2442,7 @@
case Expand:
unsigned IncrementSize = 0;
- SDOperand Lo, Hi;
+ SDValue Lo, Hi;
// If this is a vector type, then we have to calculate the increment as
// the product of the element size in bytes, and the number of elements
@@ -2546,7 +2546,7 @@
"Store size not an integral number of bytes!");
MVT RoundVT = MVT::getIntegerVT(RoundWidth);
MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
- SDOperand Lo, Hi;
+ SDValue Lo, Hi;
unsigned IncrementSize;
if (TLI.isLittleEndian()) {
@@ -2655,8 +2655,8 @@
// Since stacksave produce two values, make sure to remember that we
// legalized both of them.
- AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
- AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
+ AddLegalizedOperand(SDValue(Node, 0), Tmp1);
+ AddLegalizedOperand(SDValue(Node, 1), Tmp2);
return Op.ResNo ? Tmp2 : Tmp1;
case ISD::STACKRESTORE:
@@ -2702,8 +2702,8 @@
// Since rdcc produce two values, make sure to remember that we legalized
// both of them.
- AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
- AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
+ AddLegalizedOperand(SDValue(Node, 0), Tmp1);
+ AddLegalizedOperand(SDValue(Node, 1), Tmp2);
return Result;
case ISD::SELECT:
@@ -2779,7 +2779,7 @@
Tmp2 = Node->getOperand(1); // RHS
Tmp3 = LegalizeOp(Node->getOperand(2)); // True
Tmp4 = LegalizeOp(Node->getOperand(3)); // False
- SDOperand CC = Node->getOperand(4);
+ SDValue CC = Node->getOperand(4);
LegalizeSetCCOperands(Tmp1, Tmp2, CC);
@@ -2874,7 +2874,7 @@
case ISD::VSETCC: {
Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
- SDOperand CC = Node->getOperand(2);
+ SDValue CC = Node->getOperand(2);
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC);
@@ -2893,7 +2893,7 @@
case ISD::SHL_PARTS:
case ISD::SRA_PARTS:
case ISD::SRL_PARTS: {
- SmallVector<SDOperand, 8> Ops;
+ SmallVector<SDValue, 8> Ops;
bool Changed = false;
for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
Ops.push_back(LegalizeOp(Node->getOperand(i)));
@@ -2909,10 +2909,10 @@
case TargetLowering::Custom:
Tmp1 = TLI.LowerOperation(Result, DAG);
if (Tmp1.Val) {
- SDOperand Tmp2, RetVal(0, 0);
+ SDValue Tmp2, RetVal(0, 0);
for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
Tmp2 = LegalizeOp(Tmp1.getValue(i));
- AddLegalizedOperand(SDOperand(Node, i), Tmp2);
+ AddLegalizedOperand(SDValue(Node, i), Tmp2);
if (i == Op.ResNo)
RetVal = Tmp2;
}
@@ -2925,7 +2925,7 @@
// Since these produce multiple values, make sure to remember that we
// legalized all of them.
for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
- AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
+ AddLegalizedOperand(SDValue(Node, i), Result.getValue(i));
return Result.getValue(Op.ResNo);
}
@@ -2993,28 +2993,28 @@
OpToUse = ISD::UMUL_LOHI;
}
if (OpToUse) {
- Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0);
+ Result = SDValue(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0);
break;
}
}
if (Node->getOpcode() == ISD::MULHS &&
TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
- Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
+ Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
break;
}
if (Node->getOpcode() == ISD::MULHU &&
TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
- Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
+ Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
break;
}
if (Node->getOpcode() == ISD::SDIV &&
TLI.isOperationLegal(ISD::SDIVREM, VT)) {
- Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0);
+ Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0);
break;
}
if (Node->getOpcode() == ISD::UDIV &&
TLI.isOperationLegal(ISD::UDIVREM, VT)) {
- Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0);
+ Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0);
break;
}
@@ -3037,7 +3037,7 @@
default: break;
}
if (LC != RTLIB::UNKNOWN_LIBCALL) {
- SDOperand Dummy;
+ SDValue Dummy;
Result = ExpandLibCall(LC, Node, isSigned, Dummy);
break;
}
@@ -3116,11 +3116,11 @@
// Get the sign bit of the RHS.
MVT IVT =
Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
- SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
+ SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit),
SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
// Get the absolute value of the result.
- SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
+ SDValue AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
// Select between the nabs and abs value based on the sign bit of
// the input.
Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
@@ -3149,8 +3149,8 @@
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
// Since this produces two values, make sure to remember that we legalized
// both of them.
- AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
- AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
+ AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
+ AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
return Result;
case ISD::ADDE:
@@ -3161,8 +3161,8 @@
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
// Since this produces two values, make sure to remember that we legalized
// both of them.
- AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
- AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
+ AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
+ AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
return Result;
case ISD::BUILD_PAIR: {
@@ -3217,12 +3217,12 @@
SDVTList VTs = DAG.getVTList(VT, VT);
if (Node->getOpcode() == ISD::SREM &&
TLI.isOperationLegal(ISD::SDIVREM, VT)) {
- Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1);
+ Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1);
break;
}
if (Node->getOpcode() == ISD::UREM &&
TLI.isOperationLegal(ISD::UDIVREM, VT)) {
- Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1);
+ Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1);
break;
}
@@ -3240,7 +3240,7 @@
"Cannot expand this binary operator!");
RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
? RTLIB::UREM_I32 : RTLIB::SREM_I32;
- SDOperand Dummy;
+ SDValue Dummy;
Result = ExpandLibCall(LC, Node, isSigned, Dummy);
}
} else {
@@ -3252,7 +3252,7 @@
// Floating point mod -> fmod libcall.
RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
RTLIB::REM_F80, RTLIB::REM_PPCF128);
- SDOperand Dummy;
+ SDValue Dummy;
Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
}
}
@@ -3285,7 +3285,7 @@
break;
case TargetLowering::Expand: {
const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
- SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
+ SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
// Increment the pointer, VAList, to the next vaarg
Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
DAG.getConstant(VT.getSizeInBits()/8,
@@ -3301,8 +3301,8 @@
}
// Since VAARG produces two values, make sure to remember that we
// legalized both of them.
- AddLegalizedOperand(SDOperand(Node, 0), Result);
- AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
+ AddLegalizedOperand(SDValue(Node, 0), Result);
+ AddLegalizedOperand(SDValue(Node, 1), Tmp1);
return Op.ResNo ? Tmp1 : Result;
}
@@ -3537,7 +3537,7 @@
break;
default: assert(0 && "Unreachable!");
}
- SDOperand Dummy;
+ SDValue Dummy;
Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
break;
}
@@ -3557,7 +3557,7 @@
// We always lower FPOWI into a libcall. No target support for it yet.
RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
- SDOperand Dummy;
+ SDValue Dummy;
Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
break;
}
@@ -3701,7 +3701,7 @@
break;
case TargetLowering::Expand:
if (Node->getOpcode() == ISD::FP_TO_UINT) {
- SDOperand True, False;
+ SDValue True, False;
MVT VT = Node->getOperand(0).getValueType();
MVT NVT = Node->getValueType(0);
const uint64_t zero[] = {0, 0};
@@ -3758,7 +3758,7 @@
RTLIB::Libcall LC = (Node->getOpcode() == ISD::FP_TO_SINT) ?
RTLIB::getFPTOSINT(OVT, VT) : RTLIB::getFPTOUINT(OVT, VT);
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!");
- SDOperand Dummy;
+ SDValue Dummy;
Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
break;
}
@@ -3797,7 +3797,7 @@
MVT SrcVT = Op.getOperand(0).getValueType();
if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
if (SrcVT == MVT::ppcf128) {
- SDOperand Lo;
+ SDValue Lo;
ExpandOp(Node->getOperand(0), Lo, Result);
// Round it the rest of the way (e.g. to f32) if needed.
if (DstVT!=MVT::f64)
@@ -3878,7 +3878,7 @@
// SAR. However, it is doubtful that any exist.
unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
ExtraVT.getSizeInBits();
- SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
+ SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
Node->getOperand(0), ShiftCst);
Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
@@ -3900,7 +3900,7 @@
break;
}
case ISD::TRAMPOLINE: {
- SDOperand Ops[6];
+ SDValue Ops[6];
for (unsigned i = 0; i != 6; ++i)
Ops[i] = LegalizeOp(Node->getOperand(i));
Result = DAG.UpdateNodeOperands(Result, Ops, 6);
@@ -3912,8 +3912,8 @@
// legalized both of them.
Tmp1 = LegalizeOp(Result.getValue(1));
Result = LegalizeOp(Result);
- AddLegalizedOperand(SDOperand(Node, 0), Result);
- AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
+ AddLegalizedOperand(SDValue(Node, 0), Result);
+ AddLegalizedOperand(SDValue(Node, 1), Tmp1);
return Op.ResNo ? Tmp1 : Result;
}
case ISD::FLT_ROUNDS_: {
@@ -3947,7 +3947,7 @@
// If this operation is not supported, lower it to 'abort()' call
Tmp1 = LegalizeOp(Node->getOperand(0));
TargetLowering::ArgListTy Args;
- std::pair<SDOperand,SDOperand> CallResult =
+ std::pair<SDValue,SDValue> CallResult =
TLI.LowerCallTo(Tmp1, Type::VoidTy,
false, false, false, CallingConv::C, false,
DAG.getExternalSymbol("abort", TLI.getPointerTy()),
@@ -3976,7 +3976,7 @@
/// promote it to compute the value into a larger type. The produced value will
/// have the correct bits for the low portion of the register, but no guarantee
/// is made about the top bits: it may be zero, sign-extended, or garbage.
-SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
+SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
MVT VT = Op.getValueType();
MVT NVT = TLI.getTypeToTransformTo(VT);
assert(getTypeAction(VT) == Promote &&
@@ -3984,11 +3984,11 @@
assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() &&
"Cannot promote to smaller type!");
- SDOperand Tmp1, Tmp2, Tmp3;
- SDOperand Result;
+ SDValue Tmp1, Tmp2, Tmp3;
+ SDValue Result;
SDNode *Node = Op.Val;
- DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
+ DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op);
if (I != PromotedNodes.end()) return I->second;
switch (Node->getOpcode()) {
@@ -4331,7 +4331,7 @@
Result = TLI.LowerOperation(Tmp3, DAG);
} else {
const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
- SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
+ SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
// Increment the pointer, VAList, to the next vaarg
Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
DAG.getConstant(VT.getSizeInBits()/8,
@@ -4436,12 +4436,12 @@
/// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
/// based on the vector type. The return type of this matches the element type
/// of the vector, which may not be legal for the target.
-SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
+SDValue SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDValue Op) {
// We know that operand #0 is the Vec vector. If the index is a constant
// or if the invec is a supported hardware type, we can use it. Otherwise,
// lower to a store then an indexed load.
- SDOperand Vec = Op.getOperand(0);
- SDOperand Idx = Op.getOperand(1);
+ SDValue Vec = Op.getOperand(0);
+ SDValue Idx = Op.getOperand(1);
MVT TVT = Vec.getValueType();
unsigned NumElems = TVT.getVectorNumElements();
@@ -4451,7 +4451,7 @@
case TargetLowering::Custom: {
Vec = LegalizeOp(Vec);
Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
- SDOperand Tmp3 = TLI.LowerOperation(Op, DAG);
+ SDValue Tmp3 = TLI.LowerOperation(Op, DAG);
if (Tmp3.Val)
return Tmp3;
break;
@@ -4473,7 +4473,7 @@
} else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
unsigned NumLoElts = 1 << Log2_32(NumElems-1);
ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
- SDOperand Lo, Hi;
+ SDValue Lo, Hi;
SplitVectorOp(Vec, Lo, Hi);
if (CIdx->getValue() < NumLoElts) {
Vec = Lo;
@@ -4489,8 +4489,8 @@
} else {
// Store the value to a temporary stack slot, then LOAD the scalar
// element back out.
- SDOperand StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
- SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
+ SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
+ SDValue Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
// Add the offset to the index.
unsigned EltSize = Op.getValueType().getSizeInBits()/8;
@@ -4511,11 +4511,11 @@
/// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
/// we assume the operation can be split if it is not already legal.
-SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) {
+SDValue SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDValue Op) {
// We know that operand #0 is the Vec vector. For now we assume the index
// is a constant and that the extracted result is a supported hardware type.
- SDOperand Vec = Op.getOperand(0);
- SDOperand Idx = LegalizeOp(Op.getOperand(1));
+ SDValue Vec = Op.getOperand(0);
+ SDValue Idx = LegalizeOp(Op.getOperand(1));
unsigned NumElems = Vec.getValueType().getVectorNumElements();
@@ -4525,7 +4525,7 @@
}
ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
- SDOperand Lo, Hi;
+ SDValue Lo, Hi;
SplitVectorOp(Vec, Lo, Hi);
if (CIdx->getValue() < NumElems/2) {
Vec = Lo;
@@ -4544,11 +4544,11 @@
/// or promoting the arguments. In the case where LHS and RHS must be expanded,
/// there may be no choice but to create a new SetCC node to represent the
/// legalized value of setcc lhs, rhs. In this case, the value is returned in
-/// LHS, and the SDOperand returned in RHS has a nil SDNode value.
-void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
- SDOperand &RHS,
- SDOperand &CC) {
- SDOperand Tmp1, Tmp2, Tmp3, Result;
+/// LHS, and the SDValue returned in RHS has a nil SDNode value.
+void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
+ SDValue &RHS,
+ SDValue &CC) {
+ SDValue Tmp1, Tmp2, Tmp3, Result;
switch (getTypeAction(LHS.getValueType())) {
case Legal:
@@ -4656,8 +4656,8 @@
}
}
- SDOperand Dummy;
- SDOperand Ops[2] = { LHS, RHS };
+ SDValue Dummy;
+ SDValue Ops[2] = { LHS, RHS };
Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).Val,
false /*sign irrelevant*/, Dummy);
Tmp2 = DAG.getConstant(0, MVT::i32);
@@ -4670,14 +4670,14 @@
Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2,
DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
- Tmp2 = SDOperand();
+ Tmp2 = SDValue();
}
LHS = LegalizeOp(Tmp1);
RHS = Tmp2;
return;
}
- SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
+ SDValue LHSLo, LHSHi, RHSLo, RHSHi;
ExpandOp(LHS, LHSLo, LHSHi);
ExpandOp(RHS, RHSLo, RHSHi);
ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
@@ -4695,7 +4695,7 @@
Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode);
Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
- Tmp2 = SDOperand();
+ Tmp2 = SDValue();
break;
}
@@ -4773,7 +4773,7 @@
// For LE / GE, if high part is known false, ignore the low part.
// For LT / GT, if high part is known true, ignore the low part.
Tmp1 = Tmp2;
- Tmp2 = SDOperand();
+ Tmp2 = SDValue();
} else {
Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
ISD::SETEQ, false, DagCombineInfo);
@@ -4783,7 +4783,7 @@
Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
Result, Tmp1, Tmp2));
Tmp1 = Result;
- Tmp2 = SDOperand();
+ Tmp2 = SDValue();
}
}
}
@@ -4796,13 +4796,13 @@
/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
/// a load from the stack slot to DestVT, extending it if needed.
/// The resultant code need not be legal.
-SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp,
- MVT SlotVT,
- MVT DestVT) {
+SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
+ MVT SlotVT,
+ MVT DestVT) {
// Create the stack frame object.
unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment(
SrcOp.getValueType().getTypeForMVT());
- SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
+ SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
int SPFI = StackPtrFI->getIndex();
@@ -4815,7 +4815,7 @@
// Emit a store to the stack slot. Use a truncstore if the input value is
// later than DestVT.
- SDOperand Store;
+ SDValue Store;
if (SrcSize > SlotSize)
Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr,
@@ -4837,15 +4837,15 @@
false, DestAlign);
}
-SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
+SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
// Create a vector sized/aligned stack slot, store the value to element #0,
// then load the whole vector back out.
- SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
+ SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
int SPFI = StackPtrFI->getIndex();
- SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
+ SDValue Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
PseudoSourceValue::getFixedStack(SPFI), 0);
return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,
PseudoSourceValue::getFixedStack(SPFI), 0);
@@ -4854,17 +4854,17 @@
/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
/// support the operation, but do support the resultant vector type.
-SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
+SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
// If the only non-undef value is the low element, turn this into a
// SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
unsigned NumElems = Node->getNumOperands();
bool isOnlyLowElement = true;
- SDOperand SplatValue = Node->getOperand(0);
+ SDValue SplatValue = Node->getOperand(0);
- // FIXME: it would be far nicer to change this into map<SDOperand,uint64_t>
+ // FIXME: it would be far nicer to change this into map<SDValue,uint64_t>
// and use a bitmask instead of a list of elements.
- std::map<SDOperand, std::vector<unsigned> > Values;
+ std::map<SDValue, std::vector<unsigned> > Values;
Values[SplatValue].push_back(0);
bool isConstant = true;
if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
@@ -4872,12 +4872,12 @@
isConstant = false;
for (unsigned i = 1; i < NumElems; ++i) {
- SDOperand V = Node->getOperand(i);
+ SDValue V = Node->getOperand(i);
Values[V].push_back(i);
if (V.getOpcode() != ISD::UNDEF)
isOnlyLowElement = false;
if (SplatValue != V)
- SplatValue = SDOperand(0,0);
+ SplatValue = SDValue(0,0);
// If this isn't a constant element or an undef, we can't use a constant
// pool load.
@@ -4914,7 +4914,7 @@
}
}
Constant *CP = ConstantVector::get(CV);
- SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
+ SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
PseudoSourceValue::getConstantPool(), 0);
}
@@ -4922,15 +4922,15 @@
if (SplatValue.Val) { // Splat of one value?
// Build the shuffle constant vector: <0, 0, 0, 0>
MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
- SDOperand Zero = DAG.getConstant(0, MaskVT.getVectorElementType());
- std::vector<SDOperand> ZeroVec(NumElems, Zero);
- SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
+ SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType());
+ std::vector<SDValue> ZeroVec(NumElems, Zero);
+ SDValue SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
&ZeroVec[0], ZeroVec.size());
// If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
// Get the splatted value into the low element of a vector register.
- SDOperand LowValVec =
+ SDValue LowValVec =
DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
// Return shuffle(LowValVec, undef, <0,0,0,0>)
@@ -4944,9 +4944,9 @@
// vector shuffle.
if (Values.size() == 2) {
// Get the two values in deterministic order.
- SDOperand Val1 = Node->getOperand(1);
- SDOperand Val2;
- std::map<SDOperand, std::vector<unsigned> >::iterator MI = Values.begin();
+ SDValue Val1 = Node->getOperand(1);
+ SDValue Val2;
+ std::map<SDValue, std::vector<unsigned> >::iterator MI = Values.begin();
if (MI->first != Val1)
Val2 = MI->first;
else
@@ -4960,7 +4960,7 @@
// Build the shuffle constant vector: e.g. <0, 4, 0, 4>
MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
MVT MaskEltVT = MaskVT.getVectorElementType();
- std::vector<SDOperand> MaskVec(NumElems);
+ std::vector<SDValue> MaskVec(NumElems);
// Set elements of the shuffle mask for Val1.
std::vector<unsigned> &Val1Elts = Values[Val1];
@@ -4975,7 +4975,7 @@
else
MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT);
- SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
+ SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
&MaskVec[0], MaskVec.size());
// If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
@@ -4983,7 +4983,7 @@
isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1);
Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2);
- SDOperand Ops[] = { Val1, Val2, ShuffleMask };
+ SDValue Ops[] = { Val1, Val2, ShuffleMask };
// Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3);
@@ -4995,10 +4995,10 @@
// the result as a vector.
MVT VT = Node->getValueType(0);
// Create the stack frame object.
- SDOperand FIPtr = DAG.CreateStackTemporary(VT);
+ SDValue FIPtr = DAG.CreateStackTemporary(VT);
// Emit a store of each element to the stack slot.
- SmallVector<SDOperand, 8> Stores;
+ SmallVector<SDValue, 8> Stores;
unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8;
// Store (in the right endianness) the elements to memory.
for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
@@ -5007,14 +5007,14 @@
unsigned Offset = TypeByteSize*i;
- SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
+ SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
NULL, 0));
}
- SDOperand StoreChain;
+ SDValue StoreChain;
if (!Stores.empty()) // Not all undef elements?
StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
&Stores[0], Stores.size());
@@ -5026,13 +5026,13 @@
}
void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
- SDOperand Op, SDOperand Amt,
- SDOperand &Lo, SDOperand &Hi) {
+ SDValue Op, SDValue Amt,
+ SDValue &Lo, SDValue &Hi) {
// Expand the subcomponents.
- SDOperand LHSL, LHSH;
+ SDValue LHSL, LHSH;
ExpandOp(Op, LHSL, LHSH);
- SDOperand Ops[] = { LHSL, LHSH, Amt };
+ SDValue Ops[] = { LHSL, LHSH, Amt };
MVT VT = LHSL.getValueType();
Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
Hi = Lo.getValue(1);
@@ -5043,13 +5043,13 @@
/// smaller elements. If we can't find a way that is more efficient than a
/// libcall on this target, return false. Otherwise, return true with the
/// low-parts expanded into Lo and Hi.
-bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
- SDOperand &Lo, SDOperand &Hi) {
+bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt,
+ SDValue &Lo, SDValue &Hi) {
assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
"This is not a shift!");
MVT NVT = TLI.getTypeToTransformTo(Op.getValueType());
- SDOperand ShAmt = LegalizeOp(Amt);
+ SDValue ShAmt = LegalizeOp(Amt);
MVT ShTy = ShAmt.getValueType();
unsigned ShBits = ShTy.getSizeInBits();
unsigned VTBits = Op.getValueType().getSizeInBits();
@@ -5059,7 +5059,7 @@
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
unsigned Cst = CN->getValue();
// Expand the incoming operand to be shifted, so that we have its parts
- SDOperand InL, InH;
+ SDValue InL, InH;
ExpandOp(Op, InL, InH);
switch(Opc) {
case ISD::SHL:
@@ -5133,7 +5133,7 @@
DAG.getConstant(~Mask, Amt.getValueType()));
// Expand the incoming operand to be shifted, so that we have its parts
- SDOperand InL, InH;
+ SDValue InL, InH;
ExpandOp(Op, InL, InH);
switch(Opc) {
case ISD::SHL:
@@ -5156,12 +5156,12 @@
// do this as a couple of simple shifts.
if ((KnownZero & Mask) == Mask) {
// Compute 32-amt.
- SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
+ SDValue Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
DAG.getConstant(NVTBits, Amt.getValueType()),
Amt);
// Expand the incoming operand to be shifted, so that we have its parts
- SDOperand InL, InH;
+ SDValue InL, InH;
ExpandOp(Op, InL, InH);
switch(Opc) {
case ISD::SHL:
@@ -5193,13 +5193,13 @@
// does not fit into a register, return the lo part and set the hi part to the
// by-reg argument. If it does fit into a single register, return the result
// and leave the Hi part unset.
-SDOperand SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
- bool isSigned, SDOperand &Hi) {
+SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
+ bool isSigned, SDValue &Hi) {
assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
// The input chain to this libcall is the entry node of the function.
// Legalizing the call will automatically add the previous call to the
// dependence.
- SDOperand InChain = DAG.getEntryNode();
+ SDValue InChain = DAG.getEntryNode();
TargetLowering::ArgListTy Args;
TargetLowering::ArgListEntry Entry;
@@ -5211,12 +5211,12 @@
Entry.isZExt = !isSigned;
Args.push_back(Entry);
}
- SDOperand Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
+ SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
TLI.getPointerTy());
// Splice the libcall in wherever FindInputOutputChains tells us to.
const Type *RetTy = Node->getValueType(0).getTypeForMVT();
- std::pair<SDOperand,SDOperand> CallInfo =
+ std::pair<SDValue,SDValue> CallInfo =
TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, CallingConv::C,
false, Callee, Args, DAG);
@@ -5224,7 +5224,7 @@
// the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
// was added by LowerCallTo (guaranteeing proper serialization of calls).
LegalizeOp(CallInfo.second);
- SDOperand Result;
+ SDValue Result;
switch (getTypeAction(CallInfo.first.getValueType())) {
default: assert(0 && "Unknown thing");
case Legal:
@@ -5240,8 +5240,8 @@
/// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
///
-SDOperand SelectionDAGLegalize::
-ExpandIntToFP(bool isSigned, MVT DestTy, SDOperand Source) {
+SDValue SelectionDAGLegalize::
+ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source) {
MVT SourceVT = Source.getValueType();
bool ExpandSource = getTypeAction(SourceVT) == Expand;
@@ -5250,9 +5250,9 @@
// The integer value loaded will be incorrectly if the 'sign bit' of the
// incoming integer is set. To handle this, we dynamically test to see if
// it is set, and, if so, add a fudge factor.
- SDOperand Hi;
+ SDValue Hi;
if (ExpandSource) {
- SDOperand Lo;
+ SDValue Lo;
ExpandOp(Source, Lo, Hi);
Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi);
} else {
@@ -5262,21 +5262,21 @@
// If this is unsigned, and not supported, first perform the conversion to
// signed, then adjust the result if the sign bit is set.
- SDOperand SignedConv = ExpandIntToFP(true, DestTy, Source);
+ SDValue SignedConv = ExpandIntToFP(true, DestTy, Source);
- SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
+ SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
DAG.getConstant(0, Hi.getValueType()),
ISD::SETLT);
- SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
- SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
+ SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
+ SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
SignSet, Four, Zero);
uint64_t FF = 0x5f800000ULL;
if (TLI.isLittleEndian()) FF <<= 32;
static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
- SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
+ SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
- SDOperand FudgeInReg;
+ SDValue FudgeInReg;
if (DestTy == MVT::f32)
FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
PseudoSourceValue::getConstantPool(), 0);
@@ -5310,7 +5310,7 @@
case TargetLowering::Expand:
break; // This case is handled below.
case TargetLowering::Custom: {
- SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
+ SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
Source), DAG);
if (NV.Val)
return LegalizeOp(NV);
@@ -5321,7 +5321,7 @@
// Expand the source, then glue it back together for the call. We must expand
// the source in case it is shared (this pass of legalize must traverse it).
if (ExpandSource) {
- SDOperand SrcLo, SrcHi;
+ SDValue SrcLo, SrcHi;
ExpandOp(Source, SrcLo, SrcHi);
Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi);
}
@@ -5332,8 +5332,8 @@
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unknown int value type");
Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
- SDOperand HiPart;
- SDOperand Result = ExpandLibCall(LC, Source.Val, isSigned, HiPart);
+ SDValue HiPart;
+ SDValue Result = ExpandLibCall(LC, Source.Val, isSigned, HiPart);
if (Result.getValueType() != DestTy && HiPart.Val)
Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart);
return Result;
@@ -5343,50 +5343,50 @@
/// INT_TO_FP operation of the specified operand when the target requests that
/// we expand it. At this point, we know that the result and operand types are
/// legal for the target.
-SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
- SDOperand Op0,
- MVT DestVT) {
+SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
+ SDValue Op0,
+ MVT DestVT) {
if (Op0.getValueType() == MVT::i32) {
// simple 32-bit [signed|unsigned] integer to float/double expansion
// Get the stack frame index of a 8 byte buffer.
- SDOperand StackSlot = DAG.CreateStackTemporary(MVT::f64);
+ SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
// word offset constant for Hi/Lo address computation
- SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
+ SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
// set up Hi and Lo (into buffer) address based on endian
- SDOperand Hi = StackSlot;
- SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
+ SDValue Hi = StackSlot;
+ SDValue Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
if (TLI.isLittleEndian())
std::swap(Hi, Lo);
// if signed map to unsigned space
- SDOperand Op0Mapped;
+ SDValue Op0Mapped;
if (isSigned) {
// constant used to invert sign bit (signed to unsigned mapping)
- SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
+ SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
} else {
Op0Mapped = Op0;
}
// store the lo of the constructed double - based on integer input
- SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
+ SDValue Store1 = DAG.getStore(DAG.getEntryNode(),
Op0Mapped, Lo, NULL, 0);
// initial hi portion of constructed double
- SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
+ SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
// store the hi of the constructed double - biased exponent
- SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
+ SDValue Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
// load the constructed double
- SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
+ SDValue Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
// FP constant to bias correct the final result
- SDOperand Bias = DAG.getConstantFP(isSigned ?
+ SDValue Bias = DAG.getConstantFP(isSigned ?
BitsToDouble(0x4330000080000000ULL)
: BitsToDouble(0x4330000000000000ULL),
MVT::f64);
// subtract the bias
- SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
+ SDValue Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
// final result
- SDOperand Result;
+ SDValue Result;
// handle final rounding
if (DestVT == MVT::f64) {
// do nothing
@@ -5400,13 +5400,13 @@
return Result;
}
assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
- SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
+ SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
- SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0,
+ SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0,
DAG.getConstant(0, Op0.getValueType()),
ISD::SETLT);
- SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
- SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
+ SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
+ SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
SignSet, Four, Zero);
// If the sign bit of the integer is set, the large number will be treated
@@ -5423,9 +5423,9 @@
if (TLI.isLittleEndian()) FF <<= 32;
static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
- SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
+ SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
- SDOperand FudgeInReg;
+ SDValue FudgeInReg;
if (DestVT == MVT::f32)
FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
PseudoSourceValue::getConstantPool(), 0);
@@ -5445,9 +5445,9 @@
/// we promote it. At this point, we know that the result and operand types are
/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
/// operation that takes a larger input.
-SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
- MVT DestVT,
- bool isSigned) {
+SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
+ MVT DestVT,
+ bool isSigned) {
// First step, figure out the appropriate *INT_TO_FP operation to use.
MVT NewInTy = LegalOp.getValueType();
@@ -5500,9 +5500,9 @@
/// we promote it. At this point, we know that the result and operand types are
/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
/// operation that returns a larger result.
-SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
- MVT DestVT,
- bool isSigned) {
+SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
+ MVT DestVT,
+ bool isSigned) {
// First step, figure out the appropriate FP_TO*INT operation to use.
MVT NewOutTy = DestVT;
@@ -5544,13 +5544,13 @@
// Okay, we found the operation and type to use.
- SDOperand Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
+ SDValue Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
// If the operation produces an invalid type, it must be custom lowered. Use
// the target lowering hooks to expand it. Just keep the low part of the
// expanded operation, we know that we're truncating anyway.
if (getTypeAction(NewOutTy) == Expand) {
- Operation = SDOperand(TLI.ReplaceNodeResults(Operation.Val, DAG), 0);
+ Operation = SDValue(TLI.ReplaceNodeResults(Operation.Val, DAG), 0);
assert(Operation.Val && "Didn't return anything");
}
@@ -5561,10 +5561,10 @@
/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
///
-SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
+SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op) {
MVT VT = Op.getValueType();
MVT SHVT = TLI.getShiftAmountTy();
- SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
+ SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
switch (VT.getSimpleVT()) {
default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
case MVT::i16:
@@ -5608,7 +5608,7 @@
/// ExpandBitCount - Expand the specified bitcount instruction into operations.
///
-SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
+SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op) {
switch (Opc) {
default: assert(0 && "Cannot expand this yet!");
case ISD::CTPOP: {
@@ -5622,8 +5622,8 @@
unsigned len = VT.getSizeInBits();
for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
//x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
- SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
- SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
+ SDValue Tmp2 = DAG.getConstant(mask[i], VT);
+ SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
DAG.getNode(ISD::AND, VT,
DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
@@ -5644,7 +5644,7 @@
MVT ShVT = TLI.getShiftAmountTy();
unsigned len = VT.getSizeInBits();
for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
- SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
+ SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
}
Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
@@ -5656,8 +5656,8 @@
// { return 32 - nlz(~x & (x-1)); }
// see also http://www.hackersdelight.org/HDcode/ntz.cc
MVT VT = Op.getValueType();
- SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
- SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
+ SDValue Tmp2 = DAG.getConstant(~0ULL, VT);
+ SDValue Tmp3 = DAG.getNode(ISD::AND, VT,
DAG.getNode(ISD::XOR, VT, Op, Tmp2),
DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
// If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
@@ -5671,12 +5671,12 @@
}
}
-/// ExpandOp - Expand the specified SDOperand into its two component pieces
+/// ExpandOp - Expand the specified SDValue into its two component pieces
/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
/// LegalizeNodes map is filled in for any results that are not expanded, the
/// ExpandedNodes map is filled in for any results that are expanded, and the
/// Lo/Hi values are returned.
-void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
+void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
MVT VT = Op.getValueType();
MVT NVT = TLI.getTypeToTransformTo(VT);
SDNode *Node = Op.Val;
@@ -5685,7 +5685,7 @@
VT.isVector()) && "Cannot expand to FP value or to larger int value!");
// See if we already expanded it.
- DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
+ DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator I
= ExpandedNodes.find(Op);
if (I != ExpandedNodes.end()) {
Lo = I->second.first;
@@ -5700,10 +5700,10 @@
if (VT == MVT::ppcf128 &&
TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
TargetLowering::Custom) {
- SDOperand SrcLo, SrcHi, Src;
+ SDValue SrcLo, SrcHi, Src;
ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
- SDOperand Result = TLI.LowerOperation(
+ SDValue Result = TLI.LowerOperation(
DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
assert(Result.Val->getOpcode() == ISD::BUILD_PAIR);
Lo = Result.Val->getOperand(0);
@@ -5787,7 +5787,7 @@
case ISD::BSWAP: {
ExpandOp(Node->getOperand(0), Lo, Hi);
- SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
+ SDValue TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
Lo = TempLo;
break;
@@ -5804,11 +5804,11 @@
case ISD::CTLZ: {
// ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
ExpandOp(Node->getOperand(0), Lo, Hi);
- SDOperand BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
- SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
- SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC,
+ SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
+ SDValue HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
+ SDValue TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC,
ISD::SETNE);
- SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
+ SDValue LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
@@ -5819,11 +5819,11 @@
case ISD::CTTZ: {
// cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
ExpandOp(Node->getOperand(0), Lo, Hi);
- SDOperand BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
- SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
- SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC,
+ SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
+ SDValue LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
+ SDValue BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC,
ISD::SETNE);
- SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
+ SDValue HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
@@ -5832,8 +5832,8 @@
}
case ISD::VAARG: {
- SDOperand Ch = Node->getOperand(0); // Legalize the chain.
- SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
+ SDValue Ch = Node->getOperand(0); // Legalize the chain.
+ SDValue Ptr = Node->getOperand(1); // Legalize the pointer.
Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
@@ -5847,8 +5847,8 @@
case ISD::LOAD: {
LoadSDNode *LD = cast<LoadSDNode>(Node);
- SDOperand Ch = LD->getChain(); // Legalize the chain.
- SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
+ SDValue Ch = LD->getChain(); // Legalize the chain.
+ SDValue Ptr = LD->getBasePtr(); // Legalize the pointer.
ISD::LoadExtType ExtType = LD->getExtensionType();
int SVOffset = LD->getSrcValueOffset();
unsigned Alignment = LD->getAlignment();
@@ -5860,7 +5860,7 @@
if (VT == MVT::f32 || VT == MVT::f64) {
// f32->i32 or f64->i64 one to one expansion.
// Remember that we legalized the chain.
- AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
+ AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
// Recursively expand the new load.
if (getTypeAction(NVT) == Expand)
ExpandOp(Lo, Lo, Hi);
@@ -5878,7 +5878,7 @@
// Build a factor node to remember that this load is independent of the
// other one.
- SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
+ SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
Hi.getValue(1));
// Remember that we legalized the chain.
@@ -5891,10 +5891,10 @@
if ((VT == MVT::f64 && EVT == MVT::f32) ||
(VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
// f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
- SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
+ SDValue Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
SVOffset, isVolatile, Alignment);
// Remember that we legalized the chain.
- AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
+ AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Load.getValue(1)));
ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
break;
}
@@ -5908,7 +5908,7 @@
Alignment);
// Remember that we legalized the chain.
- AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
+ AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
if (ExtType == ISD::SEXTLOAD) {
// The high part is obtained by SRA'ing all but one of the bits of the
@@ -5929,7 +5929,7 @@
case ISD::AND:
case ISD::OR:
case ISD::XOR: { // Simple logical operators -> two trivial pieces.
- SDOperand LL, LH, RL, RH;
+ SDValue LL, LH, RL, RH;
ExpandOp(Node->getOperand(0), LL, LH);
ExpandOp(Node->getOperand(1), RL, RH);
Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
@@ -5937,7 +5937,7 @@
break;
}
case ISD::SELECT: {
- SDOperand LL, LH, RL, RH;
+ SDValue LL, LH, RL, RH;
ExpandOp(Node->getOperand(1), LL, LH);
ExpandOp(Node->getOperand(2), RL, RH);
if (getTypeAction(NVT) == Expand)
@@ -5948,7 +5948,7 @@
break;
}
case ISD::SELECT_CC: {
- SDOperand TL, TH, FL, FH;
+ SDValue TL, TH, FL, FH;
ExpandOp(Node->getOperand(2), TL, TH);
ExpandOp(Node->getOperand(3), FL, FH);
if (getTypeAction(NVT) == Expand)
@@ -5989,7 +5989,7 @@
case ISD::TRUNCATE: {
// The input value must be larger than this value. Expand *it*.
- SDOperand NewLo;
+ SDValue NewLo;
ExpandOp(Node->getOperand(0), NewLo, Hi);
// The low part is now either the right size, or it is closer. If not the
@@ -6001,7 +6001,7 @@
}
case ISD::BIT_CONVERT: {
- SDOperand Tmp;
+ SDValue Tmp;
if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
// If the target wants to, allow it to lower this itself.
switch (getTypeAction(Node->getOperand(0).getValueType())) {
@@ -6040,19 +6040,19 @@
assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
TargetLowering::Custom &&
"Must custom expand ReadCycleCounter");
- SDOperand Tmp = TLI.LowerOperation(Op, DAG);
+ SDValue Tmp = TLI.LowerOperation(Op, DAG);
assert(Tmp.Val && "Node must be custom expanded!");
ExpandOp(Tmp.getValue(0), Lo, Hi);
- AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
+ AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
LegalizeOp(Tmp.getValue(1)));
break;
}
case ISD::ATOMIC_CMP_SWAP: {
- SDOperand Tmp = TLI.LowerOperation(Op, DAG);
+ SDValue Tmp = TLI.LowerOperation(Op, DAG);
assert(Tmp.Val && "Node must be custom expanded!");
ExpandOp(Tmp.getValue(0), Lo, Hi);
- AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
+ AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
LegalizeOp(Tmp.getValue(1)));
break;
}
@@ -6063,7 +6063,7 @@
// library functions.
case ISD::FP_TO_SINT: {
if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
- SDOperand Op;
+ SDValue Op;
switch (getTypeAction(Node->getOperand(0).getValueType())) {
case Expand: assert(0 && "cannot expand FP!");
case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
@@ -6089,7 +6089,7 @@
case ISD::FP_TO_UINT: {
if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
- SDOperand Op;
+ SDValue Op;
switch (getTypeAction(Node->getOperand(0).getValueType())) {
case Expand: assert(0 && "cannot expand FP!");
case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
@@ -6114,9 +6114,9 @@
case ISD::SHL: {
// If the target wants custom lowering, do so.
- SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
+ SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
- SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
+ SDValue Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
Op = TLI.LowerOperation(Op, DAG);
if (Op.Val) {
// Now that the custom expander is done, expand the result, which is
@@ -6131,7 +6131,7 @@
if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
TLI.isOperationLegal(ISD::ADDE, NVT)) {
- SDOperand LoOps[2], HiOps[3];
+ SDValue LoOps[2], HiOps[3];
ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
LoOps[1] = LoOps[0];
@@ -6164,9 +6164,9 @@
case ISD::SRA: {
// If the target wants custom lowering, do so.
- SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
+ SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
- SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
+ SDValue Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
Op = TLI.LowerOperation(Op, DAG);
if (Op.Val) {
// Now that the custom expander is done, expand the result, which is
@@ -6196,9 +6196,9 @@
case ISD::SRL: {
// If the target wants custom lowering, do so.
- SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
+ SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
- SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
+ SDValue Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
Op = TLI.LowerOperation(Op, DAG);
if (Op.Val) {
// Now that the custom expander is done, expand the result, which is
@@ -6231,7 +6231,7 @@
// If the target wants to custom expand this, let them.
if (TLI.getOperationAction(Node->getOpcode(), VT) ==
TargetLowering::Custom) {
- SDOperand Result = TLI.LowerOperation(Op, DAG);
+ SDValue Result = TLI.LowerOperation(Op, DAG);
if (Result.Val) {
ExpandOp(Result, Lo, Hi);
break;
@@ -6239,11 +6239,11 @@
}
// Expand the subcomponents.
- SDOperand LHSL, LHSH, RHSL, RHSH;
+ SDValue LHSL, LHSH, RHSL, RHSH;
ExpandOp(Node->getOperand(0), LHSL, LHSH);
ExpandOp(Node->getOperand(1), RHSL, RHSH);
SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
- SDOperand LoOps[2], HiOps[3];
+ SDValue LoOps[2], HiOps[3];
LoOps[0] = LHSL;
LoOps[1] = RHSL;
HiOps[0] = LHSH;
@@ -6263,12 +6263,12 @@
case ISD::ADDC:
case ISD::SUBC: {
// Expand the subcomponents.
- SDOperand LHSL, LHSH, RHSL, RHSH;
+ SDValue LHSL, LHSH, RHSL, RHSH;
ExpandOp(Node->getOperand(0), LHSL, LHSH);
ExpandOp(Node->getOperand(1), RHSL, RHSH);
SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
- SDOperand LoOps[2] = { LHSL, RHSL };
- SDOperand HiOps[3] = { LHSH, RHSH };
+ SDValue LoOps[2] = { LHSL, RHSL };
+ SDValue HiOps[3] = { LHSH, RHSH };
if (Node->getOpcode() == ISD::ADDC) {
Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
@@ -6286,12 +6286,12 @@
case ISD::ADDE:
case ISD::SUBE: {
// Expand the subcomponents.
- SDOperand LHSL, LHSH, RHSL, RHSH;
+ SDValue LHSL, LHSH, RHSL, RHSH;
ExpandOp(Node->getOperand(0), LHSL, LHSH);
ExpandOp(Node->getOperand(1), RHSL, RHSH);
SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
- SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
- SDOperand HiOps[3] = { LHSH, RHSH };
+ SDValue LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
+ SDValue HiOps[3] = { LHSH, RHSH };
Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
HiOps[2] = Lo.getValue(1);
@@ -6304,7 +6304,7 @@
case ISD::MUL: {
// If the target wants to custom expand this, let them.
if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
- SDOperand New = TLI.LowerOperation(Op, DAG);
+ SDValue New = TLI.LowerOperation(Op, DAG);
if (New.Val) {
ExpandOp(New, Lo, Hi);
break;
@@ -6316,7 +6316,7 @@
bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
- SDOperand LL, LH, RL, RH;
+ SDValue LL, LH, RL, RH;
ExpandOp(Node->getOperand(0), LL, LH);
ExpandOp(Node->getOperand(1), RL, RH);
unsigned OuterBitSize = Op.getValueSizeInBits();
@@ -6330,7 +6330,7 @@
if (HasUMUL_LOHI) {
// We can emit a umul_lohi.
Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
- Hi = SDOperand(Lo.Val, 1);
+ Hi = SDValue(Lo.Val, 1);
break;
}
if (HasMULHU) {
@@ -6345,7 +6345,7 @@
if (HasSMUL_LOHI) {
// We can emit a smul_lohi.
Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
- Hi = SDOperand(Lo.Val, 1);
+ Hi = SDValue(Lo.Val, 1);
break;
}
if (HasMULHS) {
@@ -6357,7 +6357,7 @@
}
if (HasUMUL_LOHI) {
// Lo,Hi = umul LHS, RHS.
- SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
+ SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
DAG.getVTList(NVT, NVT), LL, RL);
Lo = UMulLOHI;
Hi = UMulLOHI.getValue(1);
@@ -6478,7 +6478,7 @@
}
case ISD::FABS: {
if (VT == MVT::ppcf128) {
- SDOperand Tmp;
+ SDValue Tmp;
ExpandOp(Node->getOperand(0), Lo, Tmp);
Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
// lo = hi==fabs(hi) ? lo : -lo;
@@ -6487,7 +6487,7 @@
DAG.getCondCode(ISD::SETEQ));
break;
}
- SDOperand Mask = (VT == MVT::f64)
+ SDValue Mask = (VT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
: DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
@@ -6504,7 +6504,7 @@
Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
break;
}
- SDOperand Mask = (VT == MVT::f64)
+ SDValue Mask = (VT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
: DAG.getConstantFP(BitsToFloat(1U << 31), VT);
Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
@@ -6528,7 +6528,7 @@
// Promote the operand if needed. Do this before checking for
// ppcf128 so conversions of i16 and i8 work.
if (getTypeAction(SrcVT) == Promote) {
- SDOperand Tmp = PromoteOp(Node->getOperand(0));
+ SDValue Tmp = PromoteOp(Node->getOperand(0));
Tmp = isSigned
? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
DAG.getValueType(SrcVT))
@@ -6607,8 +6607,8 @@
/// SplitVectorOp - Given an operand of vector type, break it down into
/// two smaller values, still of vector type.
-void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
- SDOperand &Hi) {
+void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
+ SDValue &Hi) {
assert(Op.getValueType().isVector() && "Cannot split non-vector type!");
SDNode *Node = Op.Val;
unsigned NumElements = Op.getValueType().getVectorNumElements();
@@ -6623,7 +6623,7 @@
MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi);
// See if we already split it.
- std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
+ std::map<SDValue, std::pair<SDValue, SDValue> >::iterator I
= SplitNodes.find(Op);
if (I != SplitNodes.end()) {
Lo = I->second.first;
@@ -6649,7 +6649,7 @@
if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
SplitVectorOp(Node->getOperand(0), Lo, Hi);
unsigned Index = Idx->getValue();
- SDOperand ScalarOp = Node->getOperand(1);
+ SDValue ScalarOp = Node->getOperand(1);
if (Index < NewNumElts_Lo)
Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
DAG.getIntPtrConstant(Index));
@@ -6658,7 +6658,7 @@
DAG.getIntPtrConstant(Index - NewNumElts_Lo));
break;
}
- SDOperand Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0),
+ SDValue Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0),
Node->getOperand(1),
Node->getOperand(2));
SplitVectorOp(Tmp, Lo, Hi);
@@ -6666,21 +6666,21 @@
}
case ISD::VECTOR_SHUFFLE: {
// Build the low part.
- SDOperand Mask = Node->getOperand(2);
- SmallVector<SDOperand, 8> Ops;
+ SDValue Mask = Node->getOperand(2);
+ SmallVector<SDValue, 8> Ops;
MVT PtrVT = TLI.getPointerTy();
// Insert all of the elements from the input that are needed. We use
// buildvector of extractelement here because the input vectors will have
// to be legalized, so this makes the code simpler.
for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
- SDOperand IdxNode = Mask.getOperand(i);
+ SDValue IdxNode = Mask.getOperand(i);
if (IdxNode.getOpcode() == ISD::UNDEF) {
Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
continue;
}
unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue();
- SDOperand InVec = Node->getOperand(0);
+ SDValue InVec = Node->getOperand(0);
if (Idx >= NumElements) {
InVec = Node->getOperand(1);
Idx -= NumElements;
@@ -6692,13 +6692,13 @@
Ops.clear();
for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
- SDOperand IdxNode = Mask.getOperand(i);
+ SDValue IdxNode = Mask.getOperand(i);
if (IdxNode.getOpcode() == ISD::UNDEF) {
Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
continue;
}
unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue();
- SDOperand InVec = Node->getOperand(0);
+ SDValue InVec = Node->getOperand(0);
if (Idx >= NumElements) {
InVec = Node->getOperand(1);
Idx -= NumElements;
@@ -6710,11 +6710,11 @@
break;
}
case ISD::BUILD_VECTOR: {
- SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
+ SmallVector<SDValue, 8> LoOps(Node->op_begin(),
Node->op_begin()+NewNumElts_Lo);
Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
- SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
+ SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
Node->op_end());
Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
break;
@@ -6726,26 +6726,26 @@
Lo = Node->getOperand(0);
Hi = Node->getOperand(1);
} else {
- SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
+ SmallVector<SDValue, 8> LoOps(Node->op_begin(),
Node->op_begin()+NewNumSubvectors);
Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
- SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors,
+ SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumSubvectors,
Node->op_end());
Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
}
break;
}
case ISD::SELECT: {
- SDOperand Cond = Node->getOperand(0);
+ SDValue Cond = Node->getOperand(0);
- SDOperand LL, LH, RL, RH;
+ SDValue LL, LH, RL, RH;
SplitVectorOp(Node->getOperand(1), LL, LH);
SplitVectorOp(Node->getOperand(2), RL, RH);
if (Cond.getValueType().isVector()) {
// Handle a vector merge.
- SDOperand CL, CH;
+ SDValue CL, CH;
SplitVectorOp(Cond, CL, CH);
Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
@@ -6757,11 +6757,11 @@
break;
}
case ISD::SELECT_CC: {
- SDOperand CondLHS = Node->getOperand(0);
- SDOperand CondRHS = Node->getOperand(1);
- SDOperand CondCode = Node->getOperand(4);
+ SDValue CondLHS = Node->getOperand(0);
+ SDValue CondRHS = Node->getOperand(1);
+ SDValue CondCode = Node->getOperand(4);
- SDOperand LL, LH, RL, RH;
+ SDValue LL, LH, RL, RH;
SplitVectorOp(Node->getOperand(2), LL, LH);
SplitVectorOp(Node->getOperand(3), RL, RH);
@@ -6773,7 +6773,7 @@
break;
}
case ISD::VSETCC: {
- SDOperand LL, LH, RL, RH;
+ SDValue LL, LH, RL, RH;
SplitVectorOp(Node->getOperand(0), LL, LH);
SplitVectorOp(Node->getOperand(1), RL, RH);
Lo = DAG.getNode(ISD::VSETCC, NewVT_Lo, LL, RL, Node->getOperand(2));
@@ -6796,7 +6796,7 @@
case ISD::UREM:
case ISD::SREM:
case ISD::FREM: {
- SDOperand LL, LH, RL, RH;
+ SDValue LL, LH, RL, RH;
SplitVectorOp(Node->getOperand(0), LL, LH);
SplitVectorOp(Node->getOperand(1), RL, RH);
@@ -6805,7 +6805,7 @@
break;
}
case ISD::FPOWI: {
- SDOperand L, H;
+ SDValue L, H;
SplitVectorOp(Node->getOperand(0), L, H);
Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
@@ -6824,7 +6824,7 @@
case ISD::FP_TO_UINT:
case ISD::SINT_TO_FP:
case ISD::UINT_TO_FP: {
- SDOperand L, H;
+ SDValue L, H;
SplitVectorOp(Node->getOperand(0), L, H);
Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
@@ -6833,8 +6833,8 @@
}
case ISD::LOAD: {
LoadSDNode *LD = cast<LoadSDNode>(Node);
- SDOperand Ch = LD->getChain();
- SDOperand Ptr = LD->getBasePtr();
+ SDValue Ch = LD->getChain();
+ SDValue Ptr = LD->getBasePtr();
const Value *SV = LD->getSrcValue();
int SVOffset = LD->getSrcValueOffset();
unsigned Alignment = LD->getAlignment();
@@ -6850,7 +6850,7 @@
// Build a factor node to remember that this load is independent of the
// other one.
- SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
+ SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
Hi.getValue(1));
// Remember that we legalized the chain.
@@ -6860,7 +6860,7 @@
case ISD::BIT_CONVERT: {
// We know the result is a vector. The input may be either a vector or a
// scalar value.
- SDOperand InOp = Node->getOperand(0);
+ SDValue InOp = Node->getOperand(0);
if (!InOp.getValueType().isVector() ||
InOp.getValueType().getVectorNumElements() == 1) {
// The input is a scalar or single-element vector.
@@ -6868,10 +6868,10 @@
// FIXME: this could be improved probably.
unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment(
Op.getValueType().getTypeForMVT());
- SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign);
+ SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign);
int FI = cast<FrameIndexSDNode>(Ptr.Val)->getIndex();
- SDOperand St = DAG.getStore(DAG.getEntryNode(),
+ SDValue St = DAG.getStore(DAG.getEntryNode(),
InOp, Ptr,
PseudoSourceValue::getFixedStack(FI), 0);
InOp = DAG.getLoad(Op.getValueType(), St, Ptr,
@@ -6895,17 +6895,17 @@
/// ScalarizeVectorOp - Given an operand of single-element vector type
/// (e.g. v1f32), convert it into the equivalent operation that returns a
/// scalar (e.g. f32) value.
-SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) {
+SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!");
SDNode *Node = Op.Val;
MVT NewVT = Op.getValueType().getVectorElementType();
assert(Op.getValueType().getVectorNumElements() == 1);
// See if we already scalarized it.
- std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op);
+ std::map<SDValue, SDValue>::iterator I = ScalarizedNodes.find(Op);
if (I != ScalarizedNodes.end()) return I->second;
- SDOperand Result;
+ SDValue Result;
switch (Node->getOpcode()) {
default:
#ifndef NDEBUG
@@ -6950,8 +6950,8 @@
break;
case ISD::LOAD: {
LoadSDNode *LD = cast<LoadSDNode>(Node);
- SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
- SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
+ SDValue Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
+ SDValue Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
const Value *SV = LD->getSrcValue();
int SVOffset = LD->getSrcValueOffset();
@@ -6976,7 +6976,7 @@
break;
case ISD::VECTOR_SHUFFLE: {
// Figure out if the scalar is the LHS or RHS and return it.
- SDOperand EltNum = Node->getOperand(2).getOperand(0);
+ SDValue EltNum = Node->getOperand(2).getOperand(0);
if (cast<ConstantSDNode>(EltNum)->getValue())
Result = ScalarizeVectorOp(Node->getOperand(1));
else
@@ -6988,7 +6988,7 @@
assert(Result.getValueType() == NewVT);
break;
case ISD::BIT_CONVERT: {
- SDOperand Op0 = Op.getOperand(0);
+ SDValue Op0 = Op.getOperand(0);
if (Op0.getValueType().getVectorNumElements() == 1)
Op0 = ScalarizeVectorOp(Op0);
Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0);
@@ -7007,8 +7007,8 @@
Node->getOperand(4));
break;
case ISD::VSETCC: {
- SDOperand Op0 = ScalarizeVectorOp(Op.getOperand(0));
- SDOperand Op1 = ScalarizeVectorOp(Op.getOperand(1));
+ SDValue Op0 = ScalarizeVectorOp(Op.getOperand(0));
+ SDValue Op1 = ScalarizeVectorOp(Op.getOperand(1));
Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0), Op0, Op1,
Op.getOperand(2));
Result = DAG.getNode(ISD::SELECT, NewVT, Result,
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp Sun Jul 27 16:46:04 2008
@@ -43,7 +43,7 @@
void DAGTypeLegalizer::SoftenFloatResult(SDNode *N, unsigned ResNo) {
DEBUG(cerr << "Soften float result " << ResNo << ": "; N->dump(&DAG);
cerr << "\n");
- SDOperand R = SDOperand();
+ SDValue R = SDValue();
switch (N->getOpcode()) {
default:
@@ -76,14 +76,14 @@
// If R is null, the sub-method took care of registering the result.
if (R.Val)
- SetSoftenedFloat(SDOperand(N, ResNo), R);
+ SetSoftenedFloat(SDValue(N, ResNo), R);
}
-SDOperand DAGTypeLegalizer::SoftenFloatRes_BIT_CONVERT(SDNode *N) {
+SDValue DAGTypeLegalizer::SoftenFloatRes_BIT_CONVERT(SDNode *N) {
return BitConvertToInteger(N->getOperand(0));
}
-SDOperand DAGTypeLegalizer::SoftenFloatRes_BUILD_PAIR(SDNode *N) {
+SDValue DAGTypeLegalizer::SoftenFloatRes_BUILD_PAIR(SDNode *N) {
// Convert the inputs to integers, and build a new pair out of them.
return DAG.getNode(ISD::BUILD_PAIR,
TLI.getTypeToTransformTo(N->getValueType(0)),
@@ -91,14 +91,14 @@
BitConvertToInteger(N->getOperand(1)));
}
-SDOperand DAGTypeLegalizer::SoftenFloatRes_ConstantFP(ConstantFPSDNode *N) {
+SDValue DAGTypeLegalizer::SoftenFloatRes_ConstantFP(ConstantFPSDNode *N) {
return DAG.getConstant(N->getValueAPF().convertToAPInt(),
TLI.getTypeToTransformTo(N->getValueType(0)));
}
-SDOperand DAGTypeLegalizer::SoftenFloatRes_FADD(SDNode *N) {
+SDValue DAGTypeLegalizer::SoftenFloatRes_FADD(SDNode *N) {
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
- SDOperand Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
+ SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
GetSoftenedFloat(N->getOperand(1)) };
return MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::ADD_F32,
@@ -108,9 +108,9 @@
NVT, Ops, 2, false);
}
-SDOperand DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN(SDNode *N) {
- SDOperand LHS = GetSoftenedFloat(N->getOperand(0));
- SDOperand RHS = BitConvertToInteger(N->getOperand(1));
+SDValue DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN(SDNode *N) {
+ SDValue LHS = GetSoftenedFloat(N->getOperand(0));
+ SDValue RHS = BitConvertToInteger(N->getOperand(1));
MVT LVT = LHS.getValueType();
MVT RVT = RHS.getValueType();
@@ -119,7 +119,7 @@
unsigned RSize = RVT.getSizeInBits();
// First get the sign bit of second operand.
- SDOperand SignBit = DAG.getNode(ISD::SHL, RVT, DAG.getConstant(1, RVT),
+ SDValue SignBit = DAG.getNode(ISD::SHL, RVT, DAG.getConstant(1, RVT),
DAG.getConstant(RSize - 1,
TLI.getShiftAmountTy()));
SignBit = DAG.getNode(ISD::AND, RVT, RHS, SignBit);
@@ -137,7 +137,7 @@
}
// Clear the sign bit of the first operand.
- SDOperand Mask = DAG.getNode(ISD::SHL, LVT, DAG.getConstant(1, LVT),
+ SDValue Mask = DAG.getNode(ISD::SHL, LVT, DAG.getConstant(1, LVT),
DAG.getConstant(LSize - 1,
TLI.getShiftAmountTy()));
Mask = DAG.getNode(ISD::SUB, LVT, Mask, DAG.getConstant(1, LVT));
@@ -147,9 +147,9 @@
return DAG.getNode(ISD::OR, LVT, LHS, SignBit);
}
-SDOperand DAGTypeLegalizer::SoftenFloatRes_FDIV(SDNode *N) {
+SDValue DAGTypeLegalizer::SoftenFloatRes_FDIV(SDNode *N) {
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
- SDOperand Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
+ SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
GetSoftenedFloat(N->getOperand(1)) };
return MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::DIV_F32,
@@ -159,9 +159,9 @@
NVT, Ops, 2, false);
}
-SDOperand DAGTypeLegalizer::SoftenFloatRes_FMUL(SDNode *N) {
+SDValue DAGTypeLegalizer::SoftenFloatRes_FMUL(SDNode *N) {
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
- SDOperand Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
+ SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
GetSoftenedFloat(N->getOperand(1)) };
return MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::MUL_F32,
@@ -171,25 +171,25 @@
NVT, Ops, 2, false);
}
-SDOperand DAGTypeLegalizer::SoftenFloatRes_FP_EXTEND(SDNode *N) {
+SDValue DAGTypeLegalizer::SoftenFloatRes_FP_EXTEND(SDNode *N) {
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
- SDOperand Op = N->getOperand(0);
+ SDValue Op = N->getOperand(0);
RTLIB::Libcall LC = RTLIB::getFPEXT(Op.getValueType(), N->getValueType(0));
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
return MakeLibCall(LC, NVT, &Op, 1, false);
}
-SDOperand DAGTypeLegalizer::SoftenFloatRes_FP_ROUND(SDNode *N) {
+SDValue DAGTypeLegalizer::SoftenFloatRes_FP_ROUND(SDNode *N) {
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
- SDOperand Op = N->getOperand(0);
+ SDValue Op = N->getOperand(0);
RTLIB::Libcall LC = RTLIB::getFPROUND(Op.getValueType(), N->getValueType(0));
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!");
return MakeLibCall(LC, NVT, &Op, 1, false);
}
-SDOperand DAGTypeLegalizer::SoftenFloatRes_FPOWI(SDNode *N) {
+SDValue DAGTypeLegalizer::SoftenFloatRes_FPOWI(SDNode *N) {
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
- SDOperand Ops[2] = { GetSoftenedFloat(N->getOperand(0)), N->getOperand(1) };
+ SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)), N->getOperand(1) };
return MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::POWI_F32,
RTLIB::POWI_F64,
@@ -198,9 +198,9 @@
NVT, Ops, 2, false);
}
-SDOperand DAGTypeLegalizer::SoftenFloatRes_FSUB(SDNode *N) {
+SDValue DAGTypeLegalizer::SoftenFloatRes_FSUB(SDNode *N) {
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
- SDOperand Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
+ SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
GetSoftenedFloat(N->getOperand(1)) };
return MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::SUB_F32,
@@ -210,12 +210,12 @@
NVT, Ops, 2, false);
}
-SDOperand DAGTypeLegalizer::SoftenFloatRes_LOAD(SDNode *N) {
+SDValue DAGTypeLegalizer::SoftenFloatRes_LOAD(SDNode *N) {
LoadSDNode *L = cast<LoadSDNode>(N);
MVT VT = N->getValueType(0);
MVT NVT = TLI.getTypeToTransformTo(VT);
- SDOperand NewL;
+ SDValue NewL;
if (L->getExtensionType() == ISD::NON_EXTLOAD) {
NewL = DAG.getLoad(L->getAddressingMode(), L->getExtensionType(),
NVT, L->getChain(), L->getBasePtr(), L->getOffset(),
@@ -223,7 +223,7 @@
L->isVolatile(), L->getAlignment());
// Legalized the chain result - switch anything that used the old chain to
// use the new one.
- ReplaceValueWith(SDOperand(N, 1), NewL.getValue(1));
+ ReplaceValueWith(SDValue(N, 1), NewL.getValue(1));
return NewL;
}
@@ -236,33 +236,33 @@
L->isVolatile(), L->getAlignment());
// Legalized the chain result - switch anything that used the old chain to
// use the new one.
- ReplaceValueWith(SDOperand(N, 1), NewL.getValue(1));
+ ReplaceValueWith(SDValue(N, 1), NewL.getValue(1));
return BitConvertToInteger(DAG.getNode(ISD::FP_EXTEND, VT, NewL));
}
-SDOperand DAGTypeLegalizer::SoftenFloatRes_SELECT(SDNode *N) {
- SDOperand LHS = GetSoftenedFloat(N->getOperand(1));
- SDOperand RHS = GetSoftenedFloat(N->getOperand(2));
+SDValue DAGTypeLegalizer::SoftenFloatRes_SELECT(SDNode *N) {
+ SDValue LHS = GetSoftenedFloat(N->getOperand(1));
+ SDValue RHS = GetSoftenedFloat(N->getOperand(2));
return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0),LHS,RHS);
}
-SDOperand DAGTypeLegalizer::SoftenFloatRes_SELECT_CC(SDNode *N) {
- SDOperand LHS = GetSoftenedFloat(N->getOperand(2));
- SDOperand RHS = GetSoftenedFloat(N->getOperand(3));
+SDValue DAGTypeLegalizer::SoftenFloatRes_SELECT_CC(SDNode *N) {
+ SDValue LHS = GetSoftenedFloat(N->getOperand(2));
+ SDValue RHS = GetSoftenedFloat(N->getOperand(3));
return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(), N->getOperand(0),
N->getOperand(1), LHS, RHS, N->getOperand(4));
}
-SDOperand DAGTypeLegalizer::SoftenFloatRes_SINT_TO_FP(SDNode *N) {
- SDOperand Op = N->getOperand(0);
+SDValue DAGTypeLegalizer::SoftenFloatRes_SINT_TO_FP(SDNode *N) {
+ SDValue Op = N->getOperand(0);
MVT RVT = N->getValueType(0);
RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), RVT);
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SINT_TO_FP!");
return MakeLibCall(LC, TLI.getTypeToTransformTo(RVT), &Op, 1, false);
}
-SDOperand DAGTypeLegalizer::SoftenFloatRes_UINT_TO_FP(SDNode *N) {
- SDOperand Op = N->getOperand(0);
+SDValue DAGTypeLegalizer::SoftenFloatRes_UINT_TO_FP(SDNode *N) {
+ SDValue Op = N->getOperand(0);
MVT RVT = N->getValueType(0);
RTLIB::Libcall LC = RTLIB::getUINTTOFP(Op.getValueType(), RVT);
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UINT_TO_FP!");
@@ -277,7 +277,7 @@
bool DAGTypeLegalizer::SoftenFloatOperand(SDNode *N, unsigned OpNo) {
DEBUG(cerr << "Soften float operand " << OpNo << ": "; N->dump(&DAG);
cerr << "\n");
- SDOperand Res = SDOperand();
+ SDValue Res = SDValue();
switch (N->getOpcode()) {
default:
@@ -313,16 +313,16 @@
assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
"Invalid operand expansion");
- ReplaceValueWith(SDOperand(N, 0), Res);
+ ReplaceValueWith(SDValue(N, 0), Res);
return false;
}
/// SoftenSetCCOperands - Soften the operands of a comparison. This code is
/// shared among BR_CC, SELECT_CC, and SETCC handlers.
-void DAGTypeLegalizer::SoftenSetCCOperands(SDOperand &NewLHS, SDOperand &NewRHS,
+void DAGTypeLegalizer::SoftenSetCCOperands(SDValue &NewLHS, SDValue &NewRHS,
ISD::CondCode &CCCode) {
- SDOperand LHSInt = GetSoftenedFloat(NewLHS);
- SDOperand RHSInt = GetSoftenedFloat(NewRHS);
+ SDValue LHSInt = GetSoftenedFloat(NewLHS);
+ SDValue RHSInt = GetSoftenedFloat(NewRHS);
MVT VT = NewLHS.getValueType();
assert((VT == MVT::f32 || VT == MVT::f64) && "Unsupported setcc type!");
@@ -387,28 +387,28 @@
}
MVT RetVT = MVT::i32; // FIXME: is this the correct return type?
- SDOperand Ops[2] = { LHSInt, RHSInt };
+ SDValue Ops[2] = { LHSInt, RHSInt };
NewLHS = MakeLibCall(LC1, RetVT, Ops, 2, false/*sign irrelevant*/);
NewRHS = DAG.getConstant(0, RetVT);
CCCode = TLI.getCmpLibcallCC(LC1);
if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
- SDOperand Tmp = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(NewLHS),
+ SDValue Tmp = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(NewLHS),
NewLHS, NewRHS, DAG.getCondCode(CCCode));
NewLHS = MakeLibCall(LC2, RetVT, Ops, 2, false/*sign irrelevant*/);
NewLHS = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(NewLHS), NewLHS,
NewRHS, DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
NewLHS = DAG.getNode(ISD::OR, Tmp.getValueType(), Tmp, NewLHS);
- NewRHS = SDOperand();
+ NewRHS = SDValue();
}
}
-SDOperand DAGTypeLegalizer::SoftenFloatOp_BIT_CONVERT(SDNode *N) {
+SDValue DAGTypeLegalizer::SoftenFloatOp_BIT_CONVERT(SDNode *N) {
return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0),
GetSoftenedFloat(N->getOperand(0)));
}
-SDOperand DAGTypeLegalizer::SoftenFloatOp_BR_CC(SDNode *N) {
- SDOperand NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
+SDValue DAGTypeLegalizer::SoftenFloatOp_BR_CC(SDNode *N) {
+ SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
SoftenSetCCOperands(NewLHS, NewRHS, CCCode);
@@ -420,29 +420,29 @@
}
// Update N to have the operands specified.
- return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
+ return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
DAG.getCondCode(CCCode), NewLHS, NewRHS,
N->getOperand(4));
}
-SDOperand DAGTypeLegalizer::SoftenFloatOp_FP_TO_SINT(SDNode *N) {
+SDValue DAGTypeLegalizer::SoftenFloatOp_FP_TO_SINT(SDNode *N) {
MVT RVT = N->getValueType(0);
RTLIB::Libcall LC = RTLIB::getFPTOSINT(N->getOperand(0).getValueType(), RVT);
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_TO_SINT!");
- SDOperand Op = GetSoftenedFloat(N->getOperand(0));
+ SDValue Op = GetSoftenedFloat(N->getOperand(0));
return MakeLibCall(LC, RVT, &Op, 1, false);
}
-SDOperand DAGTypeLegalizer::SoftenFloatOp_FP_TO_UINT(SDNode *N) {
+SDValue DAGTypeLegalizer::SoftenFloatOp_FP_TO_UINT(SDNode *N) {
MVT RVT = N->getValueType(0);
RTLIB::Libcall LC = RTLIB::getFPTOUINT(N->getOperand(0).getValueType(), RVT);
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_TO_UINT!");
- SDOperand Op = GetSoftenedFloat(N->getOperand(0));
+ SDValue Op = GetSoftenedFloat(N->getOperand(0));
return MakeLibCall(LC, RVT, &Op, 1, false);
}
-SDOperand DAGTypeLegalizer::SoftenFloatOp_SELECT_CC(SDNode *N) {
- SDOperand NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
+SDValue DAGTypeLegalizer::SoftenFloatOp_SELECT_CC(SDNode *N) {
+ SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
SoftenSetCCOperands(NewLHS, NewRHS, CCCode);
@@ -454,13 +454,13 @@
}
// Update N to have the operands specified.
- return DAG.UpdateNodeOperands(SDOperand(N, 0), NewLHS, NewRHS,
+ return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
N->getOperand(2), N->getOperand(3),
DAG.getCondCode(CCCode));
}
-SDOperand DAGTypeLegalizer::SoftenFloatOp_SETCC(SDNode *N) {
- SDOperand NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
+SDValue DAGTypeLegalizer::SoftenFloatOp_SETCC(SDNode *N) {
+ SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
SoftenSetCCOperands(NewLHS, NewRHS, CCCode);
@@ -472,15 +472,15 @@
}
// Otherwise, update N to have the operands specified.
- return DAG.UpdateNodeOperands(SDOperand(N, 0), NewLHS, NewRHS,
+ return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
DAG.getCondCode(CCCode));
}
-SDOperand DAGTypeLegalizer::SoftenFloatOp_STORE(SDNode *N, unsigned OpNo) {
+SDValue DAGTypeLegalizer::SoftenFloatOp_STORE(SDNode *N, unsigned OpNo) {
assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
assert(OpNo == 1 && "Can only soften the stored value!");
StoreSDNode *ST = cast<StoreSDNode>(N);
- SDOperand Val = ST->getValue();
+ SDValue Val = ST->getValue();
if (ST->isTruncatingStore())
// Do an FP_ROUND followed by a non-truncating store.
@@ -505,8 +505,8 @@
/// know that (at least) one result needs expansion.
void DAGTypeLegalizer::ExpandFloatResult(SDNode *N, unsigned ResNo) {
DEBUG(cerr << "Expand float result: "; N->dump(&DAG); cerr << "\n");
- SDOperand Lo, Hi;
- Lo = Hi = SDOperand();
+ SDValue Lo, Hi;
+ Lo = Hi = SDValue();
// See if the target wants to custom expand this node.
if (TLI.getOperationAction(N->getOpcode(), N->getValueType(ResNo)) ==
@@ -554,11 +554,11 @@
// If Lo/Hi is null, the sub-method took care of registering results etc.
if (Lo.Val)
- SetExpandedFloat(SDOperand(N, ResNo), Lo, Hi);
+ SetExpandedFloat(SDValue(N, ResNo), Lo, Hi);
}
-void DAGTypeLegalizer::ExpandFloatRes_ConstantFP(SDNode *N, SDOperand &Lo,
- SDOperand &Hi) {
+void DAGTypeLegalizer::ExpandFloatRes_ConstantFP(SDNode *N, SDValue &Lo,
+ SDValue &Hi) {
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
assert(NVT.getSizeInBits() == integerPartWidth &&
"Do not know how to expand this float constant!");
@@ -569,10 +569,10 @@
&C.getRawData()[0])), NVT);
}
-void DAGTypeLegalizer::ExpandFloatRes_FADD(SDNode *N, SDOperand &Lo,
- SDOperand &Hi) {
- SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
- SDOperand Call = MakeLibCall(GetFPLibCall(N->getValueType(0),
+void DAGTypeLegalizer::ExpandFloatRes_FADD(SDNode *N, SDValue &Lo,
+ SDValue &Hi) {
+ SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
+ SDValue Call = MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::ADD_F32,
RTLIB::ADD_F64,
RTLIB::ADD_F80,
@@ -583,11 +583,11 @@
Lo = Call.getOperand(0); Hi = Call.getOperand(1);
}
-void DAGTypeLegalizer::ExpandFloatRes_FABS(SDNode *N, SDOperand &Lo,
- SDOperand &Hi) {
+void DAGTypeLegalizer::ExpandFloatRes_FABS(SDNode *N, SDValue &Lo,
+ SDValue &Hi) {
assert(N->getValueType(0) == MVT::ppcf128 &&
"Logic only correct for ppcf128!");
- SDOperand Tmp;
+ SDValue Tmp;
GetExpandedFloat(N->getOperand(0), Lo, Tmp);
Hi = DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp);
// Lo = Hi==fabs(Hi) ? Lo : -Lo;
@@ -596,10 +596,10 @@
DAG.getCondCode(ISD::SETEQ));
}
-void DAGTypeLegalizer::ExpandFloatRes_FDIV(SDNode *N, SDOperand &Lo,
- SDOperand &Hi) {
- SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
- SDOperand Call = MakeLibCall(GetFPLibCall(N->getValueType(0),
+void DAGTypeLegalizer::ExpandFloatRes_FDIV(SDNode *N, SDValue &Lo,
+ SDValue &Hi) {
+ SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
+ SDValue Call = MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::DIV_F32,
RTLIB::DIV_F64,
RTLIB::DIV_F80,
@@ -610,10 +610,10 @@
Lo = Call.getOperand(0); Hi = Call.getOperand(1);
}
-void DAGTypeLegalizer::ExpandFloatRes_FMUL(SDNode *N, SDOperand &Lo,
- SDOperand &Hi) {
- SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
- SDOperand Call = MakeLibCall(GetFPLibCall(N->getValueType(0),
+void DAGTypeLegalizer::ExpandFloatRes_FMUL(SDNode *N, SDValue &Lo,
+ SDValue &Hi) {
+ SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
+ SDValue Call = MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::MUL_F32,
RTLIB::MUL_F64,
RTLIB::MUL_F80,
@@ -624,24 +624,24 @@
Lo = Call.getOperand(0); Hi = Call.getOperand(1);
}
-void DAGTypeLegalizer::ExpandFloatRes_FNEG(SDNode *N, SDOperand &Lo,
- SDOperand &Hi) {
+void DAGTypeLegalizer::ExpandFloatRes_FNEG(SDNode *N, SDValue &Lo,
+ SDValue &Hi) {
GetExpandedFloat(N->getOperand(0), Lo, Hi);
Lo = DAG.getNode(ISD::FNEG, Lo.getValueType(), Lo);
Hi = DAG.getNode(ISD::FNEG, Hi.getValueType(), Hi);
}
-void DAGTypeLegalizer::ExpandFloatRes_FP_EXTEND(SDNode *N, SDOperand &Lo,
- SDOperand &Hi) {
+void DAGTypeLegalizer::ExpandFloatRes_FP_EXTEND(SDNode *N, SDValue &Lo,
+ SDValue &Hi) {
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
Hi = DAG.getNode(ISD::FP_EXTEND, NVT, N->getOperand(0));
Lo = DAG.getConstantFP(APFloat(APInt(NVT.getSizeInBits(), 0)), NVT);
}
-void DAGTypeLegalizer::ExpandFloatRes_FSUB(SDNode *N, SDOperand &Lo,
- SDOperand &Hi) {
- SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
- SDOperand Call = MakeLibCall(GetFPLibCall(N->getValueType(0),
+void DAGTypeLegalizer::ExpandFloatRes_FSUB(SDNode *N, SDValue &Lo,
+ SDValue &Hi) {
+ SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
+ SDValue Call = MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::SUB_F32,
RTLIB::SUB_F64,
RTLIB::SUB_F80,
@@ -652,8 +652,8 @@
Lo = Call.getOperand(0); Hi = Call.getOperand(1);
}
-void DAGTypeLegalizer::ExpandFloatRes_LOAD(SDNode *N, SDOperand &Lo,
- SDOperand &Hi) {
+void DAGTypeLegalizer::ExpandFloatRes_LOAD(SDNode *N, SDValue &Lo,
+ SDValue &Hi) {
if (ISD::isNormalLoad(N)) {
ExpandRes_NormalLoad(N, Lo, Hi);
return;
@@ -661,8 +661,8 @@
assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
LoadSDNode *LD = cast<LoadSDNode>(N);
- SDOperand Chain = LD->getChain();
- SDOperand Ptr = LD->getBasePtr();
+ SDValue Chain = LD->getChain();
+ SDValue Ptr = LD->getBasePtr();
MVT NVT = TLI.getTypeToTransformTo(LD->getValueType(0));
assert(NVT.isByteSized() && "Expanded type not byte sized!");
@@ -681,15 +681,15 @@
// Modified the chain - switch anything that used the old chain to use the
// new one.
- ReplaceValueWith(SDOperand(LD, 1), Chain);
+ ReplaceValueWith(SDValue(LD, 1), Chain);
}
-void DAGTypeLegalizer::ExpandFloatRes_XINT_TO_FP(SDNode *N, SDOperand &Lo,
- SDOperand &Hi) {
+void DAGTypeLegalizer::ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo,
+ SDValue &Hi) {
assert(N->getValueType(0) == MVT::ppcf128 && "Unsupported XINT_TO_FP!");
MVT VT = N->getValueType(0);
MVT NVT = TLI.getTypeToTransformTo(VT);
- SDOperand Src = N->getOperand(0);
+ SDValue Src = N->getOperand(0);
MVT SrcVT = Src.getValueType();
// First do an SINT_TO_FP, whether the original was signed or unsigned.
@@ -760,11 +760,11 @@
/// need promotion or expansion as well as the specified one.
bool DAGTypeLegalizer::ExpandFloatOperand(SDNode *N, unsigned OpNo) {
DEBUG(cerr << "Expand float operand: "; N->dump(&DAG); cerr << "\n");
- SDOperand Res = SDOperand();
+ SDValue Res = SDValue();
if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType())
== TargetLowering::Custom)
- Res = TLI.LowerOperation(SDOperand(N, OpNo), DAG);
+ Res = TLI.LowerOperation(SDValue(N, OpNo), DAG);
if (Res.Val == 0) {
switch (N->getOpcode()) {
@@ -806,16 +806,16 @@
assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
"Invalid operand expansion");
- ReplaceValueWith(SDOperand(N, 0), Res);
+ ReplaceValueWith(SDValue(N, 0), Res);
return false;
}
/// FloatExpandSetCCOperands - Expand the operands of a comparison. This code
/// is shared among BR_CC, SELECT_CC, and SETCC handlers.
-void DAGTypeLegalizer::FloatExpandSetCCOperands(SDOperand &NewLHS,
- SDOperand &NewRHS,
+void DAGTypeLegalizer::FloatExpandSetCCOperands(SDValue &NewLHS,
+ SDValue &NewRHS,
ISD::CondCode &CCCode) {
- SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
+ SDValue LHSLo, LHSHi, RHSLo, RHSHi;
GetExpandedFloat(NewLHS, LHSLo, LHSHi);
GetExpandedFloat(NewRHS, RHSLo, RHSHi);
@@ -827,7 +827,7 @@
// BNE crN, L:
// FCMP crN, lo1, lo2
// The following can be improved, but not that much.
- SDOperand Tmp1, Tmp2, Tmp3;
+ SDValue Tmp1, Tmp2, Tmp3;
Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETEQ);
Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode);
Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
@@ -835,11 +835,11 @@
Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode);
Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
NewLHS = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
- NewRHS = SDOperand(); // LHS is the result, not a compare.
+ NewRHS = SDValue(); // LHS is the result, not a compare.
}
-SDOperand DAGTypeLegalizer::ExpandFloatOp_BR_CC(SDNode *N) {
- SDOperand NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
+SDValue DAGTypeLegalizer::ExpandFloatOp_BR_CC(SDNode *N) {
+ SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
FloatExpandSetCCOperands(NewLHS, NewRHS, CCCode);
@@ -851,36 +851,36 @@
}
// Update N to have the operands specified.
- return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
+ return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
DAG.getCondCode(CCCode), NewLHS, NewRHS,
N->getOperand(4));
}
-SDOperand DAGTypeLegalizer::ExpandFloatOp_FP_ROUND(SDNode *N) {
+SDValue DAGTypeLegalizer::ExpandFloatOp_FP_ROUND(SDNode *N) {
assert(N->getOperand(0).getValueType() == MVT::ppcf128 &&
"Logic only correct for ppcf128!");
- SDOperand Lo, Hi;
+ SDValue Lo, Hi;
GetExpandedFloat(N->getOperand(0), Lo, Hi);
// Round it the rest of the way (e.g. to f32) if needed.
return DAG.getNode(ISD::FP_ROUND, N->getValueType(0), Hi, N->getOperand(1));
}
-SDOperand DAGTypeLegalizer::ExpandFloatOp_FP_TO_SINT(SDNode *N) {
+SDValue DAGTypeLegalizer::ExpandFloatOp_FP_TO_SINT(SDNode *N) {
MVT RVT = N->getValueType(0);
RTLIB::Libcall LC = RTLIB::getFPTOSINT(N->getOperand(0).getValueType(), RVT);
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_TO_SINT!");
return MakeLibCall(LC, RVT, &N->getOperand(0), 1, false);
}
-SDOperand DAGTypeLegalizer::ExpandFloatOp_FP_TO_UINT(SDNode *N) {
+SDValue DAGTypeLegalizer::ExpandFloatOp_FP_TO_UINT(SDNode *N) {
MVT RVT = N->getValueType(0);
RTLIB::Libcall LC = RTLIB::getFPTOUINT(N->getOperand(0).getValueType(), RVT);
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_TO_UINT!");
return MakeLibCall(LC, N->getValueType(0), &N->getOperand(0), 1, false);
}
-SDOperand DAGTypeLegalizer::ExpandFloatOp_SELECT_CC(SDNode *N) {
- SDOperand NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
+SDValue DAGTypeLegalizer::ExpandFloatOp_SELECT_CC(SDNode *N) {
+ SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
FloatExpandSetCCOperands(NewLHS, NewRHS, CCCode);
@@ -892,13 +892,13 @@
}
// Update N to have the operands specified.
- return DAG.UpdateNodeOperands(SDOperand(N, 0), NewLHS, NewRHS,
+ return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
N->getOperand(2), N->getOperand(3),
DAG.getCondCode(CCCode));
}
-SDOperand DAGTypeLegalizer::ExpandFloatOp_SETCC(SDNode *N) {
- SDOperand NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
+SDValue DAGTypeLegalizer::ExpandFloatOp_SETCC(SDNode *N) {
+ SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
FloatExpandSetCCOperands(NewLHS, NewRHS, CCCode);
@@ -910,11 +910,11 @@
}
// Otherwise, update N to have the operands specified.
- return DAG.UpdateNodeOperands(SDOperand(N, 0), NewLHS, NewRHS,
+ return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
DAG.getCondCode(CCCode));
}
-SDOperand DAGTypeLegalizer::ExpandFloatOp_STORE(SDNode *N, unsigned OpNo) {
+SDValue DAGTypeLegalizer::ExpandFloatOp_STORE(SDNode *N, unsigned OpNo) {
if (ISD::isNormalStore(N))
return ExpandOp_NormalStore(N, OpNo);
@@ -922,14 +922,14 @@
assert(OpNo == 1 && "Can only expand the stored value so far");
StoreSDNode *ST = cast<StoreSDNode>(N);
- SDOperand Chain = ST->getChain();
- SDOperand Ptr = ST->getBasePtr();
+ SDValue Chain = ST->getChain();
+ SDValue Ptr = ST->getBasePtr();
MVT NVT = TLI.getTypeToTransformTo(ST->getValue().getValueType());
assert(NVT.isByteSized() && "Expanded type not byte sized!");
assert(ST->getMemoryVT().bitsLE(NVT) && "Float type not round?");
- SDOperand Lo, Hi;
+ SDValue Lo, Hi;
GetExpandedOp(ST->getValue(), Lo, Hi);
return DAG.getTruncStore(Chain, Lo, Ptr,
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Sun Jul 27 16:46:04 2008
@@ -31,7 +31,7 @@
/// expansion, we just know that (at least) one result needs promotion.
void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
DEBUG(cerr << "Promote integer result: "; N->dump(&DAG); cerr << "\n");
- SDOperand Result = SDOperand();
+ SDValue Result = SDValue();
// See if the target wants to custom expand this node.
if (TLI.getOperationAction(N->getOpcode(), N->getValueType(ResNo)) ==
@@ -100,28 +100,28 @@
// If Result is null, the sub-method took care of registering the result.
if (Result.Val)
- SetPromotedInteger(SDOperand(N, ResNo), Result);
+ SetPromotedInteger(SDValue(N, ResNo), Result);
}
-SDOperand DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
+SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
// Sign-extend the new bits, and continue the assertion.
MVT OldVT = N->getValueType(0);
- SDOperand Op = GetPromotedInteger(N->getOperand(0));
+ SDValue Op = GetPromotedInteger(N->getOperand(0));
return DAG.getNode(ISD::AssertSext, Op.getValueType(),
DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op,
DAG.getValueType(OldVT)), N->getOperand(1));
}
-SDOperand DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
+SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
// Zero the new bits, and continue the assertion.
MVT OldVT = N->getValueType(0);
- SDOperand Op = GetPromotedInteger(N->getOperand(0));
+ SDValue Op = GetPromotedInteger(N->getOperand(0));
return DAG.getNode(ISD::AssertZext, Op.getValueType(),
DAG.getZeroExtendInReg(Op, OldVT), N->getOperand(1));
}
-SDOperand DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
- SDOperand InOp = N->getOperand(0);
+SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
+ SDValue InOp = N->getOperand(0);
MVT InVT = InOp.getValueType();
MVT NInVT = TLI.getTypeToTransformTo(InVT);
MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
@@ -150,7 +150,7 @@
case SplitVector:
// For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split
// pieces of the input into integers and reassemble in the final type.
- SDOperand Lo, Hi;
+ SDValue Lo, Hi;
GetSplitVector(N->getOperand(0), Lo, Hi);
Lo = BitConvertToInteger(Lo);
Hi = BitConvertToInteger(Hi);
@@ -166,12 +166,12 @@
// Otherwise, lower the bit-convert to a store/load from the stack, then
// promote the load.
- SDOperand Op = CreateStackStoreLoad(InOp, N->getValueType(0));
+ SDValue Op = CreateStackStoreLoad(InOp, N->getValueType(0));
return PromoteIntRes_LOAD(cast<LoadSDNode>(Op.Val));
}
-SDOperand DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
- SDOperand Op = GetPromotedInteger(N->getOperand(0));
+SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
+ SDValue Op = GetPromotedInteger(N->getOperand(0));
MVT OVT = N->getValueType(0);
MVT NVT = Op.getValueType();
@@ -180,7 +180,7 @@
DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
}
-SDOperand DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
+SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
// The pair element type may be legal, or may not promote to the same type as
// the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
return DAG.getNode(ISD::ANY_EXTEND,
@@ -188,19 +188,19 @@
JoinIntegers(N->getOperand(0), N->getOperand(1)));
}
-SDOperand DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
+SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
MVT VT = N->getValueType(0);
// Zero extend things like i1, sign extend everything else. It shouldn't
// matter in theory which one we pick, but this tends to give better code?
unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
- SDOperand Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT),
- SDOperand(N, 0));
+ SDValue Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT),
+ SDValue(N, 0));
assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
return Result;
}
-SDOperand DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
- SDOperand Op = GetPromotedInteger(N->getOperand(0));
+SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
+ SDValue Op = GetPromotedInteger(N->getOperand(0));
MVT OVT = N->getValueType(0);
MVT NVT = Op.getValueType();
// Zero extend to the promoted type and do the count there.
@@ -211,16 +211,16 @@
OVT.getSizeInBits(), NVT));
}
-SDOperand DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
- SDOperand Op = GetPromotedInteger(N->getOperand(0));
+SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
+ SDValue Op = GetPromotedInteger(N->getOperand(0));
MVT OVT = N->getValueType(0);
MVT NVT = Op.getValueType();
// Zero extend to the promoted type and do the count there.
return DAG.getNode(ISD::CTPOP, NVT, DAG.getZeroExtendInReg(Op, OVT));
}
-SDOperand DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
- SDOperand Op = GetPromotedInteger(N->getOperand(0));
+SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
+ SDValue Op = GetPromotedInteger(N->getOperand(0));
MVT OVT = N->getValueType(0);
MVT NVT = Op.getValueType();
// The count is the same in the promoted type except if the original
@@ -232,9 +232,9 @@
return DAG.getNode(ISD::CTTZ, NVT, Op);
}
-SDOperand DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
+SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
MVT OldVT = N->getValueType(0);
- SDOperand OldVec = N->getOperand(0);
+ SDValue OldVec = N->getOperand(0);
unsigned OldElts = OldVec.getValueType().getVectorNumElements();
if (OldElts == 1) {
@@ -253,31 +253,31 @@
MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
assert(OldVT.isSimple() && NewVT.isSimple());
- SDOperand NewVec = DAG.getNode(ISD::BIT_CONVERT,
+ SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT,
MVT::getVectorVT(NewVT, OldElts / 2),
OldVec);
// Extract the element at OldIdx / 2 from the new vector.
- SDOperand OldIdx = N->getOperand(1);
- SDOperand NewIdx = DAG.getNode(ISD::SRL, OldIdx.getValueType(), OldIdx,
+ SDValue OldIdx = N->getOperand(1);
+ SDValue NewIdx = DAG.getNode(ISD::SRL, OldIdx.getValueType(), OldIdx,
DAG.getConstant(1, TLI.getShiftAmountTy()));
- SDOperand Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, NewVec, NewIdx);
+ SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, NewVec, NewIdx);
// Select the appropriate half of the element: Lo if OldIdx was even,
// Hi if it was odd.
- SDOperand Lo = Elt;
- SDOperand Hi = DAG.getNode(ISD::SRL, NewVT, Elt,
+ SDValue Lo = Elt;
+ SDValue Hi = DAG.getNode(ISD::SRL, NewVT, Elt,
DAG.getConstant(OldVT.getSizeInBits(),
TLI.getShiftAmountTy()));
if (TLI.isBigEndian())
std::swap(Lo, Hi);
- SDOperand Odd = DAG.getNode(ISD::AND, OldIdx.getValueType(), OldIdx,
+ SDValue Odd = DAG.getNode(ISD::AND, OldIdx.getValueType(), OldIdx,
DAG.getConstant(1, TLI.getShiftAmountTy()));
return DAG.getNode(ISD::SELECT, NewVT, Odd, Hi, Lo);
}
-SDOperand DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
+SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
unsigned NewOpc = N->getOpcode();
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
@@ -296,11 +296,11 @@
return DAG.getNode(NewOpc, NVT, N->getOperand(0));
}
-SDOperand DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
+SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) {
- SDOperand Res = GetPromotedInteger(N->getOperand(0));
+ SDValue Res = GetPromotedInteger(N->getOperand(0));
assert(Res.getValueType().getSizeInBits() <= NVT.getSizeInBits() &&
"Extension doesn't make sense!");
@@ -322,26 +322,26 @@
return DAG.getNode(N->getOpcode(), NVT, N->getOperand(0));
}
-SDOperand DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
+SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
ISD::LoadExtType ExtType =
ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
- SDOperand Res = DAG.getExtLoad(ExtType, NVT, N->getChain(), N->getBasePtr(),
+ SDValue Res = DAG.getExtLoad(ExtType, NVT, N->getChain(), N->getBasePtr(),
N->getSrcValue(), N->getSrcValueOffset(),
N->getMemoryVT(), N->isVolatile(),
N->getAlignment());
// Legalized the chain result - switch anything that used the old chain to
// use the new one.
- ReplaceValueWith(SDOperand(N, 1), Res.getValue(1));
+ ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
return Res;
}
-SDOperand DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
+SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
// Sign extend the input.
- SDOperand LHS = GetPromotedInteger(N->getOperand(0));
- SDOperand RHS = GetPromotedInteger(N->getOperand(1));
+ SDValue LHS = GetPromotedInteger(N->getOperand(0));
+ SDValue RHS = GetPromotedInteger(N->getOperand(1));
MVT VT = N->getValueType(0);
LHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, LHS.getValueType(), LHS,
DAG.getValueType(VT));
@@ -351,65 +351,65 @@
return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
}
-SDOperand DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
- SDOperand LHS = GetPromotedInteger(N->getOperand(1));
- SDOperand RHS = GetPromotedInteger(N->getOperand(2));
+SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
+ SDValue LHS = GetPromotedInteger(N->getOperand(1));
+ SDValue RHS = GetPromotedInteger(N->getOperand(2));
return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0),LHS,RHS);
}
-SDOperand DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
- SDOperand LHS = GetPromotedInteger(N->getOperand(2));
- SDOperand RHS = GetPromotedInteger(N->getOperand(3));
+SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
+ SDValue LHS = GetPromotedInteger(N->getOperand(2));
+ SDValue RHS = GetPromotedInteger(N->getOperand(3));
return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(), N->getOperand(0),
N->getOperand(1), LHS, RHS, N->getOperand(4));
}
-SDOperand DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
+SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
assert(isTypeLegal(TLI.getSetCCResultType(N->getOperand(0)))
&& "SetCC type is not legal??");
return DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(N->getOperand(0)),
N->getOperand(0), N->getOperand(1), N->getOperand(2));
}
-SDOperand DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
+SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
return DAG.getNode(ISD::SHL, TLI.getTypeToTransformTo(N->getValueType(0)),
GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
}
-SDOperand DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
- SDOperand Op = GetPromotedInteger(N->getOperand(0));
+SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
+ SDValue Op = GetPromotedInteger(N->getOperand(0));
return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op,
N->getOperand(1));
}
-SDOperand DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
+SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
// The input may have strange things in the top bits of the registers, but
// these operations don't care. They may have weird bits going out, but
// that too is okay if they are integer operations.
- SDOperand LHS = GetPromotedInteger(N->getOperand(0));
- SDOperand RHS = GetPromotedInteger(N->getOperand(1));
+ SDValue LHS = GetPromotedInteger(N->getOperand(0));
+ SDValue RHS = GetPromotedInteger(N->getOperand(1));
return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
}
-SDOperand DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
+SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
// The input value must be properly sign extended.
MVT VT = N->getValueType(0);
MVT NVT = TLI.getTypeToTransformTo(VT);
- SDOperand Res = GetPromotedInteger(N->getOperand(0));
+ SDValue Res = GetPromotedInteger(N->getOperand(0));
Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, DAG.getValueType(VT));
return DAG.getNode(ISD::SRA, NVT, Res, N->getOperand(1));
}
-SDOperand DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
+SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
// The input value must be properly zero extended.
MVT VT = N->getValueType(0);
MVT NVT = TLI.getTypeToTransformTo(VT);
- SDOperand Res = ZExtPromotedInteger(N->getOperand(0));
+ SDValue Res = ZExtPromotedInteger(N->getOperand(0));
return DAG.getNode(ISD::SRL, NVT, Res, N->getOperand(1));
}
-SDOperand DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
- SDOperand Res;
+SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
+ SDValue Res;
switch (getTypeAction(N->getOperand(0).getValueType())) {
default: assert(0 && "Unknown type action!");
@@ -432,10 +432,10 @@
return DAG.getNode(ISD::TRUNCATE, NVT, Res);
}
-SDOperand DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
+SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
// Zero extend the input.
- SDOperand LHS = GetPromotedInteger(N->getOperand(0));
- SDOperand RHS = GetPromotedInteger(N->getOperand(1));
+ SDValue LHS = GetPromotedInteger(N->getOperand(0));
+ SDValue RHS = GetPromotedInteger(N->getOperand(1));
MVT VT = N->getValueType(0);
LHS = DAG.getZeroExtendInReg(LHS, VT);
RHS = DAG.getZeroExtendInReg(RHS, VT);
@@ -443,17 +443,17 @@
return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
}
-SDOperand DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
+SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
return DAG.getNode(ISD::UNDEF, TLI.getTypeToTransformTo(N->getValueType(0)));
}
-SDOperand DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
- SDOperand Chain = N->getOperand(0); // Get the chain.
- SDOperand Ptr = N->getOperand(1); // Get the pointer.
+SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
+ SDValue Chain = N->getOperand(0); // Get the chain.
+ SDValue Ptr = N->getOperand(1); // Get the pointer.
MVT VT = N->getValueType(0);
const Value *V = cast<SrcValueSDNode>(N->getOperand(2))->getValue();
- SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Chain, Ptr, V, 0);
+ SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Chain, Ptr, V, 0);
// Increment the arg pointer, VAList, to the next vaarg
// FIXME: should the ABI size be used for the increment? Think of
@@ -461,7 +461,7 @@
// integers of unusual size (such MVT::i1, which gives an increment
// of zero here!).
unsigned Increment = VT.getSizeInBits() / 8;
- SDOperand Tmp = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
+ SDValue Tmp = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
DAG.getConstant(Increment, TLI.getPointerTy()));
// Store the incremented VAList to the pointer.
@@ -473,7 +473,7 @@
// Legalized the chain result - switch anything that used the old chain to
// use the new one.
- ReplaceValueWith(SDOperand(N, 1), Tmp.getValue(1));
+ ReplaceValueWith(SDValue(N, 1), Tmp.getValue(1));
return Tmp;
}
@@ -488,11 +488,11 @@
/// node may need promotion or expansion as well as the specified one.
bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
DEBUG(cerr << "Promote integer operand: "; N->dump(&DAG); cerr << "\n");
- SDOperand Res = SDOperand();
+ SDValue Res = SDValue();
if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType())
== TargetLowering::Custom)
- Res = TLI.LowerOperation(SDOperand(N, OpNo), DAG);
+ Res = TLI.LowerOperation(SDValue(N, OpNo), DAG);
if (Res.Val == 0) {
switch (N->getOpcode()) {
@@ -542,13 +542,13 @@
assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
"Invalid operand expansion");
- ReplaceValueWith(SDOperand(N, 0), Res);
+ ReplaceValueWith(SDValue(N, 0), Res);
return false;
}
/// PromoteSetCCOperands - Promote the operands of a comparison. This code is
/// shared among BR_CC, SELECT_CC, and SETCC handlers.
-void DAGTypeLegalizer::PromoteSetCCOperands(SDOperand &NewLHS,SDOperand &NewRHS,
+void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
ISD::CondCode CCCode) {
MVT VT = NewLHS.getValueType();
@@ -586,27 +586,27 @@
}
}
-SDOperand DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
- SDOperand Op = GetPromotedInteger(N->getOperand(0));
+SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
+ SDValue Op = GetPromotedInteger(N->getOperand(0));
return DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
}
-SDOperand DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
+SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
assert(OpNo == 2 && "Don't know how to promote this operand!");
- SDOperand LHS = N->getOperand(2);
- SDOperand RHS = N->getOperand(3);
+ SDValue LHS = N->getOperand(2);
+ SDValue RHS = N->getOperand(3);
PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
// The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
// legal types.
- return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
+ return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
N->getOperand(1), LHS, RHS, N->getOperand(4));
}
-SDOperand DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
+SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
assert(OpNo == 1 && "only know how to promote condition");
- SDOperand Cond = GetPromotedInteger(N->getOperand(1)); // Promote condition.
+ SDValue Cond = GetPromotedInteger(N->getOperand(1)); // Promote condition.
// The top bits of the promoted condition are not necessarily zero, ensure
// that the value is properly zero extended.
@@ -616,15 +616,15 @@
Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
// The chain (Op#0) and basic block destination (Op#2) are always legal types.
- return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0), Cond,
+ return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Cond,
N->getOperand(2));
}
-SDOperand DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
+SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
// Since the result type is legal, the operands must promote to it.
MVT OVT = N->getOperand(0).getValueType();
- SDOperand Lo = GetPromotedInteger(N->getOperand(0));
- SDOperand Hi = GetPromotedInteger(N->getOperand(1));
+ SDValue Lo = GetPromotedInteger(N->getOperand(0));
+ SDValue Hi = GetPromotedInteger(N->getOperand(1));
assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
Lo = DAG.getZeroExtendInReg(Lo, OVT);
@@ -634,7 +634,7 @@
return DAG.getNode(ISD::OR, N->getValueType(0), Lo, Hi);
}
-SDOperand DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
+SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
// The vector type is legal but the element type is not. This implies
// that the vector is a power-of-two in length and that the element
// type does not have a strange size (eg: it is not i1).
@@ -648,19 +648,19 @@
MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
assert(OldVT.isSimple() && NewVT.isSimple());
- std::vector<SDOperand> NewElts;
+ std::vector<SDValue> NewElts;
NewElts.reserve(NumElts/2);
for (unsigned i = 0; i < NumElts; i += 2) {
// Combine two successive elements into one promoted element.
- SDOperand Lo = N->getOperand(i);
- SDOperand Hi = N->getOperand(i+1);
+ SDValue Lo = N->getOperand(i);
+ SDValue Hi = N->getOperand(i+1);
if (TLI.isBigEndian())
std::swap(Lo, Hi);
NewElts.push_back(JoinIntegers(Lo, Hi));
}
- SDOperand NewVec = DAG.getNode(ISD::BUILD_VECTOR,
+ SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR,
MVT::getVectorVT(NewVT, NewElts.size()),
&NewElts[0], NewElts.size());
@@ -668,19 +668,19 @@
return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec);
}
-SDOperand DAGTypeLegalizer::PromoteIntOp_FP_EXTEND(SDNode *N) {
- SDOperand Op = GetPromotedInteger(N->getOperand(0));
+SDValue DAGTypeLegalizer::PromoteIntOp_FP_EXTEND(SDNode *N) {
+ SDValue Op = GetPromotedInteger(N->getOperand(0));
return DAG.getNode(ISD::FP_EXTEND, N->getValueType(0), Op);
}
-SDOperand DAGTypeLegalizer::PromoteIntOp_FP_ROUND(SDNode *N) {
- SDOperand Op = GetPromotedInteger(N->getOperand(0));
+SDValue DAGTypeLegalizer::PromoteIntOp_FP_ROUND(SDNode *N) {
+ SDValue Op = GetPromotedInteger(N->getOperand(0));
return DAG.getNode(ISD::FP_ROUND, N->getValueType(0), Op,
DAG.getIntPtrConstant(0));
}
-SDOperand DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
- unsigned OpNo) {
+SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
+ unsigned OpNo) {
if (OpNo == 1) {
// Promote the inserted value. This is valid because the type does not
// have to match the vector element type.
@@ -689,7 +689,7 @@
assert(N->getOperand(1).getValueType().getSizeInBits() >=
N->getValueType(0).getVectorElementType().getSizeInBits() &&
"Type of inserted value narrower than vector element type!");
- return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
+ return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
GetPromotedInteger(N->getOperand(1)),
N->getOperand(2));
}
@@ -697,14 +697,14 @@
assert(OpNo == 2 && "Different operand and result vector types?");
// Promote the index.
- SDOperand Idx = N->getOperand(2);
+ SDValue Idx = N->getOperand(2);
Idx = DAG.getZeroExtendInReg(GetPromotedInteger(Idx), Idx.getValueType());
- return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
+ return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
N->getOperand(1), Idx);
}
-SDOperand DAGTypeLegalizer::PromoteIntOp_INT_TO_FP(SDNode *N) {
- SDOperand In = GetPromotedInteger(N->getOperand(0));
+SDValue DAGTypeLegalizer::PromoteIntOp_INT_TO_FP(SDNode *N) {
+ SDValue In = GetPromotedInteger(N->getOperand(0));
MVT OpVT = N->getOperand(0).getValueType();
if (N->getOpcode() == ISD::UINT_TO_FP)
In = DAG.getZeroExtendInReg(In, OpVT);
@@ -712,23 +712,23 @@
In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(),
In, DAG.getValueType(OpVT));
- return DAG.UpdateNodeOperands(SDOperand(N, 0), In);
+ return DAG.UpdateNodeOperands(SDValue(N, 0), In);
}
-SDOperand DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
- SDOperand NewOps[6];
+SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
+ SDValue NewOps[6];
NewOps[0] = N->getOperand(0);
for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
- SDOperand Flag = GetPromotedInteger(N->getOperand(i));
+ SDValue Flag = GetPromotedInteger(N->getOperand(i));
NewOps[i] = DAG.getZeroExtendInReg(Flag, MVT::i1);
}
- return DAG.UpdateNodeOperands(SDOperand (N, 0), NewOps,
+ return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps,
array_lengthof(NewOps));
}
-SDOperand DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
+SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
assert(OpNo == 0 && "Only know how to promote condition");
- SDOperand Cond = GetPromotedInteger(N->getOperand(0)); // Promote condition.
+ SDValue Cond = GetPromotedInteger(N->getOperand(0)); // Promote condition.
// The top bits of the promoted condition are not necessarily zero, ensure
// that the value is properly zero extended.
@@ -738,48 +738,48 @@
Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
// The chain (Op#0) and basic block destination (Op#2) are always legal types.
- return DAG.UpdateNodeOperands(SDOperand(N, 0), Cond, N->getOperand(1),
+ return DAG.UpdateNodeOperands(SDValue(N, 0), Cond, N->getOperand(1),
N->getOperand(2));
}
-SDOperand DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
+SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
assert(OpNo == 0 && "Don't know how to promote this operand!");
- SDOperand LHS = N->getOperand(0);
- SDOperand RHS = N->getOperand(1);
+ SDValue LHS = N->getOperand(0);
+ SDValue RHS = N->getOperand(1);
PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
// The CC (#4) and the possible return values (#2 and #3) have legal types.
- return DAG.UpdateNodeOperands(SDOperand(N, 0), LHS, RHS, N->getOperand(2),
+ return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2),
N->getOperand(3), N->getOperand(4));
}
-SDOperand DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
+SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
assert(OpNo == 0 && "Don't know how to promote this operand!");
- SDOperand LHS = N->getOperand(0);
- SDOperand RHS = N->getOperand(1);
+ SDValue LHS = N->getOperand(0);
+ SDValue RHS = N->getOperand(1);
PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
// The CC (#2) is always legal.
- return DAG.UpdateNodeOperands(SDOperand(N, 0), LHS, RHS, N->getOperand(2));
+ return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2));
}
-SDOperand DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
- SDOperand Op = GetPromotedInteger(N->getOperand(0));
+SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
+ SDValue Op = GetPromotedInteger(N->getOperand(0));
Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(),
Op, DAG.getValueType(N->getOperand(0).getValueType()));
}
-SDOperand DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
+SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
- SDOperand Ch = N->getChain(), Ptr = N->getBasePtr();
+ SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
int SVOffset = N->getSrcValueOffset();
unsigned Alignment = N->getAlignment();
bool isVolatile = N->isVolatile();
- SDOperand Val = GetPromotedInteger(N->getValue()); // Get promoted value.
+ SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
assert(!N->isTruncatingStore() && "Cannot promote this store operand!");
@@ -789,13 +789,13 @@
isVolatile, Alignment);
}
-SDOperand DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
- SDOperand Op = GetPromotedInteger(N->getOperand(0));
+SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
+ SDValue Op = GetPromotedInteger(N->getOperand(0));
return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), Op);
}
-SDOperand DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
- SDOperand Op = GetPromotedInteger(N->getOperand(0));
+SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
+ SDValue Op = GetPromotedInteger(N->getOperand(0));
Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
return DAG.getZeroExtendInReg(Op, N->getOperand(0).getValueType());
}
@@ -811,8 +811,8 @@
/// know that (at least) one result needs expansion.
void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
DEBUG(cerr << "Expand integer result: "; N->dump(&DAG); cerr << "\n");
- SDOperand Lo, Hi;
- Lo = Hi = SDOperand();
+ SDValue Lo, Hi;
+ Lo = Hi = SDValue();
// See if the target wants to custom expand this node.
if (TLI.getOperationAction(N->getOpcode(), N->getValueType(ResNo)) ==
@@ -886,15 +886,15 @@
// If Lo/Hi is null, the sub-method took care of registering results etc.
if (Lo.Val)
- SetExpandedInteger(SDOperand(N, ResNo), Lo, Hi);
+ SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
}
/// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
/// and the shift amount is a constant 'Amt'. Expand the operation.
void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
- SDOperand &Lo, SDOperand &Hi) {
+ SDValue &Lo, SDValue &Hi) {
// Expand the incoming operand to be shifted, so that we have its parts
- SDOperand InL, InH;
+ SDValue InL, InH;
GetExpandedInteger(N->getOperand(0), InL, InH);
MVT NVT = InL.getValueType();
@@ -914,9 +914,9 @@
} else if (Amt == 1) {
// Emit this X << 1 as X+X.
SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
- SDOperand LoOps[2] = { InL, InL };
+ SDValue LoOps[2] = { InL, InL };
Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
- SDOperand HiOps[3] = { InH, InH, Lo.getValue(1) };
+ SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
} else {
Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt, ShTy));
@@ -978,8 +978,8 @@
/// can tell this, we know that it is >= 32 or < 32, without knowing the actual
/// shift amount.
bool DAGTypeLegalizer::
-ExpandShiftWithKnownAmountBit(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
- SDOperand Amt = N->getOperand(1);
+ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
+ SDValue Amt = N->getOperand(1);
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
MVT ShTy = Amt.getValueType();
unsigned ShBits = ShTy.getSizeInBits();
@@ -996,7 +996,7 @@
return false;
// Get the incoming operand to be shifted.
- SDOperand InL, InH;
+ SDValue InL, InH;
GetExpandedInteger(N->getOperand(0), InL, InH);
// If we know that any of the high bits of the shift amount are one, then we
@@ -1028,7 +1028,7 @@
// can do this as a couple of simple shifts.
if ((KnownZero & HighBitMask) == HighBitMask) {
// Compute 32-amt.
- SDOperand Amt2 = DAG.getNode(ISD::SUB, ShTy,
+ SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy,
DAG.getConstant(NVTBits, ShTy),
Amt);
unsigned Op1, Op2;
@@ -1050,14 +1050,14 @@
}
void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
- SDOperand &Lo, SDOperand &Hi) {
+ SDValue &Lo, SDValue &Hi) {
// Expand the subcomponents.
- SDOperand LHSL, LHSH, RHSL, RHSH;
+ SDValue LHSL, LHSH, RHSL, RHSH;
GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
- SDOperand LoOps[2] = { LHSL, RHSL };
- SDOperand HiOps[3] = { LHSH, RHSH };
+ SDValue LoOps[2] = { LHSL, RHSL };
+ SDValue HiOps[3] = { LHSH, RHSH };
if (N->getOpcode() == ISD::ADD) {
Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
@@ -1071,14 +1071,14 @@
}
void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
- SDOperand &Lo, SDOperand &Hi) {
+ SDValue &Lo, SDValue &Hi) {
// Expand the subcomponents.
- SDOperand LHSL, LHSH, RHSL, RHSH;
+ SDValue LHSL, LHSH, RHSL, RHSH;
GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
- SDOperand LoOps[2] = { LHSL, RHSL };
- SDOperand HiOps[3] = { LHSH, RHSH };
+ SDValue LoOps[2] = { LHSL, RHSL };
+ SDValue HiOps[3] = { LHSH, RHSH };
if (N->getOpcode() == ISD::ADDC) {
Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
@@ -1092,18 +1092,18 @@
// Legalized the flag result - switch anything that used the old flag to
// use the new one.
- ReplaceValueWith(SDOperand(N, 1), Hi.getValue(1));
+ ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
}
void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
- SDOperand &Lo, SDOperand &Hi) {
+ SDValue &Lo, SDValue &Hi) {
// Expand the subcomponents.
- SDOperand LHSL, LHSH, RHSL, RHSH;
+ SDValue LHSL, LHSH, RHSL, RHSH;
GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
- SDOperand LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
- SDOperand HiOps[3] = { LHSH, RHSH };
+ SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
+ SDValue HiOps[3] = { LHSH, RHSH };
Lo = DAG.getNode(N->getOpcode(), VTList, LoOps, 3);
HiOps[2] = Lo.getValue(1);
@@ -1111,13 +1111,13 @@
// Legalized the flag result - switch anything that used the old flag to
// use the new one.
- ReplaceValueWith(SDOperand(N, 1), Hi.getValue(1));
+ ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
}
void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
- SDOperand &Lo, SDOperand &Hi) {
+ SDValue &Lo, SDValue &Hi) {
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
- SDOperand Op = N->getOperand(0);
+ SDValue Op = N->getOperand(0);
if (Op.getValueType().bitsLE(NVT)) {
// The low part is any extension of the input (which degenerates to a copy).
Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Op);
@@ -1127,7 +1127,7 @@
// promotes to the result type, so will end up being expanded too.
assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
"Only know how to promote this result!");
- SDOperand Res = GetPromotedInteger(Op);
+ SDValue Res = GetPromotedInteger(Op);
assert(Res.getValueType() == N->getValueType(0) &&
"Operand over promoted?");
// Split the promoted operand. This will simplify when it is expanded.
@@ -1136,7 +1136,7 @@
}
void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
- SDOperand &Lo, SDOperand &Hi) {
+ SDValue &Lo, SDValue &Hi) {
GetExpandedInteger(N->getOperand(0), Lo, Hi);
MVT NVT = Lo.getValueType();
MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
@@ -1155,7 +1155,7 @@
}
void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
- SDOperand &Lo, SDOperand &Hi) {
+ SDValue &Lo, SDValue &Hi) {
GetExpandedInteger(N->getOperand(0), Lo, Hi);
MVT NVT = Lo.getValueType();
MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
@@ -1173,14 +1173,14 @@
}
void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
- SDOperand &Lo, SDOperand &Hi) {
+ SDValue &Lo, SDValue &Hi) {
GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
Lo = DAG.getNode(ISD::BSWAP, Lo.getValueType(), Lo);
Hi = DAG.getNode(ISD::BSWAP, Hi.getValueType(), Hi);
}
void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
- SDOperand &Lo, SDOperand &Hi) {
+ SDValue &Lo, SDValue &Hi) {
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
unsigned NBitWidth = NVT.getSizeInBits();
const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
@@ -1189,16 +1189,16 @@
}
void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
- SDOperand &Lo, SDOperand &Hi) {
+ SDValue &Lo, SDValue &Hi) {
// ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
GetExpandedInteger(N->getOperand(0), Lo, Hi);
MVT NVT = Lo.getValueType();
- SDOperand HiNotZero = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
+ SDValue HiNotZero = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
DAG.getConstant(0, NVT), ISD::SETNE);
- SDOperand LoLZ = DAG.getNode(ISD::CTLZ, NVT, Lo);
- SDOperand HiLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
+ SDValue LoLZ = DAG.getNode(ISD::CTLZ, NVT, Lo);
+ SDValue HiLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
Lo = DAG.getNode(ISD::SELECT, NVT, HiNotZero, HiLZ,
DAG.getNode(ISD::ADD, NVT, LoLZ,
@@ -1207,7 +1207,7 @@
}
void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
- SDOperand &Lo, SDOperand &Hi) {
+ SDValue &Lo, SDValue &Hi) {
// ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
GetExpandedInteger(N->getOperand(0), Lo, Hi);
MVT NVT = Lo.getValueType();
@@ -1217,16 +1217,16 @@
}
void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
- SDOperand &Lo, SDOperand &Hi) {
+ SDValue &Lo, SDValue &Hi) {
// cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
GetExpandedInteger(N->getOperand(0), Lo, Hi);
MVT NVT = Lo.getValueType();
- SDOperand LoNotZero = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo,
+ SDValue LoNotZero = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo,
DAG.getConstant(0, NVT), ISD::SETNE);
- SDOperand LoLZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
- SDOperand HiLZ = DAG.getNode(ISD::CTTZ, NVT, Hi);
+ SDValue LoLZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
+ SDValue HiLZ = DAG.getNode(ISD::CTTZ, NVT, Hi);
Lo = DAG.getNode(ISD::SELECT, NVT, LoNotZero, LoLZ,
DAG.getNode(ISD::ADD, NVT, HiLZ,
@@ -1234,26 +1234,26 @@
Hi = DAG.getConstant(0, NVT);
}
-void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDOperand &Lo,
- SDOperand &Hi) {
+void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
+ SDValue &Hi) {
MVT VT = N->getValueType(0);
- SDOperand Op = N->getOperand(0);
+ SDValue Op = N->getOperand(0);
RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*sign irrelevant*/), Lo, Hi);
}
-void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDOperand &Lo,
- SDOperand &Hi) {
+void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
+ SDValue &Hi) {
MVT VT = N->getValueType(0);
- SDOperand Op = N->getOperand(0);
+ SDValue Op = N->getOperand(0);
RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*sign irrelevant*/), Lo, Hi);
}
void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
- SDOperand &Lo, SDOperand &Hi) {
+ SDValue &Lo, SDValue &Hi) {
if (ISD::isNormalLoad(N)) {
ExpandRes_NormalLoad(N, Lo, Hi);
return;
@@ -1263,8 +1263,8 @@
MVT VT = N->getValueType(0);
MVT NVT = TLI.getTypeToTransformTo(VT);
- SDOperand Ch = N->getChain();
- SDOperand Ptr = N->getBasePtr();
+ SDValue Ch = N->getChain();
+ SDValue Ptr = N->getBasePtr();
ISD::LoadExtType ExtType = N->getExtensionType();
int SVOffset = N->getSrcValueOffset();
unsigned Alignment = N->getAlignment();
@@ -1358,12 +1358,12 @@
// Legalized the chain result - switch anything that used the old chain to
// use the new one.
- ReplaceValueWith(SDOperand(N, 1), Ch);
+ ReplaceValueWith(SDValue(N, 1), Ch);
}
void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
- SDOperand &Lo, SDOperand &Hi) {
- SDOperand LL, LH, RL, RH;
+ SDValue &Lo, SDValue &Hi) {
+ SDValue LL, LH, RL, RH;
GetExpandedInteger(N->getOperand(0), LL, LH);
GetExpandedInteger(N->getOperand(1), RL, RH);
Lo = DAG.getNode(N->getOpcode(), LL.getValueType(), LL, RL);
@@ -1371,7 +1371,7 @@
}
void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
- SDOperand &Lo, SDOperand &Hi) {
+ SDValue &Lo, SDValue &Hi) {
MVT VT = N->getValueType(0);
MVT NVT = TLI.getTypeToTransformTo(VT);
@@ -1380,7 +1380,7 @@
bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
- SDOperand LL, LH, RL, RH;
+ SDValue LL, LH, RL, RH;
GetExpandedInteger(N->getOperand(0), LL, LH);
GetExpandedInteger(N->getOperand(1), RL, RH);
unsigned OuterBitSize = VT.getSizeInBits();
@@ -1395,7 +1395,7 @@
if (HasUMUL_LOHI) {
// We can emit a umul_lohi.
Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
- Hi = SDOperand(Lo.Val, 1);
+ Hi = SDValue(Lo.Val, 1);
return;
}
if (HasMULHU) {
@@ -1410,7 +1410,7 @@
if (HasSMUL_LOHI) {
// We can emit a smul_lohi.
Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
- Hi = SDOperand(Lo.Val, 1);
+ Hi = SDValue(Lo.Val, 1);
return;
}
if (HasMULHS) {
@@ -1422,7 +1422,7 @@
}
if (HasUMUL_LOHI) {
// Lo,Hi = umul LHS, RHS.
- SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
+ SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
DAG.getVTList(NVT, NVT), LL, RL);
Lo = UMulLOHI;
Hi = UMulLOHI.getValue(1);
@@ -1453,12 +1453,12 @@
LC = RTLIB::MUL_I128;
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
- SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
+ SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*sign irrelevant*/), Lo, Hi);
}
void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
- SDOperand &Lo, SDOperand &Hi) {
+ SDValue &Lo, SDValue &Hi) {
MVT VT = N->getValueType(0);
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
@@ -1470,12 +1470,12 @@
LC = RTLIB::SDIV_I128;
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
- SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
+ SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
SplitInteger(MakeLibCall(LC, VT, Ops, 2, true), Lo, Hi);
}
void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
- SDOperand &Lo, SDOperand &Hi) {
+ SDValue &Lo, SDValue &Hi) {
MVT VT = N->getValueType(0);
// If we can emit an efficient shift operation, do so now. Check to see if
@@ -1506,10 +1506,10 @@
if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
Action == TargetLowering::Custom) {
// Expand the subcomponents.
- SDOperand LHSL, LHSH;
+ SDValue LHSL, LHSH;
GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
- SDOperand Ops[] = { LHSL, LHSH, N->getOperand(1) };
+ SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) };
MVT VT = LHSL.getValueType();
Lo = DAG.getNode(PartsOpc, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
Hi = Lo.getValue(1);
@@ -1547,14 +1547,14 @@
}
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported shift!");
- SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
+ SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned), Lo, Hi);
}
void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
- SDOperand &Lo, SDOperand &Hi) {
+ SDValue &Lo, SDValue &Hi) {
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
- SDOperand Op = N->getOperand(0);
+ SDValue Op = N->getOperand(0);
if (Op.getValueType().bitsLE(NVT)) {
// The low part is sign extension of the input (which degenerates to a copy).
Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, N->getOperand(0));
@@ -1567,7 +1567,7 @@
// promotes to the result type, so will end up being expanded too.
assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
"Only know how to promote this result!");
- SDOperand Res = GetPromotedInteger(Op);
+ SDValue Res = GetPromotedInteger(Op);
assert(Res.getValueType() == N->getValueType(0) &&
"Operand over promoted?");
// Split the promoted operand. This will simplify when it is expanded.
@@ -1580,7 +1580,7 @@
}
void DAGTypeLegalizer::
-ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
+ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
GetExpandedInteger(N->getOperand(0), Lo, Hi);
MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
@@ -1605,7 +1605,7 @@
}
void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
- SDOperand &Lo, SDOperand &Hi) {
+ SDValue &Lo, SDValue &Hi) {
MVT VT = N->getValueType(0);
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
@@ -1617,12 +1617,12 @@
LC = RTLIB::SREM_I128;
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
- SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
+ SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
SplitInteger(MakeLibCall(LC, VT, Ops, 2, true), Lo, Hi);
}
void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
- SDOperand &Lo, SDOperand &Hi) {
+ SDValue &Lo, SDValue &Hi) {
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
Lo = DAG.getNode(ISD::TRUNCATE, NVT, N->getOperand(0));
Hi = DAG.getNode(ISD::SRL, N->getOperand(0).getValueType(), N->getOperand(0),
@@ -1632,7 +1632,7 @@
}
void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
- SDOperand &Lo, SDOperand &Hi) {
+ SDValue &Lo, SDValue &Hi) {
MVT VT = N->getValueType(0);
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
@@ -1644,12 +1644,12 @@
LC = RTLIB::UDIV_I128;
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
- SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
+ SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
SplitInteger(MakeLibCall(LC, VT, Ops, 2, false), Lo, Hi);
}
void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
- SDOperand &Lo, SDOperand &Hi) {
+ SDValue &Lo, SDValue &Hi) {
MVT VT = N->getValueType(0);
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
@@ -1661,14 +1661,14 @@
LC = RTLIB::UREM_I128;
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
- SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
+ SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
SplitInteger(MakeLibCall(LC, VT, Ops, 2, false), Lo, Hi);
}
void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
- SDOperand &Lo, SDOperand &Hi) {
+ SDValue &Lo, SDValue &Hi) {
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
- SDOperand Op = N->getOperand(0);
+ SDValue Op = N->getOperand(0);
if (Op.getValueType().bitsLE(NVT)) {
// The low part is zero extension of the input (which degenerates to a copy).
Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, N->getOperand(0));
@@ -1678,7 +1678,7 @@
// promotes to the result type, so will end up being expanded too.
assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
"Only know how to promote this result!");
- SDOperand Res = GetPromotedInteger(Op);
+ SDValue Res = GetPromotedInteger(Op);
assert(Res.getValueType() == N->getValueType(0) &&
"Operand over promoted?");
// Split the promoted operand. This will simplify when it is expanded.
@@ -1700,11 +1700,11 @@
/// node may need promotion or expansion as well as the specified one.
bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
DEBUG(cerr << "Expand integer operand: "; N->dump(&DAG); cerr << "\n");
- SDOperand Res = SDOperand();
+ SDValue Res = SDValue();
if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType())
== TargetLowering::Custom)
- Res = TLI.LowerOperation(SDOperand(N, OpNo), DAG);
+ Res = TLI.LowerOperation(SDValue(N, OpNo), DAG);
if (Res.Val == 0) {
switch (N->getOpcode()) {
@@ -1746,16 +1746,16 @@
assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
"Invalid operand expansion");
- ReplaceValueWith(SDOperand(N, 0), Res);
+ ReplaceValueWith(SDValue(N, 0), Res);
return false;
}
/// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
/// is shared among BR_CC, SELECT_CC, and SETCC handlers.
-void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDOperand &NewLHS,
- SDOperand &NewRHS,
+void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
+ SDValue &NewRHS,
ISD::CondCode &CCCode) {
- SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
+ SDValue LHSLo, LHSHi, RHSLo, RHSHi;
GetExpandedInteger(NewLHS, LHSLo, LHSHi);
GetExpandedInteger(NewRHS, RHSLo, RHSHi);
@@ -1811,7 +1811,7 @@
// NOTE: on targets without efficient SELECT of bools, we can always use
// this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
- SDOperand Tmp1, Tmp2;
+ SDValue Tmp1, Tmp2;
Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC,
false, DagCombineInfo);
if (!Tmp1.Val)
@@ -1835,7 +1835,7 @@
// For LE / GE, if high part is known false, ignore the low part.
// For LT / GT, if high part is known true, ignore the low part.
NewLHS = Tmp2;
- NewRHS = SDOperand();
+ NewRHS = SDValue();
return;
}
@@ -1846,11 +1846,11 @@
ISD::SETEQ);
NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
NewLHS, Tmp1, Tmp2);
- NewRHS = SDOperand();
+ NewRHS = SDValue();
}
-SDOperand DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
- SDOperand NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
+SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
+ SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
@@ -1862,13 +1862,13 @@
}
// Update N to have the operands specified.
- return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
+ return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
DAG.getCondCode(CCCode), NewLHS, NewRHS,
N->getOperand(4));
}
-SDOperand DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
- SDOperand NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
+SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
+ SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
@@ -1880,13 +1880,13 @@
}
// Update N to have the operands specified.
- return DAG.UpdateNodeOperands(SDOperand(N, 0), NewLHS, NewRHS,
+ return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
N->getOperand(2), N->getOperand(3),
DAG.getCondCode(CCCode));
}
-SDOperand DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
- SDOperand NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
+SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
+ SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
@@ -1898,12 +1898,12 @@
}
// Otherwise, update N to have the operands specified.
- return DAG.UpdateNodeOperands(SDOperand(N, 0), NewLHS, NewRHS,
+ return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
DAG.getCondCode(CCCode));
}
-SDOperand DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
- SDOperand Op = N->getOperand(0);
+SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
+ SDValue Op = N->getOperand(0);
MVT DstVT = N->getValueType(0);
RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
assert(LC != RTLIB::UNKNOWN_LIBCALL &&
@@ -1911,7 +1911,7 @@
return MakeLibCall(LC, DstVT, &Op, 1, true);
}
-SDOperand DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
+SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
if (ISD::isNormalStore(N))
return ExpandOp_NormalStore(N, OpNo);
@@ -1920,12 +1920,12 @@
MVT VT = N->getOperand(1).getValueType();
MVT NVT = TLI.getTypeToTransformTo(VT);
- SDOperand Ch = N->getChain();
- SDOperand Ptr = N->getBasePtr();
+ SDValue Ch = N->getChain();
+ SDValue Ptr = N->getBasePtr();
int SVOffset = N->getSrcValueOffset();
unsigned Alignment = N->getAlignment();
bool isVolatile = N->isVolatile();
- SDOperand Lo, Hi;
+ SDValue Lo, Hi;
assert(NVT.isByteSized() && "Expanded type not byte sized!");
@@ -1990,21 +1990,21 @@
}
}
-SDOperand DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
- SDOperand InL, InH;
+SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
+ SDValue InL, InH;
GetExpandedInteger(N->getOperand(0), InL, InH);
// Just truncate the low part of the source.
return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), InL);
}
-SDOperand DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
- SDOperand Op = N->getOperand(0);
+SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
+ SDValue Op = N->getOperand(0);
MVT SrcVT = Op.getValueType();
MVT DstVT = N->getValueType(0);
if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
// Do a signed conversion then adjust the result.
- SDOperand SignedConv = DAG.getNode(ISD::SINT_TO_FP, DstVT, Op);
+ SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, DstVT, Op);
SignedConv = TLI.LowerOperation(SignedConv, DAG);
// The result of the signed conversion needs adjusting if the 'sign bit' of
@@ -2026,27 +2026,27 @@
assert(false && "Unsupported UINT_TO_FP!");
// Check whether the sign bit is set.
- SDOperand Lo, Hi;
+ SDValue Lo, Hi;
GetExpandedInteger(Op, Lo, Hi);
- SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
+ SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
DAG.getConstant(0, Hi.getValueType()),
ISD::SETLT);
// Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
- SDOperand FudgePtr = DAG.getConstantPool(ConstantInt::get(FF.zext(64)),
+ SDValue FudgePtr = DAG.getConstantPool(ConstantInt::get(FF.zext(64)),
TLI.getPointerTy());
// Get a pointer to FF if the sign bit was set, or to 0 otherwise.
- SDOperand Zero = DAG.getIntPtrConstant(0);
- SDOperand Four = DAG.getIntPtrConstant(4);
+ SDValue Zero = DAG.getIntPtrConstant(0);
+ SDValue Four = DAG.getIntPtrConstant(4);
if (TLI.isBigEndian()) std::swap(Zero, Four);
- SDOperand Offset = DAG.getNode(ISD::SELECT, Zero.getValueType(), SignSet,
+ SDValue Offset = DAG.getNode(ISD::SELECT, Zero.getValueType(), SignSet,
Zero, Four);
FudgePtr = DAG.getNode(ISD::ADD, TLI.getPointerTy(), FudgePtr, Offset);
// Load the value out, extending it from f32 to the destination float type.
// FIXME: Avoid the extend by constructing the right constant pool?
- SDOperand Fudge = DAG.getExtLoad(ISD::EXTLOAD, DstVT, DAG.getEntryNode(),
+ SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, DstVT, DAG.getEntryNode(),
FudgePtr, NULL, 0, MVT::f32);
return DAG.getNode(ISD::FADD, DstVT, SignedConv, Fudge);
}
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Sun Jul 27 16:46:04 2008
@@ -29,7 +29,7 @@
// The root of the dag may dangle to deleted nodes until the type legalizer is
// done. Set it to null to avoid confusion.
- DAG.setRoot(SDOperand());
+ DAG.setRoot(SDValue());
// Walk all nodes in the graph, assigning them a NodeID of 'ReadyToProcess'
// (and remembering them) if they are leaves and assigning 'NewNode' if
@@ -239,11 +239,11 @@
// replaced them, which can result in our node changing. Since remapping
// is rare, the code tries to minimize overhead in the non-remapping case.
- SmallVector<SDOperand, 8> NewOps;
+ SmallVector<SDValue, 8> NewOps;
unsigned NumProcessed = 0;
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
- SDOperand OrigOp = N->getOperand(i);
- SDOperand Op = OrigOp;
+ SDValue OrigOp = N->getOperand(i);
+ SDValue Op = OrigOp;
if (Op.Val->getNodeId() == Processed)
RemapNode(Op);
@@ -266,7 +266,7 @@
// Some operands changed - update the node.
if (!NewOps.empty())
- N = DAG.UpdateNodeOperands(SDOperand(N, 0), &NewOps[0], NewOps.size()).Val;
+ N = DAG.UpdateNodeOperands(SDValue(N, 0), &NewOps[0], NewOps.size()).Val;
N->setNodeId(N->getNumOperands()-NumProcessed);
if (N->getNodeId() == ReadyToProcess)
@@ -308,7 +308,7 @@
/// ReplaceValueWith - The specified value was legalized to the specified other
/// value. If they are different, update the DAG and NodeIDs replacing any uses
/// of From to use To instead.
-void DAGTypeLegalizer::ReplaceValueWith(SDOperand From, SDOperand To) {
+void DAGTypeLegalizer::ReplaceValueWith(SDValue From, SDValue To) {
if (From == To) return;
// If expansion produced new nodes, make sure they are properly marked.
@@ -347,14 +347,14 @@
for (unsigned i = 0, e = From->getNumValues(); i != e; ++i) {
assert(From->getValueType(i) == To->getValueType(i) &&
"Node results don't match");
- ReplacedNodes[SDOperand(From, i)] = SDOperand(To, i);
+ ReplacedNodes[SDValue(From, i)] = SDValue(To, i);
}
}
/// RemapNode - If the specified value was already legalized to another value,
/// replace it by that value.
-void DAGTypeLegalizer::RemapNode(SDOperand &N) {
- DenseMap<SDOperand, SDOperand>::iterator I = ReplacedNodes.find(N);
+void DAGTypeLegalizer::RemapNode(SDValue &N) {
+ DenseMap<SDValue, SDValue>::iterator I = ReplacedNodes.find(N);
if (I != ReplacedNodes.end()) {
// Use path compression to speed up future lookups if values get multiply
// replaced with other values.
@@ -383,7 +383,7 @@
// If N is not remapped by ReplacedNodes then there is nothing to do.
unsigned i, e;
for (i = 0, e = N->getNumValues(); i != e; ++i)
- if (ReplacedNodes.find(SDOperand(N, i)) != ReplacedNodes.end())
+ if (ReplacedNodes.find(SDValue(N, i)) != ReplacedNodes.end())
break;
if (i == e)
@@ -391,80 +391,80 @@
// Remove N from all maps - this is expensive but rare.
- for (DenseMap<SDOperand, SDOperand>::iterator I = PromotedIntegers.begin(),
+ for (DenseMap<SDValue, SDValue>::iterator I = PromotedIntegers.begin(),
E = PromotedIntegers.end(); I != E; ++I) {
assert(I->first.Val != N);
RemapNode(I->second);
}
- for (DenseMap<SDOperand, SDOperand>::iterator I = SoftenedFloats.begin(),
+ for (DenseMap<SDValue, SDValue>::iterator I = SoftenedFloats.begin(),
E = SoftenedFloats.end(); I != E; ++I) {
assert(I->first.Val != N);
RemapNode(I->second);
}
- for (DenseMap<SDOperand, SDOperand>::iterator I = ScalarizedVectors.begin(),
+ for (DenseMap<SDValue, SDValue>::iterator I = ScalarizedVectors.begin(),
E = ScalarizedVectors.end(); I != E; ++I) {
assert(I->first.Val != N);
RemapNode(I->second);
}
- for (DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator
+ for (DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator
I = ExpandedIntegers.begin(), E = ExpandedIntegers.end(); I != E; ++I){
assert(I->first.Val != N);
RemapNode(I->second.first);
RemapNode(I->second.second);
}
- for (DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator
+ for (DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator
I = ExpandedFloats.begin(), E = ExpandedFloats.end(); I != E; ++I) {
assert(I->first.Val != N);
RemapNode(I->second.first);
RemapNode(I->second.second);
}
- for (DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator
+ for (DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator
I = SplitVectors.begin(), E = SplitVectors.end(); I != E; ++I) {
assert(I->first.Val != N);
RemapNode(I->second.first);
RemapNode(I->second.second);
}
- for (DenseMap<SDOperand, SDOperand>::iterator I = ReplacedNodes.begin(),
+ for (DenseMap<SDValue, SDValue>::iterator I = ReplacedNodes.begin(),
E = ReplacedNodes.end(); I != E; ++I)
RemapNode(I->second);
for (unsigned i = 0, e = N->getNumValues(); i != e; ++i)
- ReplacedNodes.erase(SDOperand(N, i));
+ ReplacedNodes.erase(SDValue(N, i));
}
-void DAGTypeLegalizer::SetPromotedInteger(SDOperand Op, SDOperand Result) {
+void DAGTypeLegalizer::SetPromotedInteger(SDValue Op, SDValue Result) {
AnalyzeNewNode(Result.Val);
- SDOperand &OpEntry = PromotedIntegers[Op];
+ SDValue &OpEntry = PromotedIntegers[Op];
assert(OpEntry.Val == 0 && "Node is already promoted!");
OpEntry = Result;
}
-void DAGTypeLegalizer::SetSoftenedFloat(SDOperand Op, SDOperand Result) {
+void DAGTypeLegalizer::SetSoftenedFloat(SDValue Op, SDValue Result) {
AnalyzeNewNode(Result.Val);
- SDOperand &OpEntry = SoftenedFloats[Op];
+ SDValue &OpEntry = SoftenedFloats[Op];
assert(OpEntry.Val == 0 && "Node is already converted to integer!");
OpEntry = Result;
}
-void DAGTypeLegalizer::SetScalarizedVector(SDOperand Op, SDOperand Result) {
+void DAGTypeLegalizer::SetScalarizedVector(SDValue Op, SDValue Result) {
AnalyzeNewNode(Result.Val);
- SDOperand &OpEntry = ScalarizedVectors[Op];
+ SDValue &OpEntry = ScalarizedVectors[Op];
assert(OpEntry.Val == 0 && "Node is already scalarized!");
OpEntry = Result;
}
-void DAGTypeLegalizer::GetExpandedInteger(SDOperand Op, SDOperand &Lo,
- SDOperand &Hi) {
- std::pair<SDOperand, SDOperand> &Entry = ExpandedIntegers[Op];
+void DAGTypeLegalizer::GetExpandedInteger(SDValue Op, SDValue &Lo,
+ SDValue &Hi) {
+ std::pair<SDValue, SDValue> &Entry = ExpandedIntegers[Op];
RemapNode(Entry.first);
RemapNode(Entry.second);
assert(Entry.first.Val && "Operand isn't expanded");
@@ -472,22 +472,22 @@
Hi = Entry.second;
}
-void DAGTypeLegalizer::SetExpandedInteger(SDOperand Op, SDOperand Lo,
- SDOperand Hi) {
+void DAGTypeLegalizer::SetExpandedInteger(SDValue Op, SDValue Lo,
+ SDValue Hi) {
// Lo/Hi may have been newly allocated, if so, add nodeid's as relevant.
AnalyzeNewNode(Lo.Val);
AnalyzeNewNode(Hi.Val);
// Remember that this is the result of the node.
- std::pair<SDOperand, SDOperand> &Entry = ExpandedIntegers[Op];
+ std::pair<SDValue, SDValue> &Entry = ExpandedIntegers[Op];
assert(Entry.first.Val == 0 && "Node already expanded");
Entry.first = Lo;
Entry.second = Hi;
}
-void DAGTypeLegalizer::GetExpandedFloat(SDOperand Op, SDOperand &Lo,
- SDOperand &Hi) {
- std::pair<SDOperand, SDOperand> &Entry = ExpandedFloats[Op];
+void DAGTypeLegalizer::GetExpandedFloat(SDValue Op, SDValue &Lo,
+ SDValue &Hi) {
+ std::pair<SDValue, SDValue> &Entry = ExpandedFloats[Op];
RemapNode(Entry.first);
RemapNode(Entry.second);
assert(Entry.first.Val && "Operand isn't expanded");
@@ -495,22 +495,22 @@
Hi = Entry.second;
}
-void DAGTypeLegalizer::SetExpandedFloat(SDOperand Op, SDOperand Lo,
- SDOperand Hi) {
+void DAGTypeLegalizer::SetExpandedFloat(SDValue Op, SDValue Lo,
+ SDValue Hi) {
// Lo/Hi may have been newly allocated, if so, add nodeid's as relevant.
AnalyzeNewNode(Lo.Val);
AnalyzeNewNode(Hi.Val);
// Remember that this is the result of the node.
- std::pair<SDOperand, SDOperand> &Entry = ExpandedFloats[Op];
+ std::pair<SDValue, SDValue> &Entry = ExpandedFloats[Op];
assert(Entry.first.Val == 0 && "Node already expanded");
Entry.first = Lo;
Entry.second = Hi;
}
-void DAGTypeLegalizer::GetSplitVector(SDOperand Op, SDOperand &Lo,
- SDOperand &Hi) {
- std::pair<SDOperand, SDOperand> &Entry = SplitVectors[Op];
+void DAGTypeLegalizer::GetSplitVector(SDValue Op, SDValue &Lo,
+ SDValue &Hi) {
+ std::pair<SDValue, SDValue> &Entry = SplitVectors[Op];
RemapNode(Entry.first);
RemapNode(Entry.second);
assert(Entry.first.Val && "Operand isn't split");
@@ -518,14 +518,14 @@
Hi = Entry.second;
}
-void DAGTypeLegalizer::SetSplitVector(SDOperand Op, SDOperand Lo,
- SDOperand Hi) {
+void DAGTypeLegalizer::SetSplitVector(SDValue Op, SDValue Lo,
+ SDValue Hi) {
// Lo/Hi may have been newly allocated, if so, add nodeid's as relevant.
AnalyzeNewNode(Lo.Val);
AnalyzeNewNode(Hi.Val);
// Remember that this is the result of the node.
- std::pair<SDOperand, SDOperand> &Entry = SplitVectors[Op];
+ std::pair<SDValue, SDValue> &Entry = SplitVectors[Op];
assert(Entry.first.Val == 0 && "Node already split");
Entry.first = Lo;
Entry.second = Hi;
@@ -537,27 +537,27 @@
//===----------------------------------------------------------------------===//
/// BitConvertToInteger - Convert to an integer of the same size.
-SDOperand DAGTypeLegalizer::BitConvertToInteger(SDOperand Op) {
+SDValue DAGTypeLegalizer::BitConvertToInteger(SDValue Op) {
unsigned BitWidth = Op.getValueType().getSizeInBits();
return DAG.getNode(ISD::BIT_CONVERT, MVT::getIntegerVT(BitWidth), Op);
}
-SDOperand DAGTypeLegalizer::CreateStackStoreLoad(SDOperand Op,
- MVT DestVT) {
+SDValue DAGTypeLegalizer::CreateStackStoreLoad(SDValue Op,
+ MVT DestVT) {
// Create the stack frame object. Make sure it is aligned for both
// the source and destination types.
unsigned SrcAlign =
TLI.getTargetData()->getPrefTypeAlignment(Op.getValueType().getTypeForMVT());
- SDOperand FIPtr = DAG.CreateStackTemporary(DestVT, SrcAlign);
+ SDValue FIPtr = DAG.CreateStackTemporary(DestVT, SrcAlign);
// Emit a store to the stack slot.
- SDOperand Store = DAG.getStore(DAG.getEntryNode(), Op, FIPtr, NULL, 0);
+ SDValue Store = DAG.getStore(DAG.getEntryNode(), Op, FIPtr, NULL, 0);
// Result is a load from the stack slot.
return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
}
/// JoinIntegers - Build an integer with low bits Lo and high bits Hi.
-SDOperand DAGTypeLegalizer::JoinIntegers(SDOperand Lo, SDOperand Hi) {
+SDValue DAGTypeLegalizer::JoinIntegers(SDValue Lo, SDValue Hi) {
MVT LVT = Lo.getValueType();
MVT HVT = Hi.getValueType();
MVT NVT = MVT::getIntegerVT(LVT.getSizeInBits() + HVT.getSizeInBits());
@@ -571,9 +571,9 @@
/// SplitInteger - Return the lower LoVT bits of Op in Lo and the upper HiVT
/// bits in Hi.
-void DAGTypeLegalizer::SplitInteger(SDOperand Op,
+void DAGTypeLegalizer::SplitInteger(SDValue Op,
MVT LoVT, MVT HiVT,
- SDOperand &Lo, SDOperand &Hi) {
+ SDValue &Lo, SDValue &Hi) {
assert(LoVT.getSizeInBits() + HiVT.getSizeInBits() ==
Op.getValueType().getSizeInBits() && "Invalid integer splitting!");
Lo = DAG.getNode(ISD::TRUNCATE, LoVT, Op);
@@ -585,17 +585,17 @@
/// SplitInteger - Return the lower and upper halves of Op's bits in a value type
/// half the size of Op's.
-void DAGTypeLegalizer::SplitInteger(SDOperand Op,
- SDOperand &Lo, SDOperand &Hi) {
+void DAGTypeLegalizer::SplitInteger(SDValue Op,
+ SDValue &Lo, SDValue &Hi) {
MVT HalfVT = MVT::getIntegerVT(Op.getValueType().getSizeInBits()/2);
SplitInteger(Op, HalfVT, HalfVT, Lo, Hi);
}
/// MakeLibCall - Generate a libcall taking the given operands as arguments and
/// returning a result of type RetVT.
-SDOperand DAGTypeLegalizer::MakeLibCall(RTLIB::Libcall LC, MVT RetVT,
- const SDOperand *Ops, unsigned NumOps,
- bool isSigned) {
+SDValue DAGTypeLegalizer::MakeLibCall(RTLIB::Libcall LC, MVT RetVT,
+ const SDValue *Ops, unsigned NumOps,
+ bool isSigned) {
TargetLowering::ArgListTy Args;
Args.reserve(NumOps);
@@ -607,18 +607,18 @@
Entry.isZExt = !isSigned;
Args.push_back(Entry);
}
- SDOperand Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
+ SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
TLI.getPointerTy());
const Type *RetTy = RetVT.getTypeForMVT();
- std::pair<SDOperand,SDOperand> CallInfo =
+ std::pair<SDValue,SDValue> CallInfo =
TLI.LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
CallingConv::C, false, Callee, Args, DAG);
return CallInfo.first;
}
-SDOperand DAGTypeLegalizer::GetVectorElementPointer(SDOperand VecPtr, MVT EltVT,
- SDOperand Index) {
+SDValue DAGTypeLegalizer::GetVectorElementPointer(SDValue VecPtr, MVT EltVT,
+ SDValue Index) {
// Make sure the index type is big enough to compute in.
if (Index.getValueType().bitsGT(TLI.getPointerTy()))
Index = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Index);
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Sun Jul 27 16:46:04 2008
@@ -112,31 +112,31 @@
/// PromotedIntegers - For integer nodes that are below legal width, this map
/// indicates what promoted value to use.
- DenseMap<SDOperand, SDOperand> PromotedIntegers;
+ DenseMap<SDValue, SDValue> PromotedIntegers;
/// ExpandedIntegers - For integer nodes that need to be expanded this map
/// indicates which operands are the expanded version of the input.
- DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedIntegers;
+ DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedIntegers;
/// SoftenedFloats - For floating point nodes converted to integers of
/// the same size, this map indicates the converted value to use.
- DenseMap<SDOperand, SDOperand> SoftenedFloats;
+ DenseMap<SDValue, SDValue> SoftenedFloats;
/// ExpandedFloats - For float nodes that need to be expanded this map
/// indicates which operands are the expanded version of the input.
- DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedFloats;
+ DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedFloats;
/// ScalarizedVectors - For nodes that are <1 x ty>, this map indicates the
/// scalar value of type 'ty' to use.
- DenseMap<SDOperand, SDOperand> ScalarizedVectors;
+ DenseMap<SDValue, SDValue> ScalarizedVectors;
/// SplitVectors - For nodes that need to be split this map indicates
/// which operands are the expanded version of the input.
- DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > SplitVectors;
+ DenseMap<SDValue, std::pair<SDValue, SDValue> > SplitVectors;
/// ReplacedNodes - For nodes that have been replaced with another,
/// indicates the replacement node to use.
- DenseMap<SDOperand, SDOperand> ReplacedNodes;
+ DenseMap<SDValue, SDValue> ReplacedNodes;
/// Worklist - This defines a worklist of nodes to process. In order to be
/// pushed onto this worklist, all operands of a node must have already been
@@ -164,47 +164,47 @@
ExpungeNode(Old);
ExpungeNode(New);
for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i)
- ReplacedNodes[SDOperand(Old, i)] = SDOperand(New, i);
+ ReplacedNodes[SDValue(Old, i)] = SDValue(New, i);
}
private:
void AnalyzeNewNode(SDNode *&N);
- void ReplaceValueWith(SDOperand From, SDOperand To);
+ void ReplaceValueWith(SDValue From, SDValue To);
void ReplaceNodeWith(SDNode *From, SDNode *To);
- void RemapNode(SDOperand &N);
+ void RemapNode(SDValue &N);
void ExpungeNode(SDNode *N);
// Common routines.
- SDOperand CreateStackStoreLoad(SDOperand Op, MVT DestVT);
- SDOperand MakeLibCall(RTLIB::Libcall LC, MVT RetVT,
- const SDOperand *Ops, unsigned NumOps, bool isSigned);
-
- SDOperand BitConvertToInteger(SDOperand Op);
- SDOperand JoinIntegers(SDOperand Lo, SDOperand Hi);
- void SplitInteger(SDOperand Op, SDOperand &Lo, SDOperand &Hi);
- void SplitInteger(SDOperand Op, MVT LoVT, MVT HiVT,
- SDOperand &Lo, SDOperand &Hi);
+ SDValue CreateStackStoreLoad(SDValue Op, MVT DestVT);
+ SDValue MakeLibCall(RTLIB::Libcall LC, MVT RetVT,
+ const SDValue *Ops, unsigned NumOps, bool isSigned);
+
+ SDValue BitConvertToInteger(SDValue Op);
+ SDValue JoinIntegers(SDValue Lo, SDValue Hi);
+ void SplitInteger(SDValue Op, SDValue &Lo, SDValue &Hi);
+ void SplitInteger(SDValue Op, MVT LoVT, MVT HiVT,
+ SDValue &Lo, SDValue &Hi);
- SDOperand GetVectorElementPointer(SDOperand VecPtr, MVT EltVT,
- SDOperand Index);
+ SDValue GetVectorElementPointer(SDValue VecPtr, MVT EltVT,
+ SDValue Index);
//===--------------------------------------------------------------------===//
// Integer Promotion Support: LegalizeIntegerTypes.cpp
//===--------------------------------------------------------------------===//
- SDOperand GetPromotedInteger(SDOperand Op) {
- SDOperand &PromotedOp = PromotedIntegers[Op];
+ SDValue GetPromotedInteger(SDValue Op) {
+ SDValue &PromotedOp = PromotedIntegers[Op];
RemapNode(PromotedOp);
assert(PromotedOp.Val && "Operand wasn't promoted?");
return PromotedOp;
}
- void SetPromotedInteger(SDOperand Op, SDOperand Result);
+ void SetPromotedInteger(SDValue Op, SDValue Result);
/// ZExtPromotedInteger - Get a promoted operand and zero extend it to the
/// final size.
- SDOperand ZExtPromotedInteger(SDOperand Op) {
+ SDValue ZExtPromotedInteger(SDValue Op) {
MVT OldVT = Op.getValueType();
Op = GetPromotedInteger(Op);
return DAG.getZeroExtendInReg(Op, OldVT);
@@ -212,251 +212,251 @@
// Integer Result Promotion.
void PromoteIntegerResult(SDNode *N, unsigned ResNo);
- SDOperand PromoteIntRes_AssertSext(SDNode *N);
- SDOperand PromoteIntRes_AssertZext(SDNode *N);
- SDOperand PromoteIntRes_BIT_CONVERT(SDNode *N);
- SDOperand PromoteIntRes_BSWAP(SDNode *N);
- SDOperand PromoteIntRes_BUILD_PAIR(SDNode *N);
- SDOperand PromoteIntRes_Constant(SDNode *N);
- SDOperand PromoteIntRes_CTLZ(SDNode *N);
- SDOperand PromoteIntRes_CTPOP(SDNode *N);
- SDOperand PromoteIntRes_CTTZ(SDNode *N);
- SDOperand PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N);
- SDOperand PromoteIntRes_FP_TO_XINT(SDNode *N);
- SDOperand PromoteIntRes_INT_EXTEND(SDNode *N);
- SDOperand PromoteIntRes_LOAD(LoadSDNode *N);
- SDOperand PromoteIntRes_SDIV(SDNode *N);
- SDOperand PromoteIntRes_SELECT (SDNode *N);
- SDOperand PromoteIntRes_SELECT_CC(SDNode *N);
- SDOperand PromoteIntRes_SETCC(SDNode *N);
- SDOperand PromoteIntRes_SHL(SDNode *N);
- SDOperand PromoteIntRes_SimpleIntBinOp(SDNode *N);
- SDOperand PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N);
- SDOperand PromoteIntRes_SRA(SDNode *N);
- SDOperand PromoteIntRes_SRL(SDNode *N);
- SDOperand PromoteIntRes_TRUNCATE(SDNode *N);
- SDOperand PromoteIntRes_UDIV(SDNode *N);
- SDOperand PromoteIntRes_UNDEF(SDNode *N);
- SDOperand PromoteIntRes_VAARG(SDNode *N);
+ SDValue PromoteIntRes_AssertSext(SDNode *N);
+ SDValue PromoteIntRes_AssertZext(SDNode *N);
+ SDValue PromoteIntRes_BIT_CONVERT(SDNode *N);
+ SDValue PromoteIntRes_BSWAP(SDNode *N);
+ SDValue PromoteIntRes_BUILD_PAIR(SDNode *N);
+ SDValue PromoteIntRes_Constant(SDNode *N);
+ SDValue PromoteIntRes_CTLZ(SDNode *N);
+ SDValue PromoteIntRes_CTPOP(SDNode *N);
+ SDValue PromoteIntRes_CTTZ(SDNode *N);
+ SDValue PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N);
+ SDValue PromoteIntRes_FP_TO_XINT(SDNode *N);
+ SDValue PromoteIntRes_INT_EXTEND(SDNode *N);
+ SDValue PromoteIntRes_LOAD(LoadSDNode *N);
+ SDValue PromoteIntRes_SDIV(SDNode *N);
+ SDValue PromoteIntRes_SELECT (SDNode *N);
+ SDValue PromoteIntRes_SELECT_CC(SDNode *N);
+ SDValue PromoteIntRes_SETCC(SDNode *N);
+ SDValue PromoteIntRes_SHL(SDNode *N);
+ SDValue PromoteIntRes_SimpleIntBinOp(SDNode *N);
+ SDValue PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N);
+ SDValue PromoteIntRes_SRA(SDNode *N);
+ SDValue PromoteIntRes_SRL(SDNode *N);
+ SDValue PromoteIntRes_TRUNCATE(SDNode *N);
+ SDValue PromoteIntRes_UDIV(SDNode *N);
+ SDValue PromoteIntRes_UNDEF(SDNode *N);
+ SDValue PromoteIntRes_VAARG(SDNode *N);
// Integer Operand Promotion.
bool PromoteIntegerOperand(SDNode *N, unsigned OperandNo);
- SDOperand PromoteIntOp_ANY_EXTEND(SDNode *N);
- SDOperand PromoteIntOp_BUILD_PAIR(SDNode *N);
- SDOperand PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo);
- SDOperand PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo);
- SDOperand PromoteIntOp_BUILD_VECTOR(SDNode *N);
- SDOperand PromoteIntOp_FP_EXTEND(SDNode *N);
- SDOperand PromoteIntOp_FP_ROUND(SDNode *N);
- SDOperand PromoteIntOp_INT_TO_FP(SDNode *N);
- SDOperand PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N, unsigned OpNo);
- SDOperand PromoteIntOp_MEMBARRIER(SDNode *N);
- SDOperand PromoteIntOp_SELECT(SDNode *N, unsigned OpNo);
- SDOperand PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo);
- SDOperand PromoteIntOp_SETCC(SDNode *N, unsigned OpNo);
- SDOperand PromoteIntOp_SIGN_EXTEND(SDNode *N);
- SDOperand PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo);
- SDOperand PromoteIntOp_TRUNCATE(SDNode *N);
- SDOperand PromoteIntOp_ZERO_EXTEND(SDNode *N);
+ SDValue PromoteIntOp_ANY_EXTEND(SDNode *N);
+ SDValue PromoteIntOp_BUILD_PAIR(SDNode *N);
+ SDValue PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo);
+ SDValue PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo);
+ SDValue PromoteIntOp_BUILD_VECTOR(SDNode *N);
+ SDValue PromoteIntOp_FP_EXTEND(SDNode *N);
+ SDValue PromoteIntOp_FP_ROUND(SDNode *N);
+ SDValue PromoteIntOp_INT_TO_FP(SDNode *N);
+ SDValue PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N, unsigned OpNo);
+ SDValue PromoteIntOp_MEMBARRIER(SDNode *N);
+ SDValue PromoteIntOp_SELECT(SDNode *N, unsigned OpNo);
+ SDValue PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo);
+ SDValue PromoteIntOp_SETCC(SDNode *N, unsigned OpNo);
+ SDValue PromoteIntOp_SIGN_EXTEND(SDNode *N);
+ SDValue PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo);
+ SDValue PromoteIntOp_TRUNCATE(SDNode *N);
+ SDValue PromoteIntOp_ZERO_EXTEND(SDNode *N);
- void PromoteSetCCOperands(SDOperand &LHS,SDOperand &RHS, ISD::CondCode Code);
+ void PromoteSetCCOperands(SDValue &LHS,SDValue &RHS, ISD::CondCode Code);
//===--------------------------------------------------------------------===//
// Integer Expansion Support: LegalizeIntegerTypes.cpp
//===--------------------------------------------------------------------===//
- void GetExpandedInteger(SDOperand Op, SDOperand &Lo, SDOperand &Hi);
- void SetExpandedInteger(SDOperand Op, SDOperand Lo, SDOperand Hi);
+ void GetExpandedInteger(SDValue Op, SDValue &Lo, SDValue &Hi);
+ void SetExpandedInteger(SDValue Op, SDValue Lo, SDValue Hi);
// Integer Result Expansion.
void ExpandIntegerResult(SDNode *N, unsigned ResNo);
- void ExpandIntRes_ANY_EXTEND (SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void ExpandIntRes_AssertSext (SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void ExpandIntRes_AssertZext (SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void ExpandIntRes_Constant (SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void ExpandIntRes_CTLZ (SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void ExpandIntRes_CTPOP (SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void ExpandIntRes_CTTZ (SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void ExpandIntRes_LOAD (LoadSDNode *N, SDOperand &Lo, SDOperand &Hi);
- void ExpandIntRes_SIGN_EXTEND (SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void ExpandIntRes_SIGN_EXTEND_INREG (SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void ExpandIntRes_TRUNCATE (SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void ExpandIntRes_ZERO_EXTEND (SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void ExpandIntRes_FP_TO_SINT (SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void ExpandIntRes_FP_TO_UINT (SDNode *N, SDOperand &Lo, SDOperand &Hi);
-
- void ExpandIntRes_Logical (SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void ExpandIntRes_ADDSUB (SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void ExpandIntRes_ADDSUBC (SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void ExpandIntRes_ADDSUBE (SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void ExpandIntRes_BSWAP (SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void ExpandIntRes_MUL (SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void ExpandIntRes_SDIV (SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void ExpandIntRes_SREM (SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void ExpandIntRes_UDIV (SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void ExpandIntRes_UREM (SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void ExpandIntRes_Shift (SDNode *N, SDOperand &Lo, SDOperand &Hi);
+ void ExpandIntRes_ANY_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandIntRes_AssertSext (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandIntRes_AssertZext (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandIntRes_Constant (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandIntRes_CTLZ (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandIntRes_CTPOP (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandIntRes_CTTZ (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandIntRes_LOAD (LoadSDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandIntRes_SIGN_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandIntRes_SIGN_EXTEND_INREG (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandIntRes_TRUNCATE (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandIntRes_ZERO_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandIntRes_FP_TO_SINT (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandIntRes_FP_TO_UINT (SDNode *N, SDValue &Lo, SDValue &Hi);
+
+ void ExpandIntRes_Logical (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandIntRes_ADDSUB (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandIntRes_ADDSUBC (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandIntRes_ADDSUBE (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandIntRes_BSWAP (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandIntRes_MUL (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandIntRes_SDIV (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandIntRes_SREM (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandIntRes_UDIV (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandIntRes_UREM (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandIntRes_Shift (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandShiftByConstant(SDNode *N, unsigned Amt,
- SDOperand &Lo, SDOperand &Hi);
- bool ExpandShiftWithKnownAmountBit(SDNode *N, SDOperand &Lo, SDOperand &Hi);
+ SDValue &Lo, SDValue &Hi);
+ bool ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi);
// Integer Operand Expansion.
bool ExpandIntegerOperand(SDNode *N, unsigned OperandNo);
- SDOperand ExpandIntOp_BIT_CONVERT(SDNode *N);
- SDOperand ExpandIntOp_BR_CC(SDNode *N);
- SDOperand ExpandIntOp_BUILD_VECTOR(SDNode *N);
- SDOperand ExpandIntOp_EXTRACT_ELEMENT(SDNode *N);
- SDOperand ExpandIntOp_SELECT_CC(SDNode *N);
- SDOperand ExpandIntOp_SETCC(SDNode *N);
- SDOperand ExpandIntOp_SINT_TO_FP(SDNode *N);
- SDOperand ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo);
- SDOperand ExpandIntOp_TRUNCATE(SDNode *N);
- SDOperand ExpandIntOp_UINT_TO_FP(SDNode *N);
+ SDValue ExpandIntOp_BIT_CONVERT(SDNode *N);
+ SDValue ExpandIntOp_BR_CC(SDNode *N);
+ SDValue ExpandIntOp_BUILD_VECTOR(SDNode *N);
+ SDValue ExpandIntOp_EXTRACT_ELEMENT(SDNode *N);
+ SDValue ExpandIntOp_SELECT_CC(SDNode *N);
+ SDValue ExpandIntOp_SETCC(SDNode *N);
+ SDValue ExpandIntOp_SINT_TO_FP(SDNode *N);
+ SDValue ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo);
+ SDValue ExpandIntOp_TRUNCATE(SDNode *N);
+ SDValue ExpandIntOp_UINT_TO_FP(SDNode *N);
- void IntegerExpandSetCCOperands(SDOperand &NewLHS, SDOperand &NewRHS,
+ void IntegerExpandSetCCOperands(SDValue &NewLHS, SDValue &NewRHS,
ISD::CondCode &CCCode);
//===--------------------------------------------------------------------===//
// Float to Integer Conversion Support: LegalizeFloatTypes.cpp
//===--------------------------------------------------------------------===//
- SDOperand GetSoftenedFloat(SDOperand Op) {
- SDOperand &SoftenedOp = SoftenedFloats[Op];
+ SDValue GetSoftenedFloat(SDValue Op) {
+ SDValue &SoftenedOp = SoftenedFloats[Op];
RemapNode(SoftenedOp);
assert(SoftenedOp.Val && "Operand wasn't converted to integer?");
return SoftenedOp;
}
- void SetSoftenedFloat(SDOperand Op, SDOperand Result);
+ void SetSoftenedFloat(SDValue Op, SDValue Result);
// Result Float to Integer Conversion.
void SoftenFloatResult(SDNode *N, unsigned OpNo);
- SDOperand SoftenFloatRes_BIT_CONVERT(SDNode *N);
- SDOperand SoftenFloatRes_BUILD_PAIR(SDNode *N);
- SDOperand SoftenFloatRes_ConstantFP(ConstantFPSDNode *N);
- SDOperand SoftenFloatRes_FADD(SDNode *N);
- SDOperand SoftenFloatRes_FCOPYSIGN(SDNode *N);
- SDOperand SoftenFloatRes_FDIV(SDNode *N);
- SDOperand SoftenFloatRes_FMUL(SDNode *N);
- SDOperand SoftenFloatRes_FP_EXTEND(SDNode *N);
- SDOperand SoftenFloatRes_FP_ROUND(SDNode *N);
- SDOperand SoftenFloatRes_FPOWI(SDNode *N);
- SDOperand SoftenFloatRes_FSUB(SDNode *N);
- SDOperand SoftenFloatRes_LOAD(SDNode *N);
- SDOperand SoftenFloatRes_SELECT(SDNode *N);
- SDOperand SoftenFloatRes_SELECT_CC(SDNode *N);
- SDOperand SoftenFloatRes_SINT_TO_FP(SDNode *N);
- SDOperand SoftenFloatRes_UINT_TO_FP(SDNode *N);
+ SDValue SoftenFloatRes_BIT_CONVERT(SDNode *N);
+ SDValue SoftenFloatRes_BUILD_PAIR(SDNode *N);
+ SDValue SoftenFloatRes_ConstantFP(ConstantFPSDNode *N);
+ SDValue SoftenFloatRes_FADD(SDNode *N);
+ SDValue SoftenFloatRes_FCOPYSIGN(SDNode *N);
+ SDValue SoftenFloatRes_FDIV(SDNode *N);
+ SDValue SoftenFloatRes_FMUL(SDNode *N);
+ SDValue SoftenFloatRes_FP_EXTEND(SDNode *N);
+ SDValue SoftenFloatRes_FP_ROUND(SDNode *N);
+ SDValue SoftenFloatRes_FPOWI(SDNode *N);
+ SDValue SoftenFloatRes_FSUB(SDNode *N);
+ SDValue SoftenFloatRes_LOAD(SDNode *N);
+ SDValue SoftenFloatRes_SELECT(SDNode *N);
+ SDValue SoftenFloatRes_SELECT_CC(SDNode *N);
+ SDValue SoftenFloatRes_SINT_TO_FP(SDNode *N);
+ SDValue SoftenFloatRes_UINT_TO_FP(SDNode *N);
// Operand Float to Integer Conversion.
bool SoftenFloatOperand(SDNode *N, unsigned OpNo);
- SDOperand SoftenFloatOp_BIT_CONVERT(SDNode *N);
- SDOperand SoftenFloatOp_BR_CC(SDNode *N);
- SDOperand SoftenFloatOp_FP_TO_SINT(SDNode *N);
- SDOperand SoftenFloatOp_FP_TO_UINT(SDNode *N);
- SDOperand SoftenFloatOp_SELECT_CC(SDNode *N);
- SDOperand SoftenFloatOp_SETCC(SDNode *N);
- SDOperand SoftenFloatOp_STORE(SDNode *N, unsigned OpNo);
+ SDValue SoftenFloatOp_BIT_CONVERT(SDNode *N);
+ SDValue SoftenFloatOp_BR_CC(SDNode *N);
+ SDValue SoftenFloatOp_FP_TO_SINT(SDNode *N);
+ SDValue SoftenFloatOp_FP_TO_UINT(SDNode *N);
+ SDValue SoftenFloatOp_SELECT_CC(SDNode *N);
+ SDValue SoftenFloatOp_SETCC(SDNode *N);
+ SDValue SoftenFloatOp_STORE(SDNode *N, unsigned OpNo);
- void SoftenSetCCOperands(SDOperand &NewLHS, SDOperand &NewRHS,
+ void SoftenSetCCOperands(SDValue &NewLHS, SDValue &NewRHS,
ISD::CondCode &CCCode);
//===--------------------------------------------------------------------===//
// Float Expansion Support: LegalizeFloatTypes.cpp
//===--------------------------------------------------------------------===//
- void GetExpandedFloat(SDOperand Op, SDOperand &Lo, SDOperand &Hi);
- void SetExpandedFloat(SDOperand Op, SDOperand Lo, SDOperand Hi);
+ void GetExpandedFloat(SDValue Op, SDValue &Lo, SDValue &Hi);
+ void SetExpandedFloat(SDValue Op, SDValue Lo, SDValue Hi);
// Float Result Expansion.
void ExpandFloatResult(SDNode *N, unsigned ResNo);
- void ExpandFloatRes_ConstantFP(SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void ExpandFloatRes_FABS (SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void ExpandFloatRes_FADD (SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void ExpandFloatRes_FDIV (SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void ExpandFloatRes_FMUL (SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void ExpandFloatRes_FNEG (SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void ExpandFloatRes_FP_EXTEND (SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void ExpandFloatRes_FSUB (SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void ExpandFloatRes_LOAD (SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void ExpandFloatRes_XINT_TO_FP(SDNode *N, SDOperand &Lo, SDOperand &Hi);
+ void ExpandFloatRes_ConstantFP(SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandFloatRes_FABS (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandFloatRes_FADD (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandFloatRes_FDIV (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandFloatRes_FMUL (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandFloatRes_FNEG (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandFloatRes_FP_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandFloatRes_FSUB (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandFloatRes_LOAD (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo, SDValue &Hi);
// Float Operand Expansion.
bool ExpandFloatOperand(SDNode *N, unsigned OperandNo);
- SDOperand ExpandFloatOp_BR_CC(SDNode *N);
- SDOperand ExpandFloatOp_FP_ROUND(SDNode *N);
- SDOperand ExpandFloatOp_FP_TO_SINT(SDNode *N);
- SDOperand ExpandFloatOp_FP_TO_UINT(SDNode *N);
- SDOperand ExpandFloatOp_SELECT_CC(SDNode *N);
- SDOperand ExpandFloatOp_SETCC(SDNode *N);
- SDOperand ExpandFloatOp_STORE(SDNode *N, unsigned OpNo);
+ SDValue ExpandFloatOp_BR_CC(SDNode *N);
+ SDValue ExpandFloatOp_FP_ROUND(SDNode *N);
+ SDValue ExpandFloatOp_FP_TO_SINT(SDNode *N);
+ SDValue ExpandFloatOp_FP_TO_UINT(SDNode *N);
+ SDValue ExpandFloatOp_SELECT_CC(SDNode *N);
+ SDValue ExpandFloatOp_SETCC(SDNode *N);
+ SDValue ExpandFloatOp_STORE(SDNode *N, unsigned OpNo);
- void FloatExpandSetCCOperands(SDOperand &NewLHS, SDOperand &NewRHS,
+ void FloatExpandSetCCOperands(SDValue &NewLHS, SDValue &NewRHS,
ISD::CondCode &CCCode);
//===--------------------------------------------------------------------===//
// Scalarization Support: LegalizeVectorTypes.cpp
//===--------------------------------------------------------------------===//
- SDOperand GetScalarizedVector(SDOperand Op) {
- SDOperand &ScalarizedOp = ScalarizedVectors[Op];
+ SDValue GetScalarizedVector(SDValue Op) {
+ SDValue &ScalarizedOp = ScalarizedVectors[Op];
RemapNode(ScalarizedOp);
assert(ScalarizedOp.Val && "Operand wasn't scalarized?");
return ScalarizedOp;
}
- void SetScalarizedVector(SDOperand Op, SDOperand Result);
+ void SetScalarizedVector(SDValue Op, SDValue Result);
// Vector Result Scalarization: <1 x ty> -> ty.
void ScalarizeVectorResult(SDNode *N, unsigned OpNo);
- SDOperand ScalarizeVecRes_BinOp(SDNode *N);
- SDOperand ScalarizeVecRes_UnaryOp(SDNode *N);
+ SDValue ScalarizeVecRes_BinOp(SDNode *N);
+ SDValue ScalarizeVecRes_UnaryOp(SDNode *N);
- SDOperand ScalarizeVecRes_BIT_CONVERT(SDNode *N);
- SDOperand ScalarizeVecRes_FPOWI(SDNode *N);
- SDOperand ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N);
- SDOperand ScalarizeVecRes_LOAD(LoadSDNode *N);
- SDOperand ScalarizeVecRes_SELECT(SDNode *N);
- SDOperand ScalarizeVecRes_UNDEF(SDNode *N);
- SDOperand ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N);
- SDOperand ScalarizeVecRes_VSETCC(SDNode *N);
+ SDValue ScalarizeVecRes_BIT_CONVERT(SDNode *N);
+ SDValue ScalarizeVecRes_FPOWI(SDNode *N);
+ SDValue ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N);
+ SDValue ScalarizeVecRes_LOAD(LoadSDNode *N);
+ SDValue ScalarizeVecRes_SELECT(SDNode *N);
+ SDValue ScalarizeVecRes_UNDEF(SDNode *N);
+ SDValue ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N);
+ SDValue ScalarizeVecRes_VSETCC(SDNode *N);
// Vector Operand Scalarization: <1 x ty> -> ty.
bool ScalarizeVectorOperand(SDNode *N, unsigned OpNo);
- SDOperand ScalarizeVecOp_BIT_CONVERT(SDNode *N);
- SDOperand ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
- SDOperand ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo);
+ SDValue ScalarizeVecOp_BIT_CONVERT(SDNode *N);
+ SDValue ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
+ SDValue ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo);
//===--------------------------------------------------------------------===//
// Vector Splitting Support: LegalizeVectorTypes.cpp
//===--------------------------------------------------------------------===//
- void GetSplitVector(SDOperand Op, SDOperand &Lo, SDOperand &Hi);
- void SetSplitVector(SDOperand Op, SDOperand Lo, SDOperand Hi);
+ void GetSplitVector(SDValue Op, SDValue &Lo, SDValue &Hi);
+ void SetSplitVector(SDValue Op, SDValue Lo, SDValue Hi);
// Vector Result Splitting: <128 x ty> -> 2 x <64 x ty>.
void SplitVectorResult(SDNode *N, unsigned OpNo);
- void SplitVecRes_BinOp(SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void SplitVecRes_UnaryOp(SDNode *N, SDOperand &Lo, SDOperand &Hi);
+ void SplitVecRes_BinOp(SDNode *N, SDValue &Lo, SDValue &Hi);
+ void SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, SDValue &Hi);
- void SplitVecRes_BIT_CONVERT(SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void SplitVecRes_BUILD_PAIR(SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void SplitVecRes_BUILD_VECTOR(SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void SplitVecRes_CONCAT_VECTORS(SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void SplitVecRes_FPOWI(SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void SplitVecRes_LOAD(LoadSDNode *N, SDOperand &Lo, SDOperand &Hi);
- void SplitVecRes_UNDEF(SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void SplitVecRes_VSETCC(SDNode *N, SDOperand &Lo, SDOperand &Hi);
+ void SplitVecRes_BIT_CONVERT(SDNode *N, SDValue &Lo, SDValue &Hi);
+ void SplitVecRes_BUILD_PAIR(SDNode *N, SDValue &Lo, SDValue &Hi);
+ void SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
+ void SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo, SDValue &Hi);
+ void SplitVecRes_FPOWI(SDNode *N, SDValue &Lo, SDValue &Hi);
+ void SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi);
+ void SplitVecRes_LOAD(LoadSDNode *N, SDValue &Lo, SDValue &Hi);
+ void SplitVecRes_UNDEF(SDNode *N, SDValue &Lo, SDValue &Hi);
+ void SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDValue &Lo, SDValue &Hi);
+ void SplitVecRes_VSETCC(SDNode *N, SDValue &Lo, SDValue &Hi);
// Vector Operand Splitting: <128 x ty> -> 2 x <64 x ty>.
bool SplitVectorOperand(SDNode *N, unsigned OpNo);
- SDOperand SplitVecOp_BIT_CONVERT(SDNode *N);
- SDOperand SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N);
- SDOperand SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
- SDOperand SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo);
- SDOperand SplitVecOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo);
+ SDValue SplitVecOp_BIT_CONVERT(SDNode *N);
+ SDValue SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N);
+ SDValue SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
+ SDValue SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo);
+ SDValue SplitVecOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo);
//===--------------------------------------------------------------------===//
// Generic Splitting: LegalizeTypesGeneric.cpp
@@ -466,7 +466,7 @@
// not necessarily identical types. As such they can be used for splitting
// vectors and expanding integers and floats.
- void GetSplitOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi) {
+ void GetSplitOp(SDValue Op, SDValue &Lo, SDValue &Hi) {
if (Op.getValueType().isVector())
GetSplitVector(Op, Lo, Hi);
else if (Op.getValueType().isInteger())
@@ -480,10 +480,10 @@
void GetSplitDestVTs(MVT InVT, MVT &LoVT, MVT &HiVT);
// Generic Result Splitting.
- void SplitRes_MERGE_VALUES(SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void SplitRes_SELECT (SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void SplitRes_SELECT_CC (SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void SplitRes_UNDEF (SDNode *N, SDOperand &Lo, SDOperand &Hi);
+ void SplitRes_MERGE_VALUES(SDNode *N, SDValue &Lo, SDValue &Hi);
+ void SplitRes_SELECT (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void SplitRes_SELECT_CC (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void SplitRes_UNDEF (SDNode *N, SDValue &Lo, SDValue &Hi);
//===--------------------------------------------------------------------===//
// Generic Expansion: LegalizeTypesGeneric.cpp
@@ -494,7 +494,7 @@
// in memory on little/big-endian machines, followed by the Hi/Lo part. As
// such they can be used for expanding integers and floats.
- void GetExpandedOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi) {
+ void GetExpandedOp(SDValue Op, SDValue &Lo, SDValue &Hi) {
if (Op.getValueType().isInteger())
GetExpandedInteger(Op, Lo, Hi);
else
@@ -502,17 +502,17 @@
}
// Generic Result Expansion.
- void ExpandRes_BIT_CONVERT (SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void ExpandRes_BUILD_PAIR (SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void ExpandRes_EXTRACT_ELEMENT (SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void ExpandRes_EXTRACT_VECTOR_ELT(SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void ExpandRes_NormalLoad (SDNode *N, SDOperand &Lo, SDOperand &Hi);
+ void ExpandRes_BIT_CONVERT (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandRes_BUILD_PAIR (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandRes_EXTRACT_ELEMENT (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandRes_EXTRACT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandRes_NormalLoad (SDNode *N, SDValue &Lo, SDValue &Hi);
// Generic Operand Expansion.
- SDOperand ExpandOp_BIT_CONVERT (SDNode *N);
- SDOperand ExpandOp_BUILD_VECTOR (SDNode *N);
- SDOperand ExpandOp_EXTRACT_ELEMENT(SDNode *N);
- SDOperand ExpandOp_NormalStore (SDNode *N, unsigned OpNo);
+ SDValue ExpandOp_BIT_CONVERT (SDNode *N);
+ SDValue ExpandOp_BUILD_VECTOR (SDNode *N);
+ SDValue ExpandOp_EXTRACT_ELEMENT(SDNode *N);
+ SDValue ExpandOp_NormalStore (SDNode *N, unsigned OpNo);
};
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp Sun Jul 27 16:46:04 2008
@@ -28,10 +28,10 @@
// little/big-endian machines, followed by the Hi/Lo part. This means that
// they cannot be used as is on vectors, for which Lo is always stored first.
-void DAGTypeLegalizer::ExpandRes_BIT_CONVERT(SDNode *N, SDOperand &Lo,
- SDOperand &Hi) {
+void DAGTypeLegalizer::ExpandRes_BIT_CONVERT(SDNode *N, SDValue &Lo,
+ SDValue &Hi) {
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
- SDOperand InOp = N->getOperand(0);
+ SDValue InOp = N->getOperand(0);
MVT InVT = InOp.getValueType();
// Handle some special cases efficiently.
@@ -74,21 +74,21 @@
}
// Lower the bit-convert to a store/load from the stack, then expand the load.
- SDOperand Op = CreateStackStoreLoad(InOp, N->getValueType(0));
+ SDValue Op = CreateStackStoreLoad(InOp, N->getValueType(0));
ExpandRes_NormalLoad(Op.Val, Lo, Hi);
}
-void DAGTypeLegalizer::ExpandRes_BUILD_PAIR(SDNode *N, SDOperand &Lo,
- SDOperand &Hi) {
+void DAGTypeLegalizer::ExpandRes_BUILD_PAIR(SDNode *N, SDValue &Lo,
+ SDValue &Hi) {
// Return the operands.
Lo = N->getOperand(0);
Hi = N->getOperand(1);
}
-void DAGTypeLegalizer::ExpandRes_EXTRACT_ELEMENT(SDNode *N, SDOperand &Lo,
- SDOperand &Hi) {
+void DAGTypeLegalizer::ExpandRes_EXTRACT_ELEMENT(SDNode *N, SDValue &Lo,
+ SDValue &Hi) {
GetExpandedOp(N->getOperand(0), Lo, Hi);
- SDOperand Part = cast<ConstantSDNode>(N->getOperand(1))->getValue() ? Hi : Lo;
+ SDValue Part = cast<ConstantSDNode>(N->getOperand(1))->getValue() ? Hi : Lo;
assert(Part.getValueType() == N->getValueType(0) &&
"Type twice as big as expanded type not itself expanded!");
@@ -100,9 +100,9 @@
DAG.getConstant(1, TLI.getPointerTy()));
}
-void DAGTypeLegalizer::ExpandRes_EXTRACT_VECTOR_ELT(SDNode *N, SDOperand &Lo,
- SDOperand &Hi) {
- SDOperand OldVec = N->getOperand(0);
+void DAGTypeLegalizer::ExpandRes_EXTRACT_VECTOR_ELT(SDNode *N, SDValue &Lo,
+ SDValue &Hi) {
+ SDValue OldVec = N->getOperand(0);
unsigned OldElts = OldVec.getValueType().getVectorNumElements();
// Convert to a vector of the expanded element type, for example
@@ -110,12 +110,12 @@
MVT OldVT = N->getValueType(0);
MVT NewVT = TLI.getTypeToTransformTo(OldVT);
- SDOperand NewVec = DAG.getNode(ISD::BIT_CONVERT,
+ SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT,
MVT::getVectorVT(NewVT, 2*OldElts),
OldVec);
// Extract the elements at 2 * Idx and 2 * Idx + 1 from the new vector.
- SDOperand Idx = N->getOperand(1);
+ SDValue Idx = N->getOperand(1);
// Make sure the type of Idx is big enough to hold the new values.
if (Idx.getValueType().bitsLT(TLI.getPointerTy()))
@@ -132,14 +132,14 @@
std::swap(Lo, Hi);
}
-void DAGTypeLegalizer::ExpandRes_NormalLoad(SDNode *N, SDOperand &Lo,
- SDOperand &Hi) {
+void DAGTypeLegalizer::ExpandRes_NormalLoad(SDNode *N, SDValue &Lo,
+ SDValue &Hi) {
assert(ISD::isNormalLoad(N) && "This routine only for normal loads!");
LoadSDNode *LD = cast<LoadSDNode>(N);
MVT NVT = TLI.getTypeToTransformTo(LD->getValueType(0));
- SDOperand Chain = LD->getChain();
- SDOperand Ptr = LD->getBasePtr();
+ SDValue Chain = LD->getChain();
+ SDValue Ptr = LD->getBasePtr();
int SVOffset = LD->getSrcValueOffset();
unsigned Alignment = LD->getAlignment();
bool isVolatile = LD->isVolatile();
@@ -167,7 +167,7 @@
// Modified the chain - switch anything that used the old chain to use
// the new one.
- ReplaceValueWith(SDOperand(N, 1), Chain);
+ ReplaceValueWith(SDValue(N, 1), Chain);
}
@@ -175,7 +175,7 @@
// Generic Operand Expansion.
//===--------------------------------------------------------------------===//
-SDOperand DAGTypeLegalizer::ExpandOp_BIT_CONVERT(SDNode *N) {
+SDValue DAGTypeLegalizer::ExpandOp_BIT_CONVERT(SDNode *N) {
if (N->getValueType(0).isVector()) {
// An illegal expanding type is being converted to a legal vector type.
// Make a two element vector out of the expanded parts and convert that
@@ -186,13 +186,13 @@
MVT NVT = MVT::getVectorVT(TLI.getTypeToTransformTo(OVT), 2);
if (isTypeLegal(NVT)) {
- SDOperand Parts[2];
+ SDValue Parts[2];
GetExpandedOp(N->getOperand(0), Parts[0], Parts[1]);
if (TLI.isBigEndian())
std::swap(Parts[0], Parts[1]);
- SDOperand Vec = DAG.getNode(ISD::BUILD_VECTOR, NVT, Parts, 2);
+ SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, NVT, Parts, 2);
return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Vec);
}
}
@@ -201,7 +201,7 @@
return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
}
-SDOperand DAGTypeLegalizer::ExpandOp_BUILD_VECTOR(SDNode *N) {
+SDValue DAGTypeLegalizer::ExpandOp_BUILD_VECTOR(SDNode *N) {
// The vector type is legal but the element type needs expansion.
MVT VecVT = N->getValueType(0);
unsigned NumElts = VecVT.getVectorNumElements();
@@ -210,11 +210,11 @@
// Build a vector of twice the length out of the expanded elements.
// For example <3 x i64> -> <6 x i32>.
- std::vector<SDOperand> NewElts;
+ std::vector<SDValue> NewElts;
NewElts.reserve(NumElts*2);
for (unsigned i = 0; i < NumElts; ++i) {
- SDOperand Lo, Hi;
+ SDValue Lo, Hi;
GetExpandedOp(N->getOperand(i), Lo, Hi);
if (TLI.isBigEndian())
std::swap(Lo, Hi);
@@ -222,7 +222,7 @@
NewElts.push_back(Hi);
}
- SDOperand NewVec = DAG.getNode(ISD::BUILD_VECTOR,
+ SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR,
MVT::getVectorVT(NewVT, NewElts.size()),
&NewElts[0], NewElts.size());
@@ -230,20 +230,20 @@
return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec);
}
-SDOperand DAGTypeLegalizer::ExpandOp_EXTRACT_ELEMENT(SDNode *N) {
- SDOperand Lo, Hi;
+SDValue DAGTypeLegalizer::ExpandOp_EXTRACT_ELEMENT(SDNode *N) {
+ SDValue Lo, Hi;
GetExpandedOp(N->getOperand(0), Lo, Hi);
return cast<ConstantSDNode>(N->getOperand(1))->getValue() ? Hi : Lo;
}
-SDOperand DAGTypeLegalizer::ExpandOp_NormalStore(SDNode *N, unsigned OpNo) {
+SDValue DAGTypeLegalizer::ExpandOp_NormalStore(SDNode *N, unsigned OpNo) {
assert(ISD::isNormalStore(N) && "This routine only for normal stores!");
assert(OpNo == 1 && "Can only expand the stored value so far");
StoreSDNode *St = cast<StoreSDNode>(N);
MVT NVT = TLI.getTypeToTransformTo(St->getValue().getValueType());
- SDOperand Chain = St->getChain();
- SDOperand Ptr = St->getBasePtr();
+ SDValue Chain = St->getChain();
+ SDValue Ptr = St->getBasePtr();
int SVOffset = St->getSrcValueOffset();
unsigned Alignment = St->getAlignment();
bool isVolatile = St->isVolatile();
@@ -251,7 +251,7 @@
assert(NVT.isByteSized() && "Expanded type not byte sized!");
unsigned IncrementSize = NVT.getSizeInBits() / 8;
- SDOperand Lo, Hi;
+ SDValue Lo, Hi;
GetExpandedOp(St->getValue(), Lo, Hi);
if (TLI.isBigEndian())
@@ -280,7 +280,7 @@
// little-endian).
void DAGTypeLegalizer::SplitRes_MERGE_VALUES(SDNode *N,
- SDOperand &Lo, SDOperand &Hi) {
+ SDValue &Lo, SDValue &Hi) {
// A MERGE_VALUES node can produce any number of values. We know that the
// first illegal one needs to be expanded into Lo/Hi.
unsigned i;
@@ -288,7 +288,7 @@
// The string of legal results gets turns into the input operands, which have
// the same type.
for (i = 0; isTypeLegal(N->getValueType(i)); ++i)
- ReplaceValueWith(SDOperand(N, i), SDOperand(N->getOperand(i)));
+ ReplaceValueWith(SDValue(N, i), SDValue(N->getOperand(i)));
// The first illegal result must be the one that needs to be expanded.
GetSplitOp(N->getOperand(i), Lo, Hi);
@@ -297,23 +297,23 @@
// legal or not.
unsigned e = N->getNumValues();
for (++i; i != e; ++i)
- ReplaceValueWith(SDOperand(N, i), SDOperand(N->getOperand(i)));
+ ReplaceValueWith(SDValue(N, i), SDValue(N->getOperand(i)));
}
-void DAGTypeLegalizer::SplitRes_SELECT(SDNode *N, SDOperand &Lo,
- SDOperand &Hi) {
- SDOperand LL, LH, RL, RH;
+void DAGTypeLegalizer::SplitRes_SELECT(SDNode *N, SDValue &Lo,
+ SDValue &Hi) {
+ SDValue LL, LH, RL, RH;
GetSplitOp(N->getOperand(1), LL, LH);
GetSplitOp(N->getOperand(2), RL, RH);
- SDOperand Cond = N->getOperand(0);
+ SDValue Cond = N->getOperand(0);
Lo = DAG.getNode(ISD::SELECT, LL.getValueType(), Cond, LL, RL);
Hi = DAG.getNode(ISD::SELECT, LH.getValueType(), Cond, LH, RH);
}
-void DAGTypeLegalizer::SplitRes_SELECT_CC(SDNode *N, SDOperand &Lo,
- SDOperand &Hi) {
- SDOperand LL, LH, RL, RH;
+void DAGTypeLegalizer::SplitRes_SELECT_CC(SDNode *N, SDValue &Lo,
+ SDValue &Hi) {
+ SDValue LL, LH, RL, RH;
GetSplitOp(N->getOperand(2), LL, LH);
GetSplitOp(N->getOperand(3), RL, RH);
@@ -323,7 +323,7 @@
N->getOperand(1), LH, RH, N->getOperand(4));
}
-void DAGTypeLegalizer::SplitRes_UNDEF(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
+void DAGTypeLegalizer::SplitRes_UNDEF(SDNode *N, SDValue &Lo, SDValue &Hi) {
MVT LoVT, HiVT;
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
Lo = DAG.getNode(ISD::UNDEF, LoVT);
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Sun Jul 27 16:46:04 2008
@@ -30,7 +30,7 @@
void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
DEBUG(cerr << "Scalarize node result " << ResNo << ": "; N->dump(&DAG);
cerr << "\n");
- SDOperand R = SDOperand();
+ SDValue R = SDValue();
switch (N->getOpcode()) {
default:
@@ -84,29 +84,29 @@
// If R is null, the sub-method took care of registering the result.
if (R.Val)
- SetScalarizedVector(SDOperand(N, ResNo), R);
+ SetScalarizedVector(SDValue(N, ResNo), R);
}
-SDOperand DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
- SDOperand LHS = GetScalarizedVector(N->getOperand(0));
- SDOperand RHS = GetScalarizedVector(N->getOperand(1));
+SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
+ SDValue LHS = GetScalarizedVector(N->getOperand(0));
+ SDValue RHS = GetScalarizedVector(N->getOperand(1));
return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
}
-SDOperand DAGTypeLegalizer::ScalarizeVecRes_BIT_CONVERT(SDNode *N) {
+SDValue DAGTypeLegalizer::ScalarizeVecRes_BIT_CONVERT(SDNode *N) {
MVT NewVT = N->getValueType(0).getVectorElementType();
return DAG.getNode(ISD::BIT_CONVERT, NewVT, N->getOperand(0));
}
-SDOperand DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
- SDOperand Op = GetScalarizedVector(N->getOperand(0));
+SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
+ SDValue Op = GetScalarizedVector(N->getOperand(0));
return DAG.getNode(ISD::FPOWI, Op.getValueType(), Op, N->getOperand(1));
}
-SDOperand DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
+SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
// The value to insert may have a wider type than the vector element type,
// so be sure to truncate it to the element type if necessary.
- SDOperand Op = N->getOperand(1);
+ SDValue Op = N->getOperand(1);
MVT EltVT = N->getValueType(0).getVectorElementType();
if (Op.getValueType() != EltVT)
// FIXME: Can this happen for floating point types?
@@ -114,47 +114,47 @@
return Op;
}
-SDOperand DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
+SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
assert(ISD::isNormalLoad(N) && "Extending load of one-element vector?");
- SDOperand Result = DAG.getLoad(N->getValueType(0).getVectorElementType(),
+ SDValue Result = DAG.getLoad(N->getValueType(0).getVectorElementType(),
N->getChain(), N->getBasePtr(),
N->getSrcValue(), N->getSrcValueOffset(),
N->isVolatile(), N->getAlignment());
// Legalized the chain result - switch anything that used the old chain to
// use the new one.
- ReplaceValueWith(SDOperand(N, 1), Result.getValue(1));
+ ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
return Result;
}
-SDOperand DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
+SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
// Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
MVT DestVT = TLI.getTypeToTransformTo(N->getValueType(0));
- SDOperand Op = GetScalarizedVector(N->getOperand(0));
+ SDValue Op = GetScalarizedVector(N->getOperand(0));
return DAG.getNode(N->getOpcode(), DestVT, Op);
}
-SDOperand DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
+SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
return DAG.getNode(ISD::UNDEF, N->getValueType(0).getVectorElementType());
}
-SDOperand DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
- SDOperand LHS = GetScalarizedVector(N->getOperand(1));
+SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
+ SDValue LHS = GetScalarizedVector(N->getOperand(1));
return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0), LHS,
GetScalarizedVector(N->getOperand(2)));
}
-SDOperand DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
+SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
// Figure out if the scalar is the LHS or RHS and return it.
- SDOperand EltNum = N->getOperand(2).getOperand(0);
+ SDValue EltNum = N->getOperand(2).getOperand(0);
unsigned Op = cast<ConstantSDNode>(EltNum)->getValue() != 0;
return GetScalarizedVector(N->getOperand(Op));
}
-SDOperand DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
+SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
MVT NewVT = N->getValueType(0).getVectorElementType();
- SDOperand LHS = GetScalarizedVector(N->getOperand(0));
- SDOperand RHS = GetScalarizedVector(N->getOperand(1));
+ SDValue LHS = GetScalarizedVector(N->getOperand(0));
+ SDValue RHS = GetScalarizedVector(N->getOperand(1));
LHS = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, RHS,
N->getOperand(2));
return
@@ -172,7 +172,7 @@
bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
DEBUG(cerr << "Scalarize node operand " << OpNo << ": "; N->dump(&DAG);
cerr << "\n");
- SDOperand Res = SDOperand();
+ SDValue Res = SDValue();
if (Res.Val == 0) {
switch (N->getOpcode()) {
@@ -211,27 +211,27 @@
assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
"Invalid operand expansion");
- ReplaceValueWith(SDOperand(N, 0), Res);
+ ReplaceValueWith(SDValue(N, 0), Res);
return false;
}
/// ScalarizeVecOp_BIT_CONVERT - If the value to convert is a vector that needs
/// to be scalarized, it must be <1 x ty>. Convert the element instead.
-SDOperand DAGTypeLegalizer::ScalarizeVecOp_BIT_CONVERT(SDNode *N) {
- SDOperand Elt = GetScalarizedVector(N->getOperand(0));
+SDValue DAGTypeLegalizer::ScalarizeVecOp_BIT_CONVERT(SDNode *N) {
+ SDValue Elt = GetScalarizedVector(N->getOperand(0));
return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Elt);
}
/// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
/// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
/// index.
-SDOperand DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
+SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
return GetScalarizedVector(N->getOperand(0));
}
/// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
/// scalarized, it must be <1 x ty>. Just store the element.
-SDOperand DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
+SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
assert(ISD::isNormalStore(N) && "Truncating store of one-element vector?");
assert(OpNo == 1 && "Do not know how to scalarize this operand!");
return DAG.getStore(N->getChain(), GetScalarizedVector(N->getOperand(1)),
@@ -251,7 +251,7 @@
/// splitting.
void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
DEBUG(cerr << "Split node result: "; N->dump(&DAG); cerr << "\n");
- SDOperand Lo, Hi;
+ SDValue Lo, Hi;
switch (N->getOpcode()) {
default:
@@ -309,28 +309,28 @@
// If Lo/Hi is null, the sub-method took care of registering results etc.
if (Lo.Val)
- SetSplitVector(SDOperand(N, ResNo), Lo, Hi);
+ SetSplitVector(SDValue(N, ResNo), Lo, Hi);
}
-void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDOperand &Lo,
- SDOperand &Hi) {
- SDOperand LHSLo, LHSHi;
+void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
+ SDValue &Hi) {
+ SDValue LHSLo, LHSHi;
GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
- SDOperand RHSLo, RHSHi;
+ SDValue RHSLo, RHSHi;
GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
Lo = DAG.getNode(N->getOpcode(), LHSLo.getValueType(), LHSLo, RHSLo);
Hi = DAG.getNode(N->getOpcode(), LHSHi.getValueType(), LHSHi, RHSHi);
}
-void DAGTypeLegalizer::SplitVecRes_BIT_CONVERT(SDNode *N, SDOperand &Lo,
- SDOperand &Hi) {
+void DAGTypeLegalizer::SplitVecRes_BIT_CONVERT(SDNode *N, SDValue &Lo,
+ SDValue &Hi) {
// We know the result is a vector. The input may be either a vector or a
// scalar value.
MVT LoVT, HiVT;
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
- SDOperand InOp = N->getOperand(0);
+ SDValue InOp = N->getOperand(0);
MVT InVT = InOp.getValueType();
// Handle some special cases efficiently.
@@ -379,20 +379,20 @@
Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
}
-void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDOperand &Lo,
- SDOperand &Hi) {
+void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
+ SDValue &Hi) {
MVT LoVT, HiVT;
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
unsigned LoNumElts = LoVT.getVectorNumElements();
- SmallVector<SDOperand, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
+ SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
Lo = DAG.getNode(ISD::BUILD_VECTOR, LoVT, &LoOps[0], LoOps.size());
- SmallVector<SDOperand, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
+ SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &HiOps[0], HiOps.size());
}
-void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDOperand &Lo,
- SDOperand &Hi) {
+void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
+ SDValue &Hi) {
assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
unsigned NumSubvectors = N->getNumOperands() / 2;
if (NumSubvectors == 1) {
@@ -404,25 +404,25 @@
MVT LoVT, HiVT;
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
- SmallVector<SDOperand, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
+ SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
Lo = DAG.getNode(ISD::CONCAT_VECTORS, LoVT, &LoOps[0], LoOps.size());
- SmallVector<SDOperand, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
+ SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
Hi = DAG.getNode(ISD::CONCAT_VECTORS, HiVT, &HiOps[0], HiOps.size());
}
-void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDOperand &Lo,
- SDOperand &Hi) {
+void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
+ SDValue &Hi) {
GetSplitVector(N->getOperand(0), Lo, Hi);
Lo = DAG.getNode(ISD::FPOWI, Lo.getValueType(), Lo, N->getOperand(1));
Hi = DAG.getNode(ISD::FPOWI, Hi.getValueType(), Hi, N->getOperand(1));
}
-void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDOperand &Lo,
- SDOperand &Hi) {
- SDOperand Vec = N->getOperand(0);
- SDOperand Elt = N->getOperand(1);
- SDOperand Idx = N->getOperand(2);
+void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
+ SDValue &Hi) {
+ SDValue Vec = N->getOperand(0);
+ SDValue Elt = N->getOperand(1);
+ SDValue Idx = N->getOperand(2);
GetSplitVector(Vec, Lo, Hi);
if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
@@ -439,29 +439,29 @@
// Spill the vector to the stack.
MVT VecVT = Vec.getValueType();
MVT EltVT = VecVT.getVectorElementType();
- SDOperand StackPtr = DAG.CreateStackTemporary(VecVT);
- SDOperand Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
+ SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
+ SDValue Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
// Store the new element. This may be larger than the vector element type,
// so use a truncating store.
- SDOperand EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
+ SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
Store = DAG.getTruncStore(Store, Elt, EltPtr, NULL, 0, EltVT);
// Reload the vector from the stack.
- SDOperand Load = DAG.getLoad(VecVT, Store, StackPtr, NULL, 0);
+ SDValue Load = DAG.getLoad(VecVT, Store, StackPtr, NULL, 0);
// Split it.
SplitVecRes_LOAD(cast<LoadSDNode>(Load.Val), Lo, Hi);
}
-void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDOperand &Lo,
- SDOperand &Hi) {
+void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
+ SDValue &Hi) {
assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
MVT LoVT, HiVT;
GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT);
- SDOperand Ch = LD->getChain();
- SDOperand Ptr = LD->getBasePtr();
+ SDValue Ch = LD->getChain();
+ SDValue Ptr = LD->getBasePtr();
const Value *SV = LD->getSrcValue();
int SVOffset = LD->getSrcValueOffset();
unsigned Alignment = LD->getAlignment();
@@ -490,11 +490,11 @@
// Legalized the chain result - switch anything that used the old chain to
// use the new one.
- ReplaceValueWith(SDOperand(LD, 1), Ch);
+ ReplaceValueWith(SDValue(LD, 1), Ch);
}
-void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDOperand &Lo,
- SDOperand &Hi) {
+void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
+ SDValue &Hi) {
// Get the dest types - they may not match the input types, e.g. int_to_fp.
MVT LoVT, HiVT;
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
@@ -504,11 +504,11 @@
Hi = DAG.getNode(N->getOpcode(), HiVT, Hi);
}
-void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDOperand &Lo,
- SDOperand &Hi) {
+void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDValue &Lo,
+ SDValue &Hi) {
// Build the low part.
- SDOperand Mask = N->getOperand(2);
- SmallVector<SDOperand, 16> Ops;
+ SDValue Mask = N->getOperand(2);
+ SmallVector<SDValue, 16> Ops;
MVT LoVT, HiVT;
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
MVT EltVT = LoVT.getVectorElementType();
@@ -520,7 +520,7 @@
// to be legalized, so this makes the code simpler.
for (unsigned i = 0; i != LoNumElts; ++i) {
unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
- SDOperand InVec = N->getOperand(0);
+ SDValue InVec = N->getOperand(0);
if (Idx >= NumElements) {
InVec = N->getOperand(1);
Idx -= NumElements;
@@ -533,7 +533,7 @@
for (unsigned i = LoNumElts; i != NumElements; ++i) {
unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
- SDOperand InVec = N->getOperand(0);
+ SDValue InVec = N->getOperand(0);
if (Idx >= NumElements) {
InVec = N->getOperand(1);
Idx -= NumElements;
@@ -544,12 +544,12 @@
Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &Ops[0], Ops.size());
}
-void DAGTypeLegalizer::SplitVecRes_VSETCC(SDNode *N, SDOperand &Lo,
- SDOperand &Hi) {
+void DAGTypeLegalizer::SplitVecRes_VSETCC(SDNode *N, SDValue &Lo,
+ SDValue &Hi) {
MVT LoVT, HiVT;
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
- SDOperand LL, LH, RL, RH;
+ SDValue LL, LH, RL, RH;
GetSplitVector(N->getOperand(0), LL, LH);
GetSplitVector(N->getOperand(1), RL, RH);
@@ -568,7 +568,7 @@
/// node may need legalization as well as the specified one.
bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
DEBUG(cerr << "Split node operand: "; N->dump(&DAG); cerr << "\n");
- SDOperand Res = SDOperand();
+ SDValue Res = SDValue();
if (Res.Val == 0) {
switch (N->getOpcode()) {
@@ -605,15 +605,15 @@
assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
"Invalid operand expansion");
- ReplaceValueWith(SDOperand(N, 0), Res);
+ ReplaceValueWith(SDValue(N, 0), Res);
return false;
}
-SDOperand DAGTypeLegalizer::SplitVecOp_BIT_CONVERT(SDNode *N) {
+SDValue DAGTypeLegalizer::SplitVecOp_BIT_CONVERT(SDNode *N) {
// For example, i64 = BIT_CONVERT v4i16 on alpha. Typically the vector will
// end up being split all the way down to individual components. Convert the
// split pieces into integers and reassemble.
- SDOperand Lo, Hi;
+ SDValue Lo, Hi;
GetSplitVector(N->getOperand(0), Lo, Hi);
Lo = BitConvertToInteger(Lo);
Hi = BitConvertToInteger(Hi);
@@ -625,12 +625,12 @@
JoinIntegers(Lo, Hi));
}
-SDOperand DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
+SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
// We know that the extracted result type is legal. For now, assume the index
// is a constant.
MVT SubVT = N->getValueType(0);
- SDOperand Idx = N->getOperand(1);
- SDOperand Lo, Hi;
+ SDValue Idx = N->getOperand(1);
+ SDValue Lo, Hi;
GetSplitVector(N->getOperand(0), Lo, Hi);
uint64_t LoElts = Lo.getValueType().getVectorNumElements();
@@ -646,48 +646,48 @@
}
}
-SDOperand DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
- SDOperand Vec = N->getOperand(0);
- SDOperand Idx = N->getOperand(1);
+SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
+ SDValue Vec = N->getOperand(0);
+ SDValue Idx = N->getOperand(1);
MVT VecVT = Vec.getValueType();
if (isa<ConstantSDNode>(Idx)) {
uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getValue();
assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
- SDOperand Lo, Hi;
+ SDValue Lo, Hi;
GetSplitVector(Vec, Lo, Hi);
uint64_t LoElts = Lo.getValueType().getVectorNumElements();
if (IdxVal < LoElts)
- return DAG.UpdateNodeOperands(SDOperand(N, 0), Lo, Idx);
+ return DAG.UpdateNodeOperands(SDValue(N, 0), Lo, Idx);
else
- return DAG.UpdateNodeOperands(SDOperand(N, 0), Hi,
+ return DAG.UpdateNodeOperands(SDValue(N, 0), Hi,
DAG.getConstant(IdxVal - LoElts,
Idx.getValueType()));
}
// Store the vector to the stack.
MVT EltVT = VecVT.getVectorElementType();
- SDOperand StackPtr = DAG.CreateStackTemporary(VecVT);
- SDOperand Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
+ SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
+ SDValue Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
// Load back the required element.
StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
return DAG.getLoad(EltVT, Store, StackPtr, NULL, 0);
}
-SDOperand DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
+SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
assert(ISD::isNormalStore(N) && "Truncating store of vector?");
assert(OpNo == 1 && "Can only split the stored value");
- SDOperand Ch = N->getChain();
- SDOperand Ptr = N->getBasePtr();
+ SDValue Ch = N->getChain();
+ SDValue Ptr = N->getBasePtr();
int SVOffset = N->getSrcValueOffset();
unsigned Alignment = N->getAlignment();
bool isVol = N->isVolatile();
- SDOperand Lo, Hi;
+ SDValue Lo, Hi;
GetSplitVector(N->getOperand(1), Lo, Hi);
unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8;
@@ -703,9 +703,9 @@
return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
}
-SDOperand DAGTypeLegalizer::SplitVecOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo){
+SDValue DAGTypeLegalizer::SplitVecOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo){
assert(OpNo == 2 && "Shuffle source type differs from result type?");
- SDOperand Mask = N->getOperand(2);
+ SDValue Mask = N->getOperand(2);
unsigned MaskLength = Mask.getValueType().getVectorNumElements();
unsigned LargestMaskEntryPlusOne = 2 * MaskLength;
unsigned MinimumBitWidth = Log2_32_Ceil(LargestMaskEntryPlusOne);
@@ -740,13 +740,13 @@
continue;
// Success! Rebuild the vector using the legal types.
- SmallVector<SDOperand, 16> Ops(MaskLength);
+ SmallVector<SDValue, 16> Ops(MaskLength);
for (unsigned i = 0; i < MaskLength; ++i) {
uint64_t Idx =
cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
Ops[i] = DAG.getConstant(Idx, OpVT);
}
- return DAG.UpdateNodeOperands(SDOperand(N,0),
+ return DAG.UpdateNodeOperands(SDValue(N,0),
N->getOperand(0), N->getOperand(1),
DAG.getNode(ISD::BUILD_VECTOR,
VecVT, &Ops[0], Ops.size()));
@@ -756,5 +756,5 @@
break;
}
assert(false && "Failed to find an appropriate mask type!");
- return SDOperand(N, 0);
+ return SDValue(N, 0);
}
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Sun Jul 27 16:46:04 2008
@@ -136,7 +136,7 @@
// have a user of the flag operand.
N = NI;
while (N->getValueType(N->getNumValues()-1) == MVT::Flag) {
- SDOperand FlagVal(N, N->getNumValues()-1);
+ SDValue FlagVal(N, N->getNumValues()-1);
// There are either zero or one users of the Flag result.
bool HasFlagUse = false;
@@ -408,11 +408,11 @@
/// implicit physical register output.
void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
bool IsClone, unsigned SrcReg,
- DenseMap<SDOperand, unsigned> &VRBaseMap) {
+ DenseMap<SDValue, unsigned> &VRBaseMap) {
unsigned VRBase = 0;
if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
// Just use the input register directly!
- SDOperand Op(Node, ResNo);
+ SDValue Op(Node, ResNo);
if (IsClone)
VRBaseMap.erase(Op);
bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
@@ -439,7 +439,7 @@
Match = false;
} else {
for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
- SDOperand Op = User->getOperand(i);
+ SDValue Op = User->getOperand(i);
if (Op.Val != Node || Op.ResNo != ResNo)
continue;
MVT VT = Node->getValueType(Op.ResNo);
@@ -472,7 +472,7 @@
TII->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, DstRC, SrcRC);
}
- SDOperand Op(Node, ResNo);
+ SDValue Op(Node, ResNo);
if (IsClone)
VRBaseMap.erase(Op);
bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
@@ -500,7 +500,7 @@
void ScheduleDAG::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
const TargetInstrDesc &II,
- DenseMap<SDOperand, unsigned> &VRBaseMap) {
+ DenseMap<SDValue, unsigned> &VRBaseMap) {
assert(Node->getMachineOpcode() != TargetInstrInfo::IMPLICIT_DEF &&
"IMPLICIT_DEF should have been handled as a special case elsewhere!");
@@ -533,7 +533,7 @@
MI->addOperand(MachineOperand::CreateReg(VRBase, true));
}
- SDOperand Op(Node, i);
+ SDValue Op(Node, i);
bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
isNew = isNew; // Silence compiler warning.
assert(isNew && "Node emitted out of order - early");
@@ -542,8 +542,8 @@
/// getVR - Return the virtual register corresponding to the specified result
/// of the specified node.
-unsigned ScheduleDAG::getVR(SDOperand Op,
- DenseMap<SDOperand, unsigned> &VRBaseMap) {
+unsigned ScheduleDAG::getVR(SDValue Op,
+ DenseMap<SDValue, unsigned> &VRBaseMap) {
if (Op.isMachineOpcode() &&
Op.getMachineOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
// Add an IMPLICIT_DEF instruction before every use.
@@ -558,7 +558,7 @@
return VReg;
}
- DenseMap<SDOperand, unsigned>::iterator I = VRBaseMap.find(Op);
+ DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
assert(I != VRBaseMap.end() && "Node emitted out of order - late");
return I->second;
}
@@ -568,10 +568,10 @@
/// specifies the instruction information for the node, and IIOpNum is the
/// operand number (in the II) that we are adding. IIOpNum and II are used for
/// assertions only.
-void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
+void ScheduleDAG::AddOperand(MachineInstr *MI, SDValue Op,
unsigned IIOpNum,
const TargetInstrDesc *II,
- DenseMap<SDOperand, unsigned> &VRBaseMap) {
+ DenseMap<SDValue, unsigned> &VRBaseMap) {
if (Op.isMachineOpcode()) {
// Note that this case is redundant with the final else block, but we
// include it because it is the most common and it makes the logic
@@ -702,7 +702,7 @@
/// EmitSubregNode - Generate machine code for subreg nodes.
///
void ScheduleDAG::EmitSubregNode(SDNode *Node,
- DenseMap<SDOperand, unsigned> &VRBaseMap) {
+ DenseMap<SDValue, unsigned> &VRBaseMap) {
unsigned VRBase = 0;
unsigned Opc = Node->getMachineOpcode();
@@ -752,9 +752,9 @@
BB->push_back(MI);
} else if (Opc == TargetInstrInfo::INSERT_SUBREG ||
Opc == TargetInstrInfo::SUBREG_TO_REG) {
- SDOperand N0 = Node->getOperand(0);
- SDOperand N1 = Node->getOperand(1);
- SDOperand N2 = Node->getOperand(2);
+ SDValue N0 = Node->getOperand(0);
+ SDValue N1 = Node->getOperand(1);
+ SDValue N2 = Node->getOperand(2);
unsigned SubReg = getVR(N1, VRBaseMap);
unsigned SubIdx = cast<ConstantSDNode>(N2)->getValue();
@@ -788,7 +788,7 @@
} else
assert(0 && "Node is not insert_subreg, extract_subreg, or subreg_to_reg");
- SDOperand Op(Node, 0);
+ SDValue Op(Node, 0);
bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
isNew = isNew; // Silence compiler warning.
assert(isNew && "Node emitted out of order - early");
@@ -797,7 +797,7 @@
/// EmitNode - Generate machine code for an node and needed dependencies.
///
void ScheduleDAG::EmitNode(SDNode *Node, bool IsClone,
- DenseMap<SDOperand, unsigned> &VRBaseMap) {
+ DenseMap<SDValue, unsigned> &VRBaseMap) {
// If machine instruction
if (Node->isMachineOpcode()) {
unsigned Opc = Node->getMachineOpcode();
@@ -891,7 +891,7 @@
break;
case ISD::CopyToReg: {
unsigned SrcReg;
- SDOperand SrcVal = Node->getOperand(2);
+ SDValue SrcVal = Node->getOperand(2);
if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
SrcReg = R->getReg();
else
@@ -1099,7 +1099,7 @@
}
// Finally, emit the code for all of the scheduled instructions.
- DenseMap<SDOperand, unsigned> VRBaseMap;
+ DenseMap<SDValue, unsigned> VRBaseMap;
DenseMap<SUnit*, unsigned> CopyVRBaseMap;
for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
SUnit *SU = Sequence[i];
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Sun Jul 27 16:46:04 2008
@@ -651,7 +651,7 @@
TryUnfold = true;
}
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
- const SDOperand &Op = N->getOperand(i);
+ const SDValue &Op = N->getOperand(i);
MVT VT = Op.Val->getValueType(Op.ResNo);
if (VT == MVT::Flag)
return NULL;
@@ -670,9 +670,9 @@
unsigned NumVals = N->getNumValues();
unsigned OldNumVals = SU->Node->getNumValues();
for (unsigned i = 0; i != NumVals; ++i)
- DAG.ReplaceAllUsesOfValueWith(SDOperand(SU->Node, i), SDOperand(N, i));
- DAG.ReplaceAllUsesOfValueWith(SDOperand(SU->Node, OldNumVals-1),
- SDOperand(LoadNode, 1));
+ DAG.ReplaceAllUsesOfValueWith(SDValue(SU->Node, i), SDValue(N, i));
+ DAG.ReplaceAllUsesOfValueWith(SDValue(SU->Node, OldNumVals-1),
+ SDValue(LoadNode, 1));
SUnit *NewSU = CreateNewSUnit(N);
assert(N->getNodeId() == -1 && "Node already inserted!");
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Sun Jul 27 16:46:04 2008
@@ -110,7 +110,7 @@
// Do not accept build_vectors that aren't all constants or which have non-~0
// elements.
- SDOperand NotZero = N->getOperand(i);
+ SDValue NotZero = N->getOperand(i);
if (isa<ConstantSDNode>(NotZero)) {
if (!cast<ConstantSDNode>(NotZero)->isAllOnesValue())
return false;
@@ -151,7 +151,7 @@
// Do not accept build_vectors that aren't all constants or which have non-~0
// elements.
- SDOperand Zero = N->getOperand(i);
+ SDValue Zero = N->getOperand(i);
if (isa<ConstantSDNode>(Zero)) {
if (!cast<ConstantSDNode>(Zero)->isNullValue())
return false;
@@ -183,7 +183,7 @@
return false;
unsigned NumElems = N->getNumOperands();
for (unsigned i = 1; i < NumElems; ++i) {
- SDOperand V = N->getOperand(i);
+ SDValue V = N->getOperand(i);
if (V.getOpcode() != ISD::UNDEF)
return false;
}
@@ -194,7 +194,7 @@
/// isDebugLabel - Return true if the specified node represents a debug
/// label (i.e. ISD::DBG_LABEL or TargetInstrInfo::DBG_LABEL node).
bool ISD::isDebugLabel(const SDNode *N) {
- SDOperand Zero;
+ SDValue Zero;
if (N->getOpcode() == ISD::DBG_LABEL)
return true;
if (N->isMachineOpcode() &&
@@ -323,7 +323,7 @@
/// AddNodeIDOperands - Various routines for adding operands to the NodeID data.
///
static void AddNodeIDOperands(FoldingSetNodeID &ID,
- const SDOperand *Ops, unsigned NumOps) {
+ const SDValue *Ops, unsigned NumOps) {
for (; NumOps; --NumOps, ++Ops) {
ID.AddPointer(Ops->Val);
ID.AddInteger(Ops->ResNo);
@@ -335,14 +335,14 @@
static void AddNodeIDOperands(FoldingSetNodeID &ID,
const SDUse *Ops, unsigned NumOps) {
for (; NumOps; --NumOps, ++Ops) {
- ID.AddPointer(Ops->getSDOperand().Val);
- ID.AddInteger(Ops->getSDOperand().ResNo);
+ ID.AddPointer(Ops->getVal());
+ ID.AddInteger(Ops->getSDValue().ResNo);
}
}
static void AddNodeIDNode(FoldingSetNodeID &ID,
unsigned short OpC, SDVTList VTList,
- const SDOperand *OpList, unsigned N) {
+ const SDValue *OpList, unsigned N) {
AddNodeIDOpcode(ID, OpC);
AddNodeIDValueTypes(ID, VTList);
AddNodeIDOperands(ID, OpList, N);
@@ -649,7 +649,7 @@
/// were replaced with those specified. If this node is never memoized,
/// return null, otherwise return a pointer to the slot it would take. If a
/// node already exists with these operands, the slot will be non-null.
-SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, SDOperand Op,
+SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, SDValue Op,
void *&InsertPos) {
if (N->getValueType(0) == MVT::Flag)
return 0; // Never CSE anything that produces a flag.
@@ -668,7 +668,7 @@
if (N->getValueType(i) == MVT::Flag)
return 0; // Never CSE anything that produces a flag.
- SDOperand Ops[] = { Op };
+ SDValue Ops[] = { Op };
FoldingSetNodeID ID;
AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 1);
return CSEMap.FindNodeOrInsertPos(ID, InsertPos);
@@ -679,7 +679,7 @@
/// return null, otherwise return a pointer to the slot it would take. If a
/// node already exists with these operands, the slot will be non-null.
SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N,
- SDOperand Op1, SDOperand Op2,
+ SDValue Op1, SDValue Op2,
void *&InsertPos) {
if (N->getOpcode() == ISD::HANDLENODE || N->getValueType(0) == MVT::Flag)
@@ -688,7 +688,7 @@
if (N->getValueType(i) == MVT::Flag)
return 0; // Never CSE anything that produces a flag.
- SDOperand Ops[] = { Op1, Op2 };
+ SDValue Ops[] = { Op1, Op2 };
FoldingSetNodeID ID;
AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 2);
return CSEMap.FindNodeOrInsertPos(ID, InsertPos);
@@ -700,7 +700,7 @@
/// return null, otherwise return a pointer to the slot it would take. If a
/// node already exists with these operands, the slot will be non-null.
SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N,
- const SDOperand *Ops,unsigned NumOps,
+ const SDValue *Ops,unsigned NumOps,
void *&InsertPos) {
if (N->getValueType(0) == MVT::Flag)
return 0; // Never CSE anything that produces a flag.
@@ -752,7 +752,7 @@
"Wrong number of BUILD_VECTOR operands!");
MVT EltVT = N->getValueType(0).getVectorElementType();
for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I)
- assert(I->getSDOperand().getValueType() == EltVT &&
+ assert(I->getSDValue().getValueType() == EltVT &&
"Wrong BUILD_VECTOR operand type!");
break;
}
@@ -783,7 +783,7 @@
}
}
-SDOperand SelectionDAG::getZeroExtendInReg(SDOperand Op, MVT VT) {
+SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, MVT VT) {
if (Op.getValueType() == VT) return Op;
APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(),
VT.getSizeInBits());
@@ -791,12 +791,12 @@
getConstant(Imm, Op.getValueType()));
}
-SDOperand SelectionDAG::getConstant(uint64_t Val, MVT VT, bool isT) {
+SDValue SelectionDAG::getConstant(uint64_t Val, MVT VT, bool isT) {
MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
return getConstant(APInt(EltVT.getSizeInBits(), Val), VT, isT);
}
-SDOperand SelectionDAG::getConstant(const APInt &Val, MVT VT, bool isT) {
+SDValue SelectionDAG::getConstant(const APInt &Val, MVT VT, bool isT) {
assert(VT.isInteger() && "Cannot create FP integer constant!");
MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
@@ -811,7 +811,7 @@
SDNode *N = NULL;
if ((N = CSEMap.FindNodeOrInsertPos(ID, IP)))
if (!VT.isVector())
- return SDOperand(N, 0);
+ return SDValue(N, 0);
if (!N) {
N = getAllocator().Allocate<ConstantSDNode>();
new (N) ConstantSDNode(isT, Val, EltVT);
@@ -819,21 +819,21 @@
AllNodes.push_back(N);
}
- SDOperand Result(N, 0);
+ SDValue Result(N, 0);
if (VT.isVector()) {
- SmallVector<SDOperand, 8> Ops;
+ SmallVector<SDValue, 8> Ops;
Ops.assign(VT.getVectorNumElements(), Result);
Result = getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
}
return Result;
}
-SDOperand SelectionDAG::getIntPtrConstant(uint64_t Val, bool isTarget) {
+SDValue SelectionDAG::getIntPtrConstant(uint64_t Val, bool isTarget) {
return getConstant(Val, TLI.getPointerTy(), isTarget);
}
-SDOperand SelectionDAG::getConstantFP(const APFloat& V, MVT VT, bool isTarget) {
+SDValue SelectionDAG::getConstantFP(const APFloat& V, MVT VT, bool isTarget) {
assert(VT.isFloatingPoint() && "Cannot create integer FP constant!");
MVT EltVT =
@@ -850,7 +850,7 @@
SDNode *N = NULL;
if ((N = CSEMap.FindNodeOrInsertPos(ID, IP)))
if (!VT.isVector())
- return SDOperand(N, 0);
+ return SDValue(N, 0);
if (!N) {
N = getAllocator().Allocate<ConstantFPSDNode>();
new (N) ConstantFPSDNode(isTarget, V, EltVT);
@@ -858,16 +858,16 @@
AllNodes.push_back(N);
}
- SDOperand Result(N, 0);
+ SDValue Result(N, 0);
if (VT.isVector()) {
- SmallVector<SDOperand, 8> Ops;
+ SmallVector<SDValue, 8> Ops;
Ops.assign(VT.getVectorNumElements(), Result);
Result = getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
}
return Result;
}
-SDOperand SelectionDAG::getConstantFP(double Val, MVT VT, bool isTarget) {
+SDValue SelectionDAG::getConstantFP(double Val, MVT VT, bool isTarget) {
MVT EltVT =
VT.isVector() ? VT.getVectorElementType() : VT;
if (EltVT==MVT::f32)
@@ -876,9 +876,9 @@
return getConstantFP(APFloat(Val), VT, isTarget);
}
-SDOperand SelectionDAG::getGlobalAddress(const GlobalValue *GV,
- MVT VT, int Offset,
- bool isTargetGA) {
+SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV,
+ MVT VT, int Offset,
+ bool isTargetGA) {
unsigned Opc;
const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
@@ -899,47 +899,47 @@
ID.AddInteger(Offset);
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
- return SDOperand(E, 0);
+ return SDValue(E, 0);
SDNode *N = getAllocator().Allocate<GlobalAddressSDNode>();
new (N) GlobalAddressSDNode(isTargetGA, GV, VT, Offset);
CSEMap.InsertNode(N, IP);
AllNodes.push_back(N);
- return SDOperand(N, 0);
+ return SDValue(N, 0);
}
-SDOperand SelectionDAG::getFrameIndex(int FI, MVT VT, bool isTarget) {
+SDValue SelectionDAG::getFrameIndex(int FI, MVT VT, bool isTarget) {
unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex;
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0);
ID.AddInteger(FI);
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
- return SDOperand(E, 0);
+ return SDValue(E, 0);
SDNode *N = getAllocator().Allocate<FrameIndexSDNode>();
new (N) FrameIndexSDNode(FI, VT, isTarget);
CSEMap.InsertNode(N, IP);
AllNodes.push_back(N);
- return SDOperand(N, 0);
+ return SDValue(N, 0);
}
-SDOperand SelectionDAG::getJumpTable(int JTI, MVT VT, bool isTarget){
+SDValue SelectionDAG::getJumpTable(int JTI, MVT VT, bool isTarget){
unsigned Opc = isTarget ? ISD::TargetJumpTable : ISD::JumpTable;
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0);
ID.AddInteger(JTI);
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
- return SDOperand(E, 0);
+ return SDValue(E, 0);
SDNode *N = getAllocator().Allocate<JumpTableSDNode>();
new (N) JumpTableSDNode(JTI, VT, isTarget);
CSEMap.InsertNode(N, IP);
AllNodes.push_back(N);
- return SDOperand(N, 0);
+ return SDValue(N, 0);
}
-SDOperand SelectionDAG::getConstantPool(Constant *C, MVT VT,
- unsigned Alignment, int Offset,
- bool isTarget) {
+SDValue SelectionDAG::getConstantPool(Constant *C, MVT VT,
+ unsigned Alignment, int Offset,
+ bool isTarget) {
unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool;
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0);
@@ -948,18 +948,18 @@
ID.AddPointer(C);
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
- return SDOperand(E, 0);
+ return SDValue(E, 0);
SDNode *N = getAllocator().Allocate<ConstantPoolSDNode>();
new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment);
CSEMap.InsertNode(N, IP);
AllNodes.push_back(N);
- return SDOperand(N, 0);
+ return SDValue(N, 0);
}
-SDOperand SelectionDAG::getConstantPool(MachineConstantPoolValue *C, MVT VT,
- unsigned Alignment, int Offset,
- bool isTarget) {
+SDValue SelectionDAG::getConstantPool(MachineConstantPoolValue *C, MVT VT,
+ unsigned Alignment, int Offset,
+ bool isTarget) {
unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool;
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0);
@@ -968,76 +968,76 @@
C->AddSelectionDAGCSEId(ID);
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
- return SDOperand(E, 0);
+ return SDValue(E, 0);
SDNode *N = getAllocator().Allocate<ConstantPoolSDNode>();
new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment);
CSEMap.InsertNode(N, IP);
AllNodes.push_back(N);
- return SDOperand(N, 0);
+ return SDValue(N, 0);
}
-SDOperand SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) {
+SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) {
FoldingSetNodeID ID;
AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0);
ID.AddPointer(MBB);
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
- return SDOperand(E, 0);
+ return SDValue(E, 0);
SDNode *N = getAllocator().Allocate<BasicBlockSDNode>();
new (N) BasicBlockSDNode(MBB);
CSEMap.InsertNode(N, IP);
AllNodes.push_back(N);
- return SDOperand(N, 0);
+ return SDValue(N, 0);
}
-SDOperand SelectionDAG::getArgFlags(ISD::ArgFlagsTy Flags) {
+SDValue SelectionDAG::getArgFlags(ISD::ArgFlagsTy Flags) {
FoldingSetNodeID ID;
AddNodeIDNode(ID, ISD::ARG_FLAGS, getVTList(MVT::Other), 0, 0);
ID.AddInteger(Flags.getRawBits());
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
- return SDOperand(E, 0);
+ return SDValue(E, 0);
SDNode *N = getAllocator().Allocate<ARG_FLAGSSDNode>();
new (N) ARG_FLAGSSDNode(Flags);
CSEMap.InsertNode(N, IP);
AllNodes.push_back(N);
- return SDOperand(N, 0);
+ return SDValue(N, 0);
}
-SDOperand SelectionDAG::getValueType(MVT VT) {
+SDValue SelectionDAG::getValueType(MVT VT) {
if (VT.isSimple() && (unsigned)VT.getSimpleVT() >= ValueTypeNodes.size())
ValueTypeNodes.resize(VT.getSimpleVT()+1);
SDNode *&N = VT.isExtended() ?
ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT()];
- if (N) return SDOperand(N, 0);
+ if (N) return SDValue(N, 0);
N = getAllocator().Allocate<VTSDNode>();
new (N) VTSDNode(VT);
AllNodes.push_back(N);
- return SDOperand(N, 0);
+ return SDValue(N, 0);
}
-SDOperand SelectionDAG::getExternalSymbol(const char *Sym, MVT VT) {
+SDValue SelectionDAG::getExternalSymbol(const char *Sym, MVT VT) {
SDNode *&N = ExternalSymbols[Sym];
- if (N) return SDOperand(N, 0);
+ if (N) return SDValue(N, 0);
N = getAllocator().Allocate<ExternalSymbolSDNode>();
new (N) ExternalSymbolSDNode(false, Sym, VT);
AllNodes.push_back(N);
- return SDOperand(N, 0);
+ return SDValue(N, 0);
}
-SDOperand SelectionDAG::getTargetExternalSymbol(const char *Sym, MVT VT) {
+SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, MVT VT) {
SDNode *&N = TargetExternalSymbols[Sym];
- if (N) return SDOperand(N, 0);
+ if (N) return SDValue(N, 0);
N = getAllocator().Allocate<ExternalSymbolSDNode>();
new (N) ExternalSymbolSDNode(true, Sym, VT);
AllNodes.push_back(N);
- return SDOperand(N, 0);
+ return SDValue(N, 0);
}
-SDOperand SelectionDAG::getCondCode(ISD::CondCode Cond) {
+SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) {
if ((unsigned)Cond >= CondCodeNodes.size())
CondCodeNodes.resize(Cond+1);
@@ -1047,50 +1047,50 @@
CondCodeNodes[Cond] = N;
AllNodes.push_back(N);
}
- return SDOperand(CondCodeNodes[Cond], 0);
+ return SDValue(CondCodeNodes[Cond], 0);
}
-SDOperand SelectionDAG::getRegister(unsigned RegNo, MVT VT) {
+SDValue SelectionDAG::getRegister(unsigned RegNo, MVT VT) {
FoldingSetNodeID ID;
AddNodeIDNode(ID, ISD::Register, getVTList(VT), 0, 0);
ID.AddInteger(RegNo);
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
- return SDOperand(E, 0);
+ return SDValue(E, 0);
SDNode *N = getAllocator().Allocate<RegisterSDNode>();
new (N) RegisterSDNode(RegNo, VT);
CSEMap.InsertNode(N, IP);
AllNodes.push_back(N);
- return SDOperand(N, 0);
+ return SDValue(N, 0);
}
-SDOperand SelectionDAG::getDbgStopPoint(SDOperand Root,
- unsigned Line, unsigned Col,
- const CompileUnitDesc *CU) {
+SDValue SelectionDAG::getDbgStopPoint(SDValue Root,
+ unsigned Line, unsigned Col,
+ const CompileUnitDesc *CU) {
SDNode *N = getAllocator().Allocate<DbgStopPointSDNode>();
new (N) DbgStopPointSDNode(Root, Line, Col, CU);
AllNodes.push_back(N);
- return SDOperand(N, 0);
+ return SDValue(N, 0);
}
-SDOperand SelectionDAG::getLabel(unsigned Opcode,
- SDOperand Root,
- unsigned LabelID) {
+SDValue SelectionDAG::getLabel(unsigned Opcode,
+ SDValue Root,
+ unsigned LabelID) {
FoldingSetNodeID ID;
- SDOperand Ops[] = { Root };
+ SDValue Ops[] = { Root };
AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1);
ID.AddInteger(LabelID);
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
- return SDOperand(E, 0);
+ return SDValue(E, 0);
SDNode *N = getAllocator().Allocate<LabelSDNode>();
new (N) LabelSDNode(Opcode, Root, LabelID);
CSEMap.InsertNode(N, IP);
AllNodes.push_back(N);
- return SDOperand(N, 0);
+ return SDValue(N, 0);
}
-SDOperand SelectionDAG::getSrcValue(const Value *V) {
+SDValue SelectionDAG::getSrcValue(const Value *V) {
assert((!V || isa<PointerType>(V->getType())) &&
"SrcValue is not a pointer?");
@@ -1100,16 +1100,16 @@
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
- return SDOperand(E, 0);
+ return SDValue(E, 0);
SDNode *N = getAllocator().Allocate<SrcValueSDNode>();
new (N) SrcValueSDNode(V);
CSEMap.InsertNode(N, IP);
AllNodes.push_back(N);
- return SDOperand(N, 0);
+ return SDValue(N, 0);
}
-SDOperand SelectionDAG::getMemOperand(const MachineMemOperand &MO) {
+SDValue SelectionDAG::getMemOperand(const MachineMemOperand &MO) {
const Value *v = MO.getValue();
assert((!v || isa<PointerType>(v->getType())) &&
"SrcValue is not a pointer?");
@@ -1124,18 +1124,18 @@
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
- return SDOperand(E, 0);
+ return SDValue(E, 0);
SDNode *N = getAllocator().Allocate<MemOperandSDNode>();
new (N) MemOperandSDNode(MO);
CSEMap.InsertNode(N, IP);
AllNodes.push_back(N);
- return SDOperand(N, 0);
+ return SDValue(N, 0);
}
/// CreateStackTemporary - Create a stack temporary, suitable for holding the
/// specified value type.
-SDOperand SelectionDAG::CreateStackTemporary(MVT VT, unsigned minAlign) {
+SDValue SelectionDAG::CreateStackTemporary(MVT VT, unsigned minAlign) {
MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo();
unsigned ByteSize = VT.getSizeInBits()/8;
const Type *Ty = VT.getTypeForMVT();
@@ -1146,8 +1146,8 @@
return getFrameIndex(FrameIdx, TLI.getPointerTy());
}
-SDOperand SelectionDAG::FoldSetCC(MVT VT, SDOperand N1,
- SDOperand N2, ISD::CondCode Cond) {
+SDValue SelectionDAG::FoldSetCC(MVT VT, SDValue N1,
+ SDValue N2, ISD::CondCode Cond) {
// These setcc operations always fold.
switch (Cond) {
default: break;
@@ -1194,7 +1194,7 @@
if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.Val)) {
// No compile time operations on this type yet.
if (N1C->getValueType(0) == MVT::ppcf128)
- return SDOperand();
+ return SDValue();
APFloat::cmpResult R = N1C->getValueAPF().compare(N2C->getValueAPF());
switch (Cond) {
@@ -1245,12 +1245,12 @@
}
// Could not fold it.
- return SDOperand();
+ return SDValue();
}
/// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We
/// use this predicate to simplify operations downstream.
-bool SelectionDAG::SignBitIsZero(SDOperand Op, unsigned Depth) const {
+bool SelectionDAG::SignBitIsZero(SDValue Op, unsigned Depth) const {
unsigned BitWidth = Op.getValueSizeInBits();
return MaskedValueIsZero(Op, APInt::getSignBit(BitWidth), Depth);
}
@@ -1258,7 +1258,7 @@
/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use
/// this predicate to simplify operations downstream. Mask is known to be zero
/// for bits that V cannot have.
-bool SelectionDAG::MaskedValueIsZero(SDOperand Op, const APInt &Mask,
+bool SelectionDAG::MaskedValueIsZero(SDValue Op, const APInt &Mask,
unsigned Depth) const {
APInt KnownZero, KnownOne;
ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth);
@@ -1270,7 +1270,7 @@
/// known to be either zero or one and return them in the KnownZero/KnownOne
/// bitsets. This code only analyzes bits in Mask, in order to short-circuit
/// processing.
-void SelectionDAG::ComputeMaskedBits(SDOperand Op, const APInt &Mask,
+void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask,
APInt &KnownZero, APInt &KnownOne,
unsigned Depth) const {
unsigned BitWidth = Mask.getBitWidth();
@@ -1720,7 +1720,7 @@
/// is always equal to the sign bit (itself), but other cases can give us
/// information. For example, immediately after an "SRA X, 2", we know that
/// the top 3 bits are all equal to each other, so we return 3.
-unsigned SelectionDAG::ComputeNumSignBits(SDOperand Op, unsigned Depth) const{
+unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{
MVT VT = Op.getValueType();
assert(VT.isInteger() && "Invalid VT!");
unsigned VTBits = VT.getSizeInBits();
@@ -1932,7 +1932,7 @@
}
-bool SelectionDAG::isVerifiedDebugInfoDesc(SDOperand Op) const {
+bool SelectionDAG::isVerifiedDebugInfoDesc(SDValue Op) const {
GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
if (!GA) return false;
GlobalVariable *GV = dyn_cast<GlobalVariable>(GA->getGlobal());
@@ -1944,21 +1944,21 @@
/// getShuffleScalarElt - Returns the scalar element that will make up the ith
/// element of the result of the vector shuffle.
-SDOperand SelectionDAG::getShuffleScalarElt(const SDNode *N, unsigned i) {
+SDValue SelectionDAG::getShuffleScalarElt(const SDNode *N, unsigned i) {
MVT VT = N->getValueType(0);
- SDOperand PermMask = N->getOperand(2);
- SDOperand Idx = PermMask.getOperand(i);
+ SDValue PermMask = N->getOperand(2);
+ SDValue Idx = PermMask.getOperand(i);
if (Idx.getOpcode() == ISD::UNDEF)
return getNode(ISD::UNDEF, VT.getVectorElementType());
unsigned Index = cast<ConstantSDNode>(Idx)->getValue();
unsigned NumElems = PermMask.getNumOperands();
- SDOperand V = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
+ SDValue V = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
Index %= NumElems;
if (V.getOpcode() == ISD::BIT_CONVERT) {
V = V.getOperand(0);
if (V.getValueType().getVectorNumElements() != NumElems)
- return SDOperand();
+ return SDValue();
}
if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
return (Index == 0) ? V.getOperand(0)
@@ -1967,18 +1967,18 @@
return V.getOperand(Index);
if (V.getOpcode() == ISD::VECTOR_SHUFFLE)
return getShuffleScalarElt(V.Val, Index);
- return SDOperand();
+ return SDValue();
}
/// getNode - Gets or creates the specified node.
///
-SDOperand SelectionDAG::getNode(unsigned Opcode, MVT VT) {
+SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT) {
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opcode, getVTList(VT), 0, 0);
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
- return SDOperand(E, 0);
+ return SDValue(E, 0);
SDNode *N = getAllocator().Allocate<SDNode>();
new (N) SDNode(Opcode, SDNode::getSDVTList(VT));
CSEMap.InsertNode(N, IP);
@@ -1987,10 +1987,10 @@
#ifndef NDEBUG
VerifyNode(N);
#endif
- return SDOperand(N, 0);
+ return SDValue(N, 0);
}
-SDOperand SelectionDAG::getNode(unsigned Opcode, MVT VT, SDOperand Operand) {
+SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, SDValue Operand) {
// Constant fold unary operations with an integer constant operand.
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.Val)) {
const APInt &Val = C->getAPIntValue();
@@ -2171,11 +2171,11 @@
SDVTList VTs = getVTList(VT);
if (VT != MVT::Flag) { // Don't CSE flag producing nodes
FoldingSetNodeID ID;
- SDOperand Ops[1] = { Operand };
+ SDValue Ops[1] = { Operand };
AddNodeIDNode(ID, Opcode, VTs, Ops, 1);
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
- return SDOperand(E, 0);
+ return SDValue(E, 0);
N = getAllocator().Allocate<UnarySDNode>();
new (N) UnarySDNode(Opcode, VTs, Operand);
CSEMap.InsertNode(N, IP);
@@ -2188,11 +2188,11 @@
#ifndef NDEBUG
VerifyNode(N);
#endif
- return SDOperand(N, 0);
+ return SDValue(N, 0);
}
-SDOperand SelectionDAG::getNode(unsigned Opcode, MVT VT,
- SDOperand N1, SDOperand N2) {
+SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
+ SDValue N1, SDValue N2) {
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
switch (Opcode) {
@@ -2524,12 +2524,12 @@
SDNode *N;
SDVTList VTs = getVTList(VT);
if (VT != MVT::Flag) {
- SDOperand Ops[] = { N1, N2 };
+ SDValue Ops[] = { N1, N2 };
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opcode, VTs, Ops, 2);
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
- return SDOperand(E, 0);
+ return SDValue(E, 0);
N = getAllocator().Allocate<BinarySDNode>();
new (N) BinarySDNode(Opcode, VTs, N1, N2);
CSEMap.InsertNode(N, IP);
@@ -2542,18 +2542,18 @@
#ifndef NDEBUG
VerifyNode(N);
#endif
- return SDOperand(N, 0);
+ return SDValue(N, 0);
}
-SDOperand SelectionDAG::getNode(unsigned Opcode, MVT VT,
- SDOperand N1, SDOperand N2, SDOperand N3) {
+SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
+ SDValue N1, SDValue N2, SDValue N3) {
// Perform various simplifications.
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
switch (Opcode) {
case ISD::SETCC: {
// Use FoldSetCC to simplify SETCC's.
- SDOperand Simp = FoldSetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get());
+ SDValue Simp = FoldSetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get());
if (Simp.Val) return Simp;
break;
}
@@ -2593,12 +2593,12 @@
SDNode *N;
SDVTList VTs = getVTList(VT);
if (VT != MVT::Flag) {
- SDOperand Ops[] = { N1, N2, N3 };
+ SDValue Ops[] = { N1, N2, N3 };
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opcode, VTs, Ops, 3);
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
- return SDOperand(E, 0);
+ return SDValue(E, 0);
N = getAllocator().Allocate<TernarySDNode>();
new (N) TernarySDNode(Opcode, VTs, N1, N2, N3);
CSEMap.InsertNode(N, IP);
@@ -2610,26 +2610,26 @@
#ifndef NDEBUG
VerifyNode(N);
#endif
- return SDOperand(N, 0);
+ return SDValue(N, 0);
}
-SDOperand SelectionDAG::getNode(unsigned Opcode, MVT VT,
- SDOperand N1, SDOperand N2, SDOperand N3,
- SDOperand N4) {
- SDOperand Ops[] = { N1, N2, N3, N4 };
+SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
+ SDValue N1, SDValue N2, SDValue N3,
+ SDValue N4) {
+ SDValue Ops[] = { N1, N2, N3, N4 };
return getNode(Opcode, VT, Ops, 4);
}
-SDOperand SelectionDAG::getNode(unsigned Opcode, MVT VT,
- SDOperand N1, SDOperand N2, SDOperand N3,
- SDOperand N4, SDOperand N5) {
- SDOperand Ops[] = { N1, N2, N3, N4, N5 };
+SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
+ SDValue N1, SDValue N2, SDValue N3,
+ SDValue N4, SDValue N5) {
+ SDValue Ops[] = { N1, N2, N3, N4, N5 };
return getNode(Opcode, VT, Ops, 5);
}
/// getMemsetValue - Vectorized representation of the memset value
/// operand.
-static SDOperand getMemsetValue(SDOperand Value, MVT VT, SelectionDAG &DAG) {
+static SDValue getMemsetValue(SDValue Value, MVT VT, SelectionDAG &DAG) {
unsigned NumBits = VT.isVector() ?
VT.getVectorElementType().getSizeInBits() : VT.getSizeInBits();
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
@@ -2659,7 +2659,7 @@
/// getMemsetStringVal - Similar to getMemsetValue. Except this is only
/// used when a memcpy is turned into a memset when the source is a constant
/// string ptr.
-static SDOperand getMemsetStringVal(MVT VT, SelectionDAG &DAG,
+static SDValue getMemsetStringVal(MVT VT, SelectionDAG &DAG,
const TargetLowering &TLI,
std::string &Str, unsigned Offset) {
// Handle vector with all elements zero.
@@ -2687,7 +2687,7 @@
/// getMemBasePlusOffset - Returns base and offset node for the
///
-static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset,
+static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset,
SelectionDAG &DAG) {
MVT VT = Base.getValueType();
return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT));
@@ -2695,7 +2695,7 @@
/// isMemSrcFromString - Returns true if memcpy source is a string constant.
///
-static bool isMemSrcFromString(SDOperand Src, std::string &Str) {
+static bool isMemSrcFromString(SDValue Src, std::string &Str) {
unsigned SrcDelta = 0;
GlobalAddressSDNode *G = NULL;
if (Src.getOpcode() == ISD::GlobalAddress)
@@ -2721,7 +2721,7 @@
/// types of the sequence of memory ops to perform memset / memcpy.
static
bool MeetsMaxMemopRequirement(std::vector<MVT> &MemOps,
- SDOperand Dst, SDOperand Src,
+ SDValue Dst, SDValue Src,
unsigned Limit, uint64_t Size, unsigned &Align,
std::string &Str, bool &isSrcStr,
SelectionDAG &DAG,
@@ -2802,9 +2802,9 @@
return true;
}
-static SDOperand getMemcpyLoadsAndStores(SelectionDAG &DAG,
- SDOperand Chain, SDOperand Dst,
- SDOperand Src, uint64_t Size,
+static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG,
+ SDValue Chain, SDValue Dst,
+ SDValue Src, uint64_t Size,
unsigned Align, bool AlwaysInline,
const Value *DstSV, uint64_t DstSVOff,
const Value *SrcSV, uint64_t SrcSVOff){
@@ -2821,17 +2821,17 @@
bool CopyFromStr;
if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign,
Str, CopyFromStr, DAG, TLI))
- return SDOperand();
+ return SDValue();
bool isZeroStr = CopyFromStr && Str.empty();
- SmallVector<SDOperand, 8> OutChains;
+ SmallVector<SDValue, 8> OutChains;
unsigned NumMemOps = MemOps.size();
uint64_t SrcOff = 0, DstOff = 0;
for (unsigned i = 0; i < NumMemOps; i++) {
MVT VT = MemOps[i];
unsigned VTSize = VT.getSizeInBits() / 8;
- SDOperand Value, Store;
+ SDValue Value, Store;
if (CopyFromStr && (isZeroStr || !VT.isVector())) {
// It's unlikely a store of a vector immediate can be done in a single
@@ -2860,9 +2860,9 @@
&OutChains[0], OutChains.size());
}
-static SDOperand getMemmoveLoadsAndStores(SelectionDAG &DAG,
- SDOperand Chain, SDOperand Dst,
- SDOperand Src, uint64_t Size,
+static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG,
+ SDValue Chain, SDValue Dst,
+ SDValue Src, uint64_t Size,
unsigned Align, bool AlwaysInline,
const Value *DstSV, uint64_t DstSVOff,
const Value *SrcSV, uint64_t SrcSVOff){
@@ -2879,18 +2879,18 @@
bool CopyFromStr;
if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign,
Str, CopyFromStr, DAG, TLI))
- return SDOperand();
+ return SDValue();
uint64_t SrcOff = 0, DstOff = 0;
- SmallVector<SDOperand, 8> LoadValues;
- SmallVector<SDOperand, 8> LoadChains;
- SmallVector<SDOperand, 8> OutChains;
+ SmallVector<SDValue, 8> LoadValues;
+ SmallVector<SDValue, 8> LoadChains;
+ SmallVector<SDValue, 8> OutChains;
unsigned NumMemOps = MemOps.size();
for (unsigned i = 0; i < NumMemOps; i++) {
MVT VT = MemOps[i];
unsigned VTSize = VT.getSizeInBits() / 8;
- SDOperand Value, Store;
+ SDValue Value, Store;
Value = DAG.getLoad(VT, Chain,
getMemBasePlusOffset(Src, SrcOff, DAG),
@@ -2905,7 +2905,7 @@
for (unsigned i = 0; i < NumMemOps; i++) {
MVT VT = MemOps[i];
unsigned VTSize = VT.getSizeInBits() / 8;
- SDOperand Value, Store;
+ SDValue Value, Store;
Store = DAG.getStore(Chain, LoadValues[i],
getMemBasePlusOffset(Dst, DstOff, DAG),
@@ -2918,9 +2918,9 @@
&OutChains[0], OutChains.size());
}
-static SDOperand getMemsetStores(SelectionDAG &DAG,
- SDOperand Chain, SDOperand Dst,
- SDOperand Src, uint64_t Size,
+static SDValue getMemsetStores(SelectionDAG &DAG,
+ SDValue Chain, SDValue Dst,
+ SDValue Src, uint64_t Size,
unsigned Align,
const Value *DstSV, uint64_t DstSVOff) {
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
@@ -2932,17 +2932,17 @@
bool CopyFromStr;
if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, TLI.getMaxStoresPerMemset(),
Size, Align, Str, CopyFromStr, DAG, TLI))
- return SDOperand();
+ return SDValue();
- SmallVector<SDOperand, 8> OutChains;
+ SmallVector<SDValue, 8> OutChains;
uint64_t DstOff = 0;
unsigned NumMemOps = MemOps.size();
for (unsigned i = 0; i < NumMemOps; i++) {
MVT VT = MemOps[i];
unsigned VTSize = VT.getSizeInBits() / 8;
- SDOperand Value = getMemsetValue(Src, VT, DAG);
- SDOperand Store = DAG.getStore(Chain, Value,
+ SDValue Value = getMemsetValue(Src, VT, DAG);
+ SDValue Store = DAG.getStore(Chain, Value,
getMemBasePlusOffset(Dst, DstOff, DAG),
DstSV, DstSVOff + DstOff);
OutChains.push_back(Store);
@@ -2953,11 +2953,11 @@
&OutChains[0], OutChains.size());
}
-SDOperand SelectionDAG::getMemcpy(SDOperand Chain, SDOperand Dst,
- SDOperand Src, SDOperand Size,
- unsigned Align, bool AlwaysInline,
- const Value *DstSV, uint64_t DstSVOff,
- const Value *SrcSV, uint64_t SrcSVOff) {
+SDValue SelectionDAG::getMemcpy(SDValue Chain, SDValue Dst,
+ SDValue Src, SDValue Size,
+ unsigned Align, bool AlwaysInline,
+ const Value *DstSV, uint64_t DstSVOff,
+ const Value *SrcSV, uint64_t SrcSVOff) {
// Check to see if we should lower the memcpy to loads and stores first.
// For cases within the target-specified limits, this is the best choice.
@@ -2967,7 +2967,7 @@
if (ConstantSize->isNullValue())
return Chain;
- SDOperand Result =
+ SDValue Result =
getMemcpyLoadsAndStores(*this, Chain, Dst, Src, ConstantSize->getValue(),
Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff);
if (Result.Val)
@@ -2976,7 +2976,7 @@
// Then check to see if we should lower the memcpy with target-specific
// code. If the target chooses to do this, this is the next best.
- SDOperand Result =
+ SDValue Result =
TLI.EmitTargetCodeForMemcpy(*this, Chain, Dst, Src, Size, Align,
AlwaysInline,
DstSV, DstSVOff, SrcSV, SrcSVOff);
@@ -2999,7 +2999,7 @@
Entry.Node = Dst; Args.push_back(Entry);
Entry.Node = Src; Args.push_back(Entry);
Entry.Node = Size; Args.push_back(Entry);
- std::pair<SDOperand,SDOperand> CallResult =
+ std::pair<SDValue,SDValue> CallResult =
TLI.LowerCallTo(Chain, Type::VoidTy,
false, false, false, CallingConv::C, false,
getExternalSymbol("memcpy", TLI.getPointerTy()),
@@ -3007,11 +3007,11 @@
return CallResult.second;
}
-SDOperand SelectionDAG::getMemmove(SDOperand Chain, SDOperand Dst,
- SDOperand Src, SDOperand Size,
- unsigned Align,
- const Value *DstSV, uint64_t DstSVOff,
- const Value *SrcSV, uint64_t SrcSVOff) {
+SDValue SelectionDAG::getMemmove(SDValue Chain, SDValue Dst,
+ SDValue Src, SDValue Size,
+ unsigned Align,
+ const Value *DstSV, uint64_t DstSVOff,
+ const Value *SrcSV, uint64_t SrcSVOff) {
// Check to see if we should lower the memmove to loads and stores first.
// For cases within the target-specified limits, this is the best choice.
@@ -3021,7 +3021,7 @@
if (ConstantSize->isNullValue())
return Chain;
- SDOperand Result =
+ SDValue Result =
getMemmoveLoadsAndStores(*this, Chain, Dst, Src, ConstantSize->getValue(),
Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff);
if (Result.Val)
@@ -3030,7 +3030,7 @@
// Then check to see if we should lower the memmove with target-specific
// code. If the target chooses to do this, this is the next best.
- SDOperand Result =
+ SDValue Result =
TLI.EmitTargetCodeForMemmove(*this, Chain, Dst, Src, Size, Align,
DstSV, DstSVOff, SrcSV, SrcSVOff);
if (Result.Val)
@@ -3043,7 +3043,7 @@
Entry.Node = Dst; Args.push_back(Entry);
Entry.Node = Src; Args.push_back(Entry);
Entry.Node = Size; Args.push_back(Entry);
- std::pair<SDOperand,SDOperand> CallResult =
+ std::pair<SDValue,SDValue> CallResult =
TLI.LowerCallTo(Chain, Type::VoidTy,
false, false, false, CallingConv::C, false,
getExternalSymbol("memmove", TLI.getPointerTy()),
@@ -3051,10 +3051,10 @@
return CallResult.second;
}
-SDOperand SelectionDAG::getMemset(SDOperand Chain, SDOperand Dst,
- SDOperand Src, SDOperand Size,
- unsigned Align,
- const Value *DstSV, uint64_t DstSVOff) {
+SDValue SelectionDAG::getMemset(SDValue Chain, SDValue Dst,
+ SDValue Src, SDValue Size,
+ unsigned Align,
+ const Value *DstSV, uint64_t DstSVOff) {
// Check to see if we should lower the memset to stores first.
// For cases within the target-specified limits, this is the best choice.
@@ -3064,7 +3064,7 @@
if (ConstantSize->isNullValue())
return Chain;
- SDOperand Result =
+ SDValue Result =
getMemsetStores(*this, Chain, Dst, Src, ConstantSize->getValue(), Align,
DstSV, DstSVOff);
if (Result.Val)
@@ -3073,7 +3073,7 @@
// Then check to see if we should lower the memset with target-specific
// code. If the target chooses to do this, this is the next best.
- SDOperand Result =
+ SDValue Result =
TLI.EmitTargetCodeForMemset(*this, Chain, Dst, Src, Size, Align,
DstSV, DstSVOff);
if (Result.Val)
@@ -3094,7 +3094,7 @@
Args.push_back(Entry);
Entry.Node = Size; Entry.Ty = IntPtrTy; Entry.isSExt = false;
Args.push_back(Entry);
- std::pair<SDOperand,SDOperand> CallResult =
+ std::pair<SDValue,SDValue> CallResult =
TLI.LowerCallTo(Chain, Type::VoidTy,
false, false, false, CallingConv::C, false,
getExternalSymbol("memset", TLI.getPointerTy()),
@@ -3102,10 +3102,10 @@
return CallResult.second;
}
-SDOperand SelectionDAG::getAtomic(unsigned Opcode, SDOperand Chain,
- SDOperand Ptr, SDOperand Cmp,
- SDOperand Swp, const Value* PtrVal,
- unsigned Alignment) {
+SDValue SelectionDAG::getAtomic(unsigned Opcode, SDValue Chain,
+ SDValue Ptr, SDValue Cmp,
+ SDValue Swp, const Value* PtrVal,
+ unsigned Alignment) {
assert(Opcode == ISD::ATOMIC_CMP_SWAP && "Invalid Atomic Op");
assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types");
@@ -3116,22 +3116,22 @@
SDVTList VTs = getVTList(VT, MVT::Other);
FoldingSetNodeID ID;
- SDOperand Ops[] = {Chain, Ptr, Cmp, Swp};
+ SDValue Ops[] = {Chain, Ptr, Cmp, Swp};
AddNodeIDNode(ID, Opcode, VTs, Ops, 4);
void* IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
- return SDOperand(E, 0);
+ return SDValue(E, 0);
SDNode* N = getAllocator().Allocate<AtomicSDNode>();
new (N) AtomicSDNode(Opcode, VTs, Chain, Ptr, Cmp, Swp, PtrVal, Alignment);
CSEMap.InsertNode(N, IP);
AllNodes.push_back(N);
- return SDOperand(N, 0);
+ return SDValue(N, 0);
}
-SDOperand SelectionDAG::getAtomic(unsigned Opcode, SDOperand Chain,
- SDOperand Ptr, SDOperand Val,
- const Value* PtrVal,
- unsigned Alignment) {
+SDValue SelectionDAG::getAtomic(unsigned Opcode, SDValue Chain,
+ SDValue Ptr, SDValue Val,
+ const Value* PtrVal,
+ unsigned Alignment) {
assert(( Opcode == ISD::ATOMIC_LOAD_ADD || Opcode == ISD::ATOMIC_LOAD_SUB
|| Opcode == ISD::ATOMIC_SWAP || Opcode == ISD::ATOMIC_LOAD_AND
|| Opcode == ISD::ATOMIC_LOAD_OR || Opcode == ISD::ATOMIC_LOAD_XOR
@@ -3147,22 +3147,22 @@
SDVTList VTs = getVTList(VT, MVT::Other);
FoldingSetNodeID ID;
- SDOperand Ops[] = {Chain, Ptr, Val};
+ SDValue Ops[] = {Chain, Ptr, Val};
AddNodeIDNode(ID, Opcode, VTs, Ops, 3);
void* IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
- return SDOperand(E, 0);
+ return SDValue(E, 0);
SDNode* N = getAllocator().Allocate<AtomicSDNode>();
new (N) AtomicSDNode(Opcode, VTs, Chain, Ptr, Val, PtrVal, Alignment);
CSEMap.InsertNode(N, IP);
AllNodes.push_back(N);
- return SDOperand(N, 0);
+ return SDValue(N, 0);
}
/// getMergeValues - Create a MERGE_VALUES node from the given operands.
/// Allowed to return something different (and simpler) if Simplify is true.
-SDOperand SelectionDAG::getMergeValues(const SDOperand *Ops, unsigned NumOps,
- bool Simplify) {
+SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps,
+ bool Simplify) {
if (Simplify && NumOps == 1)
return Ops[0];
@@ -3173,10 +3173,10 @@
return getNode(ISD::MERGE_VALUES, getVTList(&VTs[0], NumOps), Ops, NumOps);
}
-SDOperand
+SDValue
SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
- MVT VT, SDOperand Chain,
- SDOperand Ptr, SDOperand Offset,
+ MVT VT, SDValue Chain,
+ SDValue Ptr, SDValue Offset,
const Value *SV, int SVOffset, MVT EVT,
bool isVolatile, unsigned Alignment) {
if (Alignment == 0) // Ensure that codegen never sees alignment 0
@@ -3205,7 +3205,7 @@
SDVTList VTs = Indexed ?
getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other);
- SDOperand Ops[] = { Chain, Ptr, Offset };
+ SDValue Ops[] = { Chain, Ptr, Offset };
FoldingSetNodeID ID;
AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3);
ID.AddInteger(AM);
@@ -3215,37 +3215,37 @@
ID.AddInteger(isVolatile);
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
- return SDOperand(E, 0);
+ return SDValue(E, 0);
SDNode *N = getAllocator().Allocate<LoadSDNode>();
new (N) LoadSDNode(Ops, VTs, AM, ExtType, EVT, SV, SVOffset,
Alignment, isVolatile);
CSEMap.InsertNode(N, IP);
AllNodes.push_back(N);
- return SDOperand(N, 0);
+ return SDValue(N, 0);
}
-SDOperand SelectionDAG::getLoad(MVT VT,
- SDOperand Chain, SDOperand Ptr,
- const Value *SV, int SVOffset,
- bool isVolatile, unsigned Alignment) {
- SDOperand Undef = getNode(ISD::UNDEF, Ptr.getValueType());
+SDValue SelectionDAG::getLoad(MVT VT,
+ SDValue Chain, SDValue Ptr,
+ const Value *SV, int SVOffset,
+ bool isVolatile, unsigned Alignment) {
+ SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType());
return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, Chain, Ptr, Undef,
SV, SVOffset, VT, isVolatile, Alignment);
}
-SDOperand SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, MVT VT,
- SDOperand Chain, SDOperand Ptr,
- const Value *SV,
- int SVOffset, MVT EVT,
- bool isVolatile, unsigned Alignment) {
- SDOperand Undef = getNode(ISD::UNDEF, Ptr.getValueType());
+SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, MVT VT,
+ SDValue Chain, SDValue Ptr,
+ const Value *SV,
+ int SVOffset, MVT EVT,
+ bool isVolatile, unsigned Alignment) {
+ SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType());
return getLoad(ISD::UNINDEXED, ExtType, VT, Chain, Ptr, Undef,
SV, SVOffset, EVT, isVolatile, Alignment);
}
-SDOperand
-SelectionDAG::getIndexedLoad(SDOperand OrigLoad, SDOperand Base,
- SDOperand Offset, ISD::MemIndexedMode AM) {
+SDValue
+SelectionDAG::getIndexedLoad(SDValue OrigLoad, SDValue Base,
+ SDValue Offset, ISD::MemIndexedMode AM) {
LoadSDNode *LD = cast<LoadSDNode>(OrigLoad);
assert(LD->getOffset().getOpcode() == ISD::UNDEF &&
"Load is already a indexed load!");
@@ -3255,17 +3255,17 @@
LD->isVolatile(), LD->getAlignment());
}
-SDOperand SelectionDAG::getStore(SDOperand Chain, SDOperand Val,
- SDOperand Ptr, const Value *SV, int SVOffset,
- bool isVolatile, unsigned Alignment) {
+SDValue SelectionDAG::getStore(SDValue Chain, SDValue Val,
+ SDValue Ptr, const Value *SV, int SVOffset,
+ bool isVolatile, unsigned Alignment) {
MVT VT = Val.getValueType();
if (Alignment == 0) // Ensure that codegen never sees alignment 0
Alignment = getMVTAlignment(VT);
SDVTList VTs = getVTList(MVT::Other);
- SDOperand Undef = getNode(ISD::UNDEF, Ptr.getValueType());
- SDOperand Ops[] = { Chain, Val, Ptr, Undef };
+ SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType());
+ SDValue Ops[] = { Chain, Val, Ptr, Undef };
FoldingSetNodeID ID;
AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
ID.AddInteger(ISD::UNINDEXED);
@@ -3275,19 +3275,19 @@
ID.AddInteger(isVolatile);
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
- return SDOperand(E, 0);
+ return SDValue(E, 0);
SDNode *N = getAllocator().Allocate<StoreSDNode>();
new (N) StoreSDNode(Ops, VTs, ISD::UNINDEXED, false,
VT, SV, SVOffset, Alignment, isVolatile);
CSEMap.InsertNode(N, IP);
AllNodes.push_back(N);
- return SDOperand(N, 0);
+ return SDValue(N, 0);
}
-SDOperand SelectionDAG::getTruncStore(SDOperand Chain, SDOperand Val,
- SDOperand Ptr, const Value *SV,
- int SVOffset, MVT SVT,
- bool isVolatile, unsigned Alignment) {
+SDValue SelectionDAG::getTruncStore(SDValue Chain, SDValue Val,
+ SDValue Ptr, const Value *SV,
+ int SVOffset, MVT SVT,
+ bool isVolatile, unsigned Alignment) {
MVT VT = Val.getValueType();
if (VT == SVT)
@@ -3301,8 +3301,8 @@
Alignment = getMVTAlignment(VT);
SDVTList VTs = getVTList(MVT::Other);
- SDOperand Undef = getNode(ISD::UNDEF, Ptr.getValueType());
- SDOperand Ops[] = { Chain, Val, Ptr, Undef };
+ SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType());
+ SDValue Ops[] = { Chain, Val, Ptr, Undef };
FoldingSetNodeID ID;
AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
ID.AddInteger(ISD::UNINDEXED);
@@ -3312,23 +3312,23 @@
ID.AddInteger(isVolatile);
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
- return SDOperand(E, 0);
+ return SDValue(E, 0);
SDNode *N = getAllocator().Allocate<StoreSDNode>();
new (N) StoreSDNode(Ops, VTs, ISD::UNINDEXED, true,
SVT, SV, SVOffset, Alignment, isVolatile);
CSEMap.InsertNode(N, IP);
AllNodes.push_back(N);
- return SDOperand(N, 0);
+ return SDValue(N, 0);
}
-SDOperand
-SelectionDAG::getIndexedStore(SDOperand OrigStore, SDOperand Base,
- SDOperand Offset, ISD::MemIndexedMode AM) {
+SDValue
+SelectionDAG::getIndexedStore(SDValue OrigStore, SDValue Base,
+ SDValue Offset, ISD::MemIndexedMode AM) {
StoreSDNode *ST = cast<StoreSDNode>(OrigStore);
assert(ST->getOffset().getOpcode() == ISD::UNDEF &&
"Store is already a indexed store!");
SDVTList VTs = getVTList(Base.getValueType(), MVT::Other);
- SDOperand Ops[] = { ST->getChain(), ST->getValue(), Base, Offset };
+ SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset };
FoldingSetNodeID ID;
AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
ID.AddInteger(AM);
@@ -3338,7 +3338,7 @@
ID.AddInteger(ST->isVolatile());
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
- return SDOperand(E, 0);
+ return SDValue(E, 0);
SDNode *N = getAllocator().Allocate<StoreSDNode>();
new (N) StoreSDNode(Ops, VTs, AM,
ST->isTruncatingStore(), ST->getMemoryVT(),
@@ -3346,39 +3346,34 @@
ST->getAlignment(), ST->isVolatile());
CSEMap.InsertNode(N, IP);
AllNodes.push_back(N);
- return SDOperand(N, 0);
+ return SDValue(N, 0);
}
-SDOperand SelectionDAG::getVAArg(MVT VT,
- SDOperand Chain, SDOperand Ptr,
- SDOperand SV) {
- SDOperand Ops[] = { Chain, Ptr, SV };
+SDValue SelectionDAG::getVAArg(MVT VT,
+ SDValue Chain, SDValue Ptr,
+ SDValue SV) {
+ SDValue Ops[] = { Chain, Ptr, SV };
return getNode(ISD::VAARG, getVTList(VT, MVT::Other), Ops, 3);
}
-SDOperand SelectionDAG::getNode(unsigned Opcode, MVT VT,
- const SDUse *Ops, unsigned NumOps) {
+SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
+ const SDUse *Ops, unsigned NumOps) {
switch (NumOps) {
case 0: return getNode(Opcode, VT);
- case 1: return getNode(Opcode, VT, Ops[0].getSDOperand());
- case 2: return getNode(Opcode, VT, Ops[0].getSDOperand(),
- Ops[1].getSDOperand());
- case 3: return getNode(Opcode, VT, Ops[0].getSDOperand(),
- Ops[1].getSDOperand(), Ops[2].getSDOperand());
+ case 1: return getNode(Opcode, VT, Ops[0]);
+ case 2: return getNode(Opcode, VT, Ops[0], Ops[1]);
+ case 3: return getNode(Opcode, VT, Ops[0], Ops[1], Ops[2]);
default: break;
}
- // Copy from an SDUse array into an SDOperand array for use with
+ // Copy from an SDUse array into an SDValue array for use with
// the regular getNode logic.
- SmallVector<SDOperand, 8> NewOps;
- NewOps.reserve(NumOps);
- for (unsigned i = 0; i != NumOps; ++i)
- NewOps.push_back(Ops[i].getSDOperand());
- return getNode(Opcode, VT, Ops, NumOps);
+ SmallVector<SDValue, 8> NewOps(Ops, Ops + NumOps);
+ return getNode(Opcode, VT, &NewOps[0], NumOps);
}
-SDOperand SelectionDAG::getNode(unsigned Opcode, MVT VT,
- const SDOperand *Ops, unsigned NumOps) {
+SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
+ const SDValue *Ops, unsigned NumOps) {
switch (NumOps) {
case 0: return getNode(Opcode, VT);
case 1: return getNode(Opcode, VT, Ops[0]);
@@ -3415,7 +3410,7 @@
AddNodeIDNode(ID, Opcode, VTs, Ops, NumOps);
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
- return SDOperand(E, 0);
+ return SDValue(E, 0);
N = getAllocator().Allocate<SDNode>();
new (N) SDNode(Opcode, VTs, Ops, NumOps);
CSEMap.InsertNode(N, IP);
@@ -3427,26 +3422,26 @@
#ifndef NDEBUG
VerifyNode(N);
#endif
- return SDOperand(N, 0);
+ return SDValue(N, 0);
}
-SDOperand SelectionDAG::getNode(unsigned Opcode,
- const std::vector<MVT> &ResultTys,
- const SDOperand *Ops, unsigned NumOps) {
+SDValue SelectionDAG::getNode(unsigned Opcode,
+ const std::vector<MVT> &ResultTys,
+ const SDValue *Ops, unsigned NumOps) {
return getNode(Opcode, getNodeValueTypes(ResultTys), ResultTys.size(),
Ops, NumOps);
}
-SDOperand SelectionDAG::getNode(unsigned Opcode,
- const MVT *VTs, unsigned NumVTs,
- const SDOperand *Ops, unsigned NumOps) {
+SDValue SelectionDAG::getNode(unsigned Opcode,
+ const MVT *VTs, unsigned NumVTs,
+ const SDValue *Ops, unsigned NumOps) {
if (NumVTs == 1)
return getNode(Opcode, VTs[0], Ops, NumOps);
return getNode(Opcode, makeVTList(VTs, NumVTs), Ops, NumOps);
}
-SDOperand SelectionDAG::getNode(unsigned Opcode, SDVTList VTList,
- const SDOperand *Ops, unsigned NumOps) {
+SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList,
+ const SDValue *Ops, unsigned NumOps) {
if (VTList.NumVTs == 1)
return getNode(Opcode, VTList.VTs[0], Ops, NumOps);
@@ -3480,7 +3475,7 @@
AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps);
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
- return SDOperand(E, 0);
+ return SDValue(E, 0);
if (NumOps == 1) {
N = getAllocator().Allocate<UnarySDNode>();
new (N) UnarySDNode(Opcode, VTList, Ops[0]);
@@ -3514,42 +3509,42 @@
#ifndef NDEBUG
VerifyNode(N);
#endif
- return SDOperand(N, 0);
+ return SDValue(N, 0);
}
-SDOperand SelectionDAG::getNode(unsigned Opcode, SDVTList VTList) {
+SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList) {
return getNode(Opcode, VTList, 0, 0);
}
-SDOperand SelectionDAG::getNode(unsigned Opcode, SDVTList VTList,
- SDOperand N1) {
- SDOperand Ops[] = { N1 };
+SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList,
+ SDValue N1) {
+ SDValue Ops[] = { N1 };
return getNode(Opcode, VTList, Ops, 1);
}
-SDOperand SelectionDAG::getNode(unsigned Opcode, SDVTList VTList,
- SDOperand N1, SDOperand N2) {
- SDOperand Ops[] = { N1, N2 };
+SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList,
+ SDValue N1, SDValue N2) {
+ SDValue Ops[] = { N1, N2 };
return getNode(Opcode, VTList, Ops, 2);
}
-SDOperand SelectionDAG::getNode(unsigned Opcode, SDVTList VTList,
- SDOperand N1, SDOperand N2, SDOperand N3) {
- SDOperand Ops[] = { N1, N2, N3 };
+SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList,
+ SDValue N1, SDValue N2, SDValue N3) {
+ SDValue Ops[] = { N1, N2, N3 };
return getNode(Opcode, VTList, Ops, 3);
}
-SDOperand SelectionDAG::getNode(unsigned Opcode, SDVTList VTList,
- SDOperand N1, SDOperand N2, SDOperand N3,
- SDOperand N4) {
- SDOperand Ops[] = { N1, N2, N3, N4 };
+SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList,
+ SDValue N1, SDValue N2, SDValue N3,
+ SDValue N4) {
+ SDValue Ops[] = { N1, N2, N3, N4 };
return getNode(Opcode, VTList, Ops, 4);
}
-SDOperand SelectionDAG::getNode(unsigned Opcode, SDVTList VTList,
- SDOperand N1, SDOperand N2, SDOperand N3,
- SDOperand N4, SDOperand N5) {
- SDOperand Ops[] = { N1, N2, N3, N4, N5 };
+SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList,
+ SDValue N1, SDValue N2, SDValue N3,
+ SDValue N4, SDValue N5) {
+ SDValue Ops[] = { N1, N2, N3, N4, N5 };
return getNode(Opcode, VTList, Ops, 5);
}
@@ -3625,8 +3620,7 @@
/// already exists. If the resultant node does not exist in the DAG, the
/// input node is returned. As a degenerate case, if you specify the same
/// input operands as the node already has, the input node is returned.
-SDOperand SelectionDAG::
-UpdateNodeOperands(SDOperand InN, SDOperand Op) {
+SDValue SelectionDAG::UpdateNodeOperands(SDValue InN, SDValue Op) {
SDNode *N = InN.Val;
assert(N->getNumOperands() == 1 && "Update with wrong number of operands");
@@ -3636,7 +3630,7 @@
// See if the modified node already exists.
void *InsertPos = 0;
if (SDNode *Existing = FindModifiedNodeSlot(N, Op, InsertPos))
- return SDOperand(Existing, InN.ResNo);
+ return SDValue(Existing, InN.ResNo);
// Nope it doesn't. Remove the node from its current place in the maps.
if (InsertPos)
@@ -3653,8 +3647,8 @@
return InN;
}
-SDOperand SelectionDAG::
-UpdateNodeOperands(SDOperand InN, SDOperand Op1, SDOperand Op2) {
+SDValue SelectionDAG::
+UpdateNodeOperands(SDValue InN, SDValue Op1, SDValue Op2) {
SDNode *N = InN.Val;
assert(N->getNumOperands() == 2 && "Update with wrong number of operands");
@@ -3665,7 +3659,7 @@
// See if the modified node already exists.
void *InsertPos = 0;
if (SDNode *Existing = FindModifiedNodeSlot(N, Op1, Op2, InsertPos))
- return SDOperand(Existing, InN.ResNo);
+ return SDValue(Existing, InN.ResNo);
// Nope it doesn't. Remove the node from its current place in the maps.
if (InsertPos)
@@ -3690,28 +3684,28 @@
return InN;
}
-SDOperand SelectionDAG::
-UpdateNodeOperands(SDOperand N, SDOperand Op1, SDOperand Op2, SDOperand Op3) {
- SDOperand Ops[] = { Op1, Op2, Op3 };
+SDValue SelectionDAG::
+UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, SDValue Op3) {
+ SDValue Ops[] = { Op1, Op2, Op3 };
return UpdateNodeOperands(N, Ops, 3);
}
-SDOperand SelectionDAG::
-UpdateNodeOperands(SDOperand N, SDOperand Op1, SDOperand Op2,
- SDOperand Op3, SDOperand Op4) {
- SDOperand Ops[] = { Op1, Op2, Op3, Op4 };
+SDValue SelectionDAG::
+UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2,
+ SDValue Op3, SDValue Op4) {
+ SDValue Ops[] = { Op1, Op2, Op3, Op4 };
return UpdateNodeOperands(N, Ops, 4);
}
-SDOperand SelectionDAG::
-UpdateNodeOperands(SDOperand N, SDOperand Op1, SDOperand Op2,
- SDOperand Op3, SDOperand Op4, SDOperand Op5) {
- SDOperand Ops[] = { Op1, Op2, Op3, Op4, Op5 };
+SDValue SelectionDAG::
+UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2,
+ SDValue Op3, SDValue Op4, SDValue Op5) {
+ SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 };
return UpdateNodeOperands(N, Ops, 5);
}
-SDOperand SelectionDAG::
-UpdateNodeOperands(SDOperand InN, const SDOperand *Ops, unsigned NumOps) {
+SDValue SelectionDAG::
+UpdateNodeOperands(SDValue InN, const SDValue *Ops, unsigned NumOps) {
SDNode *N = InN.Val;
assert(N->getNumOperands() == NumOps &&
"Update with wrong number of operands");
@@ -3731,7 +3725,7 @@
// See if the modified node already exists.
void *InsertPos = 0;
if (SDNode *Existing = FindModifiedNodeSlot(N, Ops, NumOps, InsertPos))
- return SDOperand(Existing, InN.ResNo);
+ return SDValue(Existing, InN.ResNo);
// Nope it doesn't. Remove the node from its current place in the maps.
if (InsertPos)
@@ -3773,37 +3767,37 @@
}
SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- MVT VT, SDOperand Op1) {
+ MVT VT, SDValue Op1) {
SDVTList VTs = getVTList(VT);
- SDOperand Ops[] = { Op1 };
+ SDValue Ops[] = { Op1 };
return SelectNodeTo(N, MachineOpc, VTs, Ops, 1);
}
SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- MVT VT, SDOperand Op1,
- SDOperand Op2) {
+ MVT VT, SDValue Op1,
+ SDValue Op2) {
SDVTList VTs = getVTList(VT);
- SDOperand Ops[] = { Op1, Op2 };
+ SDValue Ops[] = { Op1, Op2 };
return SelectNodeTo(N, MachineOpc, VTs, Ops, 2);
}
SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- MVT VT, SDOperand Op1,
- SDOperand Op2, SDOperand Op3) {
+ MVT VT, SDValue Op1,
+ SDValue Op2, SDValue Op3) {
SDVTList VTs = getVTList(VT);
- SDOperand Ops[] = { Op1, Op2, Op3 };
+ SDValue Ops[] = { Op1, Op2, Op3 };
return SelectNodeTo(N, MachineOpc, VTs, Ops, 3);
}
SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- MVT VT, const SDOperand *Ops,
+ MVT VT, const SDValue *Ops,
unsigned NumOps) {
SDVTList VTs = getVTList(VT);
return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps);
}
SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- MVT VT1, MVT VT2, const SDOperand *Ops,
+ MVT VT1, MVT VT2, const SDValue *Ops,
unsigned NumOps) {
SDVTList VTs = getVTList(VT1, VT2);
return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps);
@@ -3812,43 +3806,43 @@
SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
MVT VT1, MVT VT2) {
SDVTList VTs = getVTList(VT1, VT2);
- return SelectNodeTo(N, MachineOpc, VTs, (SDOperand *)0, 0);
+ return SelectNodeTo(N, MachineOpc, VTs, (SDValue *)0, 0);
}
SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
MVT VT1, MVT VT2, MVT VT3,
- const SDOperand *Ops, unsigned NumOps) {
+ const SDValue *Ops, unsigned NumOps) {
SDVTList VTs = getVTList(VT1, VT2, VT3);
return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps);
}
SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
MVT VT1, MVT VT2,
- SDOperand Op1) {
+ SDValue Op1) {
SDVTList VTs = getVTList(VT1, VT2);
- SDOperand Ops[] = { Op1 };
+ SDValue Ops[] = { Op1 };
return SelectNodeTo(N, MachineOpc, VTs, Ops, 1);
}
SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
MVT VT1, MVT VT2,
- SDOperand Op1, SDOperand Op2) {
+ SDValue Op1, SDValue Op2) {
SDVTList VTs = getVTList(VT1, VT2);
- SDOperand Ops[] = { Op1, Op2 };
+ SDValue Ops[] = { Op1, Op2 };
return SelectNodeTo(N, MachineOpc, VTs, Ops, 2);
}
SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
MVT VT1, MVT VT2,
- SDOperand Op1, SDOperand Op2,
- SDOperand Op3) {
+ SDValue Op1, SDValue Op2,
+ SDValue Op3) {
SDVTList VTs = getVTList(VT1, VT2);
- SDOperand Ops[] = { Op1, Op2, Op3 };
+ SDValue Ops[] = { Op1, Op2, Op3 };
return SelectNodeTo(N, MachineOpc, VTs, Ops, 3);
}
SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- SDVTList VTs, const SDOperand *Ops,
+ SDVTList VTs, const SDValue *Ops,
unsigned NumOps) {
return MorphNodeTo(N, ~MachineOpc, VTs, Ops, NumOps);
}
@@ -3860,37 +3854,37 @@
}
SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
- MVT VT, SDOperand Op1) {
+ MVT VT, SDValue Op1) {
SDVTList VTs = getVTList(VT);
- SDOperand Ops[] = { Op1 };
+ SDValue Ops[] = { Op1 };
return MorphNodeTo(N, Opc, VTs, Ops, 1);
}
SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
- MVT VT, SDOperand Op1,
- SDOperand Op2) {
+ MVT VT, SDValue Op1,
+ SDValue Op2) {
SDVTList VTs = getVTList(VT);
- SDOperand Ops[] = { Op1, Op2 };
+ SDValue Ops[] = { Op1, Op2 };
return MorphNodeTo(N, Opc, VTs, Ops, 2);
}
SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
- MVT VT, SDOperand Op1,
- SDOperand Op2, SDOperand Op3) {
+ MVT VT, SDValue Op1,
+ SDValue Op2, SDValue Op3) {
SDVTList VTs = getVTList(VT);
- SDOperand Ops[] = { Op1, Op2, Op3 };
+ SDValue Ops[] = { Op1, Op2, Op3 };
return MorphNodeTo(N, Opc, VTs, Ops, 3);
}
SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
- MVT VT, const SDOperand *Ops,
+ MVT VT, const SDValue *Ops,
unsigned NumOps) {
SDVTList VTs = getVTList(VT);
return MorphNodeTo(N, Opc, VTs, Ops, NumOps);
}
SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
- MVT VT1, MVT VT2, const SDOperand *Ops,
+ MVT VT1, MVT VT2, const SDValue *Ops,
unsigned NumOps) {
SDVTList VTs = getVTList(VT1, VT2);
return MorphNodeTo(N, Opc, VTs, Ops, NumOps);
@@ -3899,38 +3893,38 @@
SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
MVT VT1, MVT VT2) {
SDVTList VTs = getVTList(VT1, VT2);
- return MorphNodeTo(N, Opc, VTs, (SDOperand *)0, 0);
+ return MorphNodeTo(N, Opc, VTs, (SDValue *)0, 0);
}
SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
MVT VT1, MVT VT2, MVT VT3,
- const SDOperand *Ops, unsigned NumOps) {
+ const SDValue *Ops, unsigned NumOps) {
SDVTList VTs = getVTList(VT1, VT2, VT3);
return MorphNodeTo(N, Opc, VTs, Ops, NumOps);
}
SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
MVT VT1, MVT VT2,
- SDOperand Op1) {
+ SDValue Op1) {
SDVTList VTs = getVTList(VT1, VT2);
- SDOperand Ops[] = { Op1 };
+ SDValue Ops[] = { Op1 };
return MorphNodeTo(N, Opc, VTs, Ops, 1);
}
SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
MVT VT1, MVT VT2,
- SDOperand Op1, SDOperand Op2) {
+ SDValue Op1, SDValue Op2) {
SDVTList VTs = getVTList(VT1, VT2);
- SDOperand Ops[] = { Op1, Op2 };
+ SDValue Ops[] = { Op1, Op2 };
return MorphNodeTo(N, Opc, VTs, Ops, 2);
}
SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
MVT VT1, MVT VT2,
- SDOperand Op1, SDOperand Op2,
- SDOperand Op3) {
+ SDValue Op1, SDValue Op2,
+ SDValue Op3) {
SDVTList VTs = getVTList(VT1, VT2);
- SDOperand Ops[] = { Op1, Op2, Op3 };
+ SDValue Ops[] = { Op1, Op2, Op3 };
return MorphNodeTo(N, Opc, VTs, Ops, 3);
}
@@ -3947,7 +3941,7 @@
/// the node's users.
///
SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
- SDVTList VTs, const SDOperand *Ops,
+ SDVTList VTs, const SDValue *Ops,
unsigned NumOps) {
// If an identical node already exists, use it.
void *IP = 0;
@@ -4027,72 +4021,72 @@
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT) {
return getNode(~Opcode, VT).Val;
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, SDOperand Op1) {
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, SDValue Op1) {
return getNode(~Opcode, VT, Op1).Val;
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT,
- SDOperand Op1, SDOperand Op2) {
+ SDValue Op1, SDValue Op2) {
return getNode(~Opcode, VT, Op1, Op2).Val;
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT,
- SDOperand Op1, SDOperand Op2,
- SDOperand Op3) {
+ SDValue Op1, SDValue Op2,
+ SDValue Op3) {
return getNode(~Opcode, VT, Op1, Op2, Op3).Val;
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT,
- const SDOperand *Ops, unsigned NumOps) {
+ const SDValue *Ops, unsigned NumOps) {
return getNode(~Opcode, VT, Ops, NumOps).Val;
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2) {
const MVT *VTs = getNodeValueTypes(VT1, VT2);
- SDOperand Op;
+ SDValue Op;
return getNode(~Opcode, VTs, 2, &Op, 0).Val;
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
- MVT VT2, SDOperand Op1) {
+ MVT VT2, SDValue Op1) {
const MVT *VTs = getNodeValueTypes(VT1, VT2);
return getNode(~Opcode, VTs, 2, &Op1, 1).Val;
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
- MVT VT2, SDOperand Op1,
- SDOperand Op2) {
+ MVT VT2, SDValue Op1,
+ SDValue Op2) {
const MVT *VTs = getNodeValueTypes(VT1, VT2);
- SDOperand Ops[] = { Op1, Op2 };
+ SDValue Ops[] = { Op1, Op2 };
return getNode(~Opcode, VTs, 2, Ops, 2).Val;
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
- MVT VT2, SDOperand Op1,
- SDOperand Op2, SDOperand Op3) {
+ MVT VT2, SDValue Op1,
+ SDValue Op2, SDValue Op3) {
const MVT *VTs = getNodeValueTypes(VT1, VT2);
- SDOperand Ops[] = { Op1, Op2, Op3 };
+ SDValue Ops[] = { Op1, Op2, Op3 };
return getNode(~Opcode, VTs, 2, Ops, 3).Val;
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2,
- const SDOperand *Ops, unsigned NumOps) {
+ const SDValue *Ops, unsigned NumOps) {
const MVT *VTs = getNodeValueTypes(VT1, VT2);
return getNode(~Opcode, VTs, 2, Ops, NumOps).Val;
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
- SDOperand Op1, SDOperand Op2) {
+ SDValue Op1, SDValue Op2) {
const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
- SDOperand Ops[] = { Op1, Op2 };
+ SDValue Ops[] = { Op1, Op2 };
return getNode(~Opcode, VTs, 3, Ops, 2).Val;
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
- SDOperand Op1, SDOperand Op2,
- SDOperand Op3) {
+ SDValue Op1, SDValue Op2,
+ SDValue Op3) {
const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
- SDOperand Ops[] = { Op1, Op2, Op3 };
+ SDValue Ops[] = { Op1, Op2, Op3 };
return getNode(~Opcode, VTs, 3, Ops, 3).Val;
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
- const SDOperand *Ops, unsigned NumOps) {
+ const SDValue *Ops, unsigned NumOps) {
const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
return getNode(~Opcode, VTs, 3, Ops, NumOps).Val;
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
MVT VT2, MVT VT3, MVT VT4,
- const SDOperand *Ops, unsigned NumOps) {
+ const SDValue *Ops, unsigned NumOps) {
std::vector<MVT> VTList;
VTList.push_back(VT1);
VTList.push_back(VT2);
@@ -4103,7 +4097,7 @@
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode,
const std::vector<MVT> &ResultTys,
- const SDOperand *Ops, unsigned NumOps) {
+ const SDValue *Ops, unsigned NumOps) {
const MVT *VTs = getNodeValueTypes(ResultTys);
return getNode(~Opcode, VTs, ResultTys.size(),
Ops, NumOps).Val;
@@ -4112,7 +4106,7 @@
/// getNodeIfExists - Get the specified node if it's already available, or
/// else return NULL.
SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList,
- const SDOperand *Ops, unsigned NumOps) {
+ const SDValue *Ops, unsigned NumOps) {
if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) {
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps);
@@ -4129,7 +4123,7 @@
///
/// This version assumes From has a single result value.
///
-void SelectionDAG::ReplaceAllUsesWith(SDOperand FromN, SDOperand To,
+void SelectionDAG::ReplaceAllUsesWith(SDValue FromN, SDValue To,
DAGUpdateListener *UpdateListener) {
SDNode *From = FromN.Val;
assert(From->getNumValues() == 1 && FromN.ResNo == 0 &&
@@ -4223,10 +4217,10 @@
/// This version can replace From with any result values. To must match the
/// number and types of values returned by From.
void SelectionDAG::ReplaceAllUsesWith(SDNode *From,
- const SDOperand *To,
+ const SDValue *To,
DAGUpdateListener *UpdateListener) {
if (From->getNumValues() == 1) // Handle the simple case efficiently.
- return ReplaceAllUsesWith(SDOperand(From, 0), To[0], UpdateListener);
+ return ReplaceAllUsesWith(SDValue(From, 0), To[0], UpdateListener);
while (!From->use_empty()) {
SDNode::use_iterator UI = From->use_begin();
@@ -4238,7 +4232,7 @@
for (SDNode::op_iterator I = U->op_begin(), E = U->op_end();
I != E; ++I, ++operandNum)
if (I->getVal() == From) {
- const SDOperand &ToOp = To[I->getSDOperand().ResNo];
+ const SDValue &ToOp = To[I->getSDValue().ResNo];
From->removeUser(operandNum, U);
*I = ToOp;
I->setUser(U);
@@ -4265,7 +4259,7 @@
/// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving
/// uses of other values produced by From.Val alone. The Deleted vector is
/// handled the same way as for ReplaceAllUsesWith.
-void SelectionDAG::ReplaceAllUsesOfValueWith(SDOperand From, SDOperand To,
+void SelectionDAG::ReplaceAllUsesOfValueWith(SDValue From, SDValue To,
DAGUpdateListener *UpdateListener){
// Handle the really simple, really trivial case efficiently.
if (From == To) return;
@@ -4331,8 +4325,8 @@
/// uses of other values produced by From.Val alone. The same value may
/// appear in both the From and To list. The Deleted vector is
/// handled the same way as for ReplaceAllUsesWith.
-void SelectionDAG::ReplaceAllUsesOfValuesWith(const SDOperand *From,
- const SDOperand *To,
+void SelectionDAG::ReplaceAllUsesOfValuesWith(const SDValue *From,
+ const SDValue *To,
unsigned Num,
DAGUpdateListener *UpdateListener){
// Handle the simple, trivial case efficiently.
@@ -4549,7 +4543,7 @@
// TODO: Only iterate over uses of a given value of the node
for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) {
- if (UI.getUse().getSDOperand().ResNo == Value) {
+ if (UI.getUse().getSDValue().ResNo == Value) {
if (NUses == 0)
return false;
--NUses;
@@ -4567,7 +4561,7 @@
assert(Value < getNumValues() && "Bad value!");
for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI)
- if (UI.getUse().getSDOperand().ResNo == Value)
+ if (UI.getUse().getSDValue().ResNo == Value)
return true;
return false;
@@ -4591,7 +4585,7 @@
/// isOperand - Return true if this node is an operand of N.
///
-bool SDOperand::isOperandOf(SDNode *N) const {
+bool SDValue::isOperandOf(SDNode *N) const {
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
if (*this == N->getOperand(i))
return true;
@@ -4610,7 +4604,7 @@
/// side-effecting instructions. In practice, this looks through token
/// factors and non-volatile loads. In order to remain efficient, this only
/// looks a couple of nodes in, it does not do an exhaustive search.
-bool SDOperand::reachesChainWithoutSideEffects(SDOperand Dest,
+bool SDValue::reachesChainWithoutSideEffects(SDValue Dest,
unsigned Depth) const {
if (*this == Dest) return true;
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sun Jul 27 16:46:04 2008
@@ -261,21 +261,21 @@
/// this value and returns the result as a ValueVTs value. This uses
/// Chain/Flag as the input and updates them for the output Chain/Flag.
/// If the Flag pointer is NULL, no flag is used.
- SDOperand getCopyFromRegs(SelectionDAG &DAG,
- SDOperand &Chain, SDOperand *Flag) const;
+ SDValue getCopyFromRegs(SelectionDAG &DAG,
+ SDValue &Chain, SDValue *Flag) const;
/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
/// specified value into the registers specified by this object. This uses
/// Chain/Flag as the input and updates them for the output Chain/Flag.
/// If the Flag pointer is NULL, no flag is used.
- void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
- SDOperand &Chain, SDOperand *Flag) const;
+ void getCopyToRegs(SDValue Val, SelectionDAG &DAG,
+ SDValue &Chain, SDValue *Flag) const;
/// AddInlineAsmOperands - Add this value to the specified inlineasm node
/// operand list. This adds the code marker and includes the number of
/// values added into it.
void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
- std::vector<SDOperand> &Ops) const;
+ std::vector<SDValue> &Ops) const;
};
}
@@ -489,20 +489,20 @@
class SelectionDAGLowering {
MachineBasicBlock *CurMBB;
- DenseMap<const Value*, SDOperand> NodeMap;
+ DenseMap<const Value*, SDValue> NodeMap;
/// PendingLoads - Loads are not emitted to the program immediately. We bunch
/// them up and then emit token factor nodes when possible. This allows us to
/// get simple disambiguation between loads without worrying about alias
/// analysis.
- SmallVector<SDOperand, 8> PendingLoads;
+ SmallVector<SDValue, 8> PendingLoads;
/// PendingExports - CopyToReg nodes that copy values to virtual registers
/// for export to other blocks need to be emitted before any terminator
/// instruction, but they have no other ordering requirements. We bunch them
/// up and the emit a single tokenfactor for them just before terminator
/// instructions.
- std::vector<SDOperand> PendingExports;
+ std::vector<SDValue> PendingExports;
/// Case - A struct to record the Value for a switch case, and the
/// case's target basic block.
@@ -610,19 +610,19 @@
/// a store or any other node that may need to be ordered after any
/// prior load instructions.
///
- SDOperand getRoot() {
+ SDValue getRoot() {
if (PendingLoads.empty())
return DAG.getRoot();
if (PendingLoads.size() == 1) {
- SDOperand Root = PendingLoads[0];
+ SDValue Root = PendingLoads[0];
DAG.setRoot(Root);
PendingLoads.clear();
return Root;
}
// Otherwise, we have to make a token factor node.
- SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
+ SDValue Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
&PendingLoads[0], PendingLoads.size());
PendingLoads.clear();
DAG.setRoot(Root);
@@ -633,8 +633,8 @@
/// PendingLoad items, flush all the PendingExports items. It is necessary
/// to do this before emitting a terminator instruction.
///
- SDOperand getControlRoot() {
- SDOperand Root = DAG.getRoot();
+ SDValue getControlRoot() {
+ SDValue Root = DAG.getRoot();
if (PendingExports.empty())
return Root;
@@ -679,10 +679,10 @@
void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
- SDOperand getValue(const Value *V);
+ SDValue getValue(const Value *V);
- void setValue(const Value *V, SDOperand NewN) {
- SDOperand &N = NodeMap[V];
+ void setValue(const Value *V, SDValue NewN) {
+ SDValue &N = NodeMap[V];
assert(N.Val == 0 && "Already set a value for this node!");
N = NewN;
}
@@ -696,7 +696,7 @@
unsigned Opc);
bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
void ExportFromCurrentBlock(Value *V);
- void LowerCallTo(CallSite CS, SDOperand Callee, bool IsTailCall,
+ void LowerCallTo(CallSite CS, SDValue Callee, bool IsTailCall,
MachineBasicBlock *LandingPad = NULL);
// Terminator instructions.
@@ -827,15 +827,15 @@
/// larger then ValueVT then AssertOp can be used to specify whether the extra
/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
/// (ISD::AssertSext).
-static SDOperand getCopyFromParts(SelectionDAG &DAG,
- const SDOperand *Parts,
+static SDValue getCopyFromParts(SelectionDAG &DAG,
+ const SDValue *Parts,
unsigned NumParts,
MVT PartVT,
MVT ValueVT,
ISD::NodeType AssertOp = ISD::DELETED_NODE) {
assert(NumParts > 0 && "No parts to assemble!");
TargetLowering &TLI = DAG.getTargetLoweringInfo();
- SDOperand Val = Parts[0];
+ SDValue Val = Parts[0];
if (NumParts > 1) {
// Assemble the value from multiple parts.
@@ -849,7 +849,7 @@
unsigned RoundBits = PartBits * RoundParts;
MVT RoundVT = RoundBits == ValueBits ?
ValueVT : MVT::getIntegerVT(RoundBits);
- SDOperand Lo, Hi;
+ SDValue Lo, Hi;
if (RoundParts > 2) {
MVT HalfVT = MVT::getIntegerVT(RoundBits/2);
@@ -896,7 +896,7 @@
"Part type doesn't match part!");
// Assemble the parts into intermediate operands.
- SmallVector<SDOperand, 8> Ops(NumIntermediates);
+ SmallVector<SDValue, 8> Ops(NumIntermediates);
if (NumIntermediates == NumParts) {
// If the register was not expanded, truncate or copy the value,
// as appropriate.
@@ -967,15 +967,15 @@
return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
assert(0 && "Unknown mismatch!");
- return SDOperand();
+ return SDValue();
}
/// getCopyToParts - Create a series of nodes that contain the specified value
/// split into legal parts. If the parts contain more bits than Val, then, for
/// integers, ExtendKind can be used to specify how to generate the extra bits.
static void getCopyToParts(SelectionDAG &DAG,
- SDOperand Val,
- SDOperand *Parts,
+ SDValue Val,
+ SDValue *Parts,
unsigned NumParts,
MVT PartVT,
ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
@@ -1039,7 +1039,7 @@
unsigned RoundParts = 1 << Log2_32(NumParts);
unsigned RoundBits = RoundParts * PartBits;
unsigned OddParts = NumParts - RoundParts;
- SDOperand OddVal = DAG.getNode(ISD::SRL, ValueVT, Val,
+ SDValue OddVal = DAG.getNode(ISD::SRL, ValueVT, Val,
DAG.getConstant(RoundBits,
TLI.getShiftAmountTy()));
getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT);
@@ -1060,8 +1060,8 @@
for (unsigned i = 0; i < NumParts; i += StepSize) {
unsigned ThisBits = StepSize * PartBits / 2;
MVT ThisVT = MVT::getIntegerVT (ThisBits);
- SDOperand &Part0 = Parts[i];
- SDOperand &Part1 = Parts[i+StepSize/2];
+ SDValue &Part0 = Parts[i];
+ SDValue &Part1 = Parts[i+StepSize/2];
Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
DAG.getConstant(1, PtrVT));
@@ -1113,7 +1113,7 @@
assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
// Split the vector into intermediate operands.
- SmallVector<SDOperand, 8> Ops(NumIntermediates);
+ SmallVector<SDValue, 8> Ops(NumIntermediates);
for (unsigned i = 0; i != NumIntermediates; ++i)
if (IntermediateVT.isVector())
Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR,
@@ -1143,8 +1143,8 @@
}
-SDOperand SelectionDAGLowering::getValue(const Value *V) {
- SDOperand &N = NodeMap[V];
+SDValue SelectionDAGLowering::getValue(const Value *V) {
+ SDValue &N = NodeMap[V];
if (N.Val) return N;
if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
@@ -1168,18 +1168,18 @@
if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
visit(CE->getOpcode(), *CE);
- SDOperand N1 = NodeMap[V];
+ SDValue N1 = NodeMap[V];
assert(N1.Val && "visit didn't populate the ValueMap!");
return N1;
}
if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
- SmallVector<SDOperand, 4> Constants;
+ SmallVector<SDValue, 4> Constants;
for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
OI != OE; ++OI) {
SDNode *Val = getValue(*OI).Val;
for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
- Constants.push_back(SDOperand(Val, i));
+ Constants.push_back(SDValue(Val, i));
}
return DAG.getMergeValues(&Constants[0], Constants.size());
}
@@ -1189,9 +1189,9 @@
"Unknown array constant!");
unsigned NumElts = ATy->getNumElements();
if (NumElts == 0)
- return SDOperand(); // empty array
+ return SDValue(); // empty array
MVT EltVT = TLI.getValueType(ATy->getElementType());
- SmallVector<SDOperand, 4> Constants(NumElts);
+ SmallVector<SDValue, 4> Constants(NumElts);
for (unsigned i = 0, e = NumElts; i != e; ++i) {
if (isa<UndefValue>(C))
Constants[i] = DAG.getNode(ISD::UNDEF, EltVT);
@@ -1208,8 +1208,8 @@
"Unknown struct constant!");
unsigned NumElts = STy->getNumElements();
if (NumElts == 0)
- return SDOperand(); // empty struct
- SmallVector<SDOperand, 4> Constants(NumElts);
+ return SDValue(); // empty struct
+ SmallVector<SDValue, 4> Constants(NumElts);
for (unsigned i = 0, e = NumElts; i != e; ++i) {
MVT EltVT = TLI.getValueType(STy->getElementType(i));
if (isa<UndefValue>(C))
@@ -1227,7 +1227,7 @@
// Now that we know the number and type of the elements, get that number of
// elements into the Ops array based on what kind of constant it is.
- SmallVector<SDOperand, 16> Ops;
+ SmallVector<SDValue, 16> Ops;
if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
for (unsigned i = 0; i != NumElements; ++i)
Ops.push_back(getValue(CP->getOperand(i)));
@@ -1236,7 +1236,7 @@
"Unknown vector constant!");
MVT EltVT = TLI.getValueType(VecTy->getElementType());
- SDOperand Op;
+ SDValue Op;
if (isa<UndefValue>(C))
Op = DAG.getNode(ISD::UNDEF, EltVT);
else if (EltVT.isFloatingPoint())
@@ -1263,7 +1263,7 @@
assert(InReg && "Value not in map!");
RegsForValue RFV(TLI, InReg, V->getType());
- SDOperand Chain = DAG.getEntryNode();
+ SDValue Chain = DAG.getEntryNode();
return RFV.getCopyFromRegs(DAG, Chain, NULL);
}
@@ -1274,10 +1274,10 @@
return;
}
- SmallVector<SDOperand, 8> NewValues;
+ SmallVector<SDValue, 8> NewValues;
NewValues.push_back(getControlRoot());
for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
- SDOperand RetOp = getValue(I.getOperand(i));
+ SDValue RetOp = getValue(I.getOperand(i));
SmallVector<MVT, 4> ValueVTs;
ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
@@ -1294,7 +1294,7 @@
unsigned NumParts = TLI.getNumRegisters(VT);
MVT PartVT = TLI.getRegisterType(VT);
- SmallVector<SDOperand, 4> Parts(NumParts);
+ SmallVector<SDValue, 4> Parts(NumParts);
ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
const Function *F = I.getParent()->getParent();
@@ -1303,7 +1303,7 @@
else if (F->paramHasAttr(0, ParamAttr::ZExt))
ExtendKind = ISD::ZERO_EXTEND;
- getCopyToParts(DAG, SDOperand(RetOp.Val, RetOp.ResNo + j),
+ getCopyToParts(DAG, SDValue(RetOp.Val, RetOp.ResNo + j),
&Parts[0], NumParts, PartVT, ExtendKind);
for (unsigned i = 0; i < NumParts; ++i) {
@@ -1590,8 +1590,8 @@
/// visitSwitchCase - Emits the necessary code to represent a single node in
/// the binary search tree resulting from lowering a switch instruction.
void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
- SDOperand Cond;
- SDOperand CondLHS = getValue(CB.CmpLHS);
+ SDValue Cond;
+ SDValue CondLHS = getValue(CB.CmpLHS);
// Build the setcc now.
if (CB.CmpMHS == NULL) {
@@ -1600,7 +1600,7 @@
if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
Cond = CondLHS;
else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
- SDOperand True = DAG.getConstant(1, CondLHS.getValueType());
+ SDValue True = DAG.getConstant(1, CondLHS.getValueType());
Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
} else
Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
@@ -1610,13 +1610,13 @@
uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue();
uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue();
- SDOperand CmpOp = getValue(CB.CmpMHS);
+ SDValue CmpOp = getValue(CB.CmpMHS);
MVT VT = CmpOp.getValueType();
if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
} else {
- SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
+ SDValue SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
Cond = DAG.getSetCC(MVT::i1, SUB,
DAG.getConstant(High-Low, VT), ISD::SETULE);
}
@@ -1637,10 +1637,10 @@
// fall through to the lhs instead of the rhs block.
if (CB.TrueBB == NextBlock) {
std::swap(CB.TrueBB, CB.FalseBB);
- SDOperand True = DAG.getConstant(1, Cond.getValueType());
+ SDValue True = DAG.getConstant(1, Cond.getValueType());
Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
}
- SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(), Cond,
+ SDValue BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(), Cond,
DAG.getBasicBlock(CB.TrueBB));
if (CB.FalseBB == NextBlock)
DAG.setRoot(BrCond);
@@ -1654,8 +1654,8 @@
// Emit the code for the jump table
assert(JT.Reg != -1U && "Should lower JT Header first!");
MVT PTy = TLI.getPointerTy();
- SDOperand Index = DAG.getCopyFromReg(getControlRoot(), JT.Reg, PTy);
- SDOperand Table = DAG.getJumpTable(JT.JTI, PTy);
+ SDValue Index = DAG.getCopyFromReg(getControlRoot(), JT.Reg, PTy);
+ SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
Table, Index));
return;
@@ -1668,9 +1668,9 @@
// Subtract the lowest switch case value from the value being switched on
// and conditional branch to default mbb if the result is greater than the
// difference between smallest and largest cases.
- SDOperand SwitchOp = getValue(JTH.SValue);
+ SDValue SwitchOp = getValue(JTH.SValue);
MVT VT = SwitchOp.getValueType();
- SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
+ SDValue SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
DAG.getConstant(JTH.First, VT));
// The SDNode we just created, which holds the value being switched on
@@ -1684,13 +1684,13 @@
SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
- SDOperand CopyTo = DAG.getCopyToReg(getControlRoot(), JumpTableReg, SwitchOp);
+ SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), JumpTableReg, SwitchOp);
JT.Reg = JumpTableReg;
// Emit the range check for the jump table, and branch to the default
// block for the switch statement if the value being switched on exceeds
// the largest case in the switch.
- SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
+ SDValue CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
DAG.getConstant(JTH.Last-JTH.First,VT),
ISD::SETUGT);
@@ -1701,7 +1701,7 @@
if (++BBI != CurMBB->getParent()->end())
NextBlock = BBI;
- SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
+ SDValue BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
DAG.getBasicBlock(JT.Default));
if (JT.MBB == NextBlock)
@@ -1717,29 +1717,29 @@
/// suitable for "bit tests"
void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) {
// Subtract the minimum value
- SDOperand SwitchOp = getValue(B.SValue);
+ SDValue SwitchOp = getValue(B.SValue);
MVT VT = SwitchOp.getValueType();
- SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
+ SDValue SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
DAG.getConstant(B.First, VT));
// Check range
- SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
+ SDValue RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
DAG.getConstant(B.Range, VT),
ISD::SETUGT);
- SDOperand ShiftOp;
+ SDValue ShiftOp;
if (VT.bitsGT(TLI.getShiftAmountTy()))
ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
else
ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
// Make desired shift
- SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
+ SDValue SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
DAG.getConstant(1, TLI.getPointerTy()),
ShiftOp);
unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy());
- SDOperand CopyTo = DAG.getCopyToReg(getControlRoot(), SwitchReg, SwitchVal);
+ SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), SwitchReg, SwitchVal);
B.Reg = SwitchReg;
// Set NextBlock to be the MBB immediately after the current one, if any.
@@ -1754,7 +1754,7 @@
CurMBB->addSuccessor(B.Default);
CurMBB->addSuccessor(MBB);
- SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
+ SDValue BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
DAG.getBasicBlock(B.Default));
if (MBB == NextBlock)
@@ -1771,19 +1771,19 @@
unsigned Reg,
SelectionDAGISel::BitTestCase &B) {
// Emit bit tests and jumps
- SDOperand SwitchVal = DAG.getCopyFromReg(getControlRoot(), Reg,
+ SDValue SwitchVal = DAG.getCopyFromReg(getControlRoot(), Reg,
TLI.getPointerTy());
- SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), SwitchVal,
+ SDValue AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), SwitchVal,
DAG.getConstant(B.Mask, TLI.getPointerTy()));
- SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp), AndOp,
+ SDValue AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp), AndOp,
DAG.getConstant(0, TLI.getPointerTy()),
ISD::SETNE);
CurMBB->addSuccessor(B.TargetBB);
CurMBB->addSuccessor(NextMBB);
- SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(),
+ SDValue BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(),
AndCmp, DAG.getBasicBlock(B.TargetBB));
// Set NextBlock to be the MBB immediately after the current one, if any.
@@ -2378,7 +2378,7 @@
std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
if (CV == CNZ) {
- SDOperand Op2 = getValue(I.getOperand(1));
+ SDValue Op2 = getValue(I.getOperand(1));
setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
return;
}
@@ -2388,7 +2388,7 @@
if (Ty->isFloatingPoint()) {
if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
- SDOperand Op2 = getValue(I.getOperand(1));
+ SDValue Op2 = getValue(I.getOperand(1));
setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
return;
}
@@ -2398,15 +2398,15 @@
}
void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
- SDOperand Op1 = getValue(I.getOperand(0));
- SDOperand Op2 = getValue(I.getOperand(1));
+ SDValue Op1 = getValue(I.getOperand(0));
+ SDValue Op2 = getValue(I.getOperand(1));
setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
}
void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
- SDOperand Op1 = getValue(I.getOperand(0));
- SDOperand Op2 = getValue(I.getOperand(1));
+ SDValue Op1 = getValue(I.getOperand(0));
+ SDValue Op2 = getValue(I.getOperand(1));
if (TLI.getShiftAmountTy().bitsLT(Op2.getValueType()))
Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
@@ -2422,8 +2422,8 @@
predicate = IC->getPredicate();
else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
predicate = ICmpInst::Predicate(IC->getPredicate());
- SDOperand Op1 = getValue(I.getOperand(0));
- SDOperand Op2 = getValue(I.getOperand(1));
+ SDValue Op1 = getValue(I.getOperand(0));
+ SDValue Op2 = getValue(I.getOperand(1));
ISD::CondCode Opcode;
switch (predicate) {
case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
@@ -2450,8 +2450,8 @@
predicate = FC->getPredicate();
else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
predicate = FCmpInst::Predicate(FC->getPredicate());
- SDOperand Op1 = getValue(I.getOperand(0));
- SDOperand Op2 = getValue(I.getOperand(1));
+ SDValue Op1 = getValue(I.getOperand(0));
+ SDValue Op2 = getValue(I.getOperand(1));
ISD::CondCode Condition, FOC, FPC;
switch (predicate) {
case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
@@ -2488,8 +2488,8 @@
predicate = IC->getPredicate();
else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
predicate = ICmpInst::Predicate(IC->getPredicate());
- SDOperand Op1 = getValue(I.getOperand(0));
- SDOperand Op2 = getValue(I.getOperand(1));
+ SDValue Op1 = getValue(I.getOperand(0));
+ SDValue Op2 = getValue(I.getOperand(1));
ISD::CondCode Opcode;
switch (predicate) {
case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
@@ -2516,8 +2516,8 @@
predicate = FC->getPredicate();
else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
predicate = FCmpInst::Predicate(FC->getPredicate());
- SDOperand Op1 = getValue(I.getOperand(0));
- SDOperand Op2 = getValue(I.getOperand(1));
+ SDValue Op1 = getValue(I.getOperand(0));
+ SDValue Op2 = getValue(I.getOperand(1));
ISD::CondCode Condition, FOC, FPC;
switch (predicate) {
case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
@@ -2552,9 +2552,9 @@
}
void SelectionDAGLowering::visitSelect(User &I) {
- SDOperand Cond = getValue(I.getOperand(0));
- SDOperand TrueVal = getValue(I.getOperand(1));
- SDOperand FalseVal = getValue(I.getOperand(2));
+ SDValue Cond = getValue(I.getOperand(0));
+ SDValue TrueVal = getValue(I.getOperand(1));
+ SDValue FalseVal = getValue(I.getOperand(2));
setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
TrueVal, FalseVal));
}
@@ -2562,7 +2562,7 @@
void SelectionDAGLowering::visitTrunc(User &I) {
// TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
- SDOperand N = getValue(I.getOperand(0));
+ SDValue N = getValue(I.getOperand(0));
MVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
}
@@ -2570,7 +2570,7 @@
void SelectionDAGLowering::visitZExt(User &I) {
// ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
// ZExt also can't be a cast to bool for same reason. So, nothing much to do
- SDOperand N = getValue(I.getOperand(0));
+ SDValue N = getValue(I.getOperand(0));
MVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
}
@@ -2578,49 +2578,49 @@
void SelectionDAGLowering::visitSExt(User &I) {
// SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
// SExt also can't be a cast to bool for same reason. So, nothing much to do
- SDOperand N = getValue(I.getOperand(0));
+ SDValue N = getValue(I.getOperand(0));
MVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
}
void SelectionDAGLowering::visitFPTrunc(User &I) {
// FPTrunc is never a no-op cast, no need to check
- SDOperand N = getValue(I.getOperand(0));
+ SDValue N = getValue(I.getOperand(0));
MVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0)));
}
void SelectionDAGLowering::visitFPExt(User &I){
// FPTrunc is never a no-op cast, no need to check
- SDOperand N = getValue(I.getOperand(0));
+ SDValue N = getValue(I.getOperand(0));
MVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
}
void SelectionDAGLowering::visitFPToUI(User &I) {
// FPToUI is never a no-op cast, no need to check
- SDOperand N = getValue(I.getOperand(0));
+ SDValue N = getValue(I.getOperand(0));
MVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
}
void SelectionDAGLowering::visitFPToSI(User &I) {
// FPToSI is never a no-op cast, no need to check
- SDOperand N = getValue(I.getOperand(0));
+ SDValue N = getValue(I.getOperand(0));
MVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
}
void SelectionDAGLowering::visitUIToFP(User &I) {
// UIToFP is never a no-op cast, no need to check
- SDOperand N = getValue(I.getOperand(0));
+ SDValue N = getValue(I.getOperand(0));
MVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
}
void SelectionDAGLowering::visitSIToFP(User &I){
// UIToFP is never a no-op cast, no need to check
- SDOperand N = getValue(I.getOperand(0));
+ SDValue N = getValue(I.getOperand(0));
MVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
}
@@ -2628,10 +2628,10 @@
void SelectionDAGLowering::visitPtrToInt(User &I) {
// What to do depends on the size of the integer and the size of the pointer.
// We can either truncate, zero extend, or no-op, accordingly.
- SDOperand N = getValue(I.getOperand(0));
+ SDValue N = getValue(I.getOperand(0));
MVT SrcVT = N.getValueType();
MVT DestVT = TLI.getValueType(I.getType());
- SDOperand Result;
+ SDValue Result;
if (DestVT.bitsLT(SrcVT))
Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
else
@@ -2643,7 +2643,7 @@
void SelectionDAGLowering::visitIntToPtr(User &I) {
// What to do depends on the size of the integer and the size of the pointer.
// We can either truncate, zero extend, or no-op, accordingly.
- SDOperand N = getValue(I.getOperand(0));
+ SDValue N = getValue(I.getOperand(0));
MVT SrcVT = N.getValueType();
MVT DestVT = TLI.getValueType(I.getType());
if (DestVT.bitsLT(SrcVT))
@@ -2654,7 +2654,7 @@
}
void SelectionDAGLowering::visitBitCast(User &I) {
- SDOperand N = getValue(I.getOperand(0));
+ SDValue N = getValue(I.getOperand(0));
MVT DestVT = TLI.getValueType(I.getType());
// BitCast assures us that source and destination are the same size so this
@@ -2666,9 +2666,9 @@
}
void SelectionDAGLowering::visitInsertElement(User &I) {
- SDOperand InVec = getValue(I.getOperand(0));
- SDOperand InVal = getValue(I.getOperand(1));
- SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
+ SDValue InVec = getValue(I.getOperand(0));
+ SDValue InVal = getValue(I.getOperand(1));
+ SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
getValue(I.getOperand(2)));
setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT,
@@ -2677,17 +2677,17 @@
}
void SelectionDAGLowering::visitExtractElement(User &I) {
- SDOperand InVec = getValue(I.getOperand(0));
- SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
+ SDValue InVec = getValue(I.getOperand(0));
+ SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
getValue(I.getOperand(1)));
setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
TLI.getValueType(I.getType()), InVec, InIdx));
}
void SelectionDAGLowering::visitShuffleVector(User &I) {
- SDOperand V1 = getValue(I.getOperand(0));
- SDOperand V2 = getValue(I.getOperand(1));
- SDOperand Mask = getValue(I.getOperand(2));
+ SDValue V1 = getValue(I.getOperand(0));
+ SDValue V2 = getValue(I.getOperand(1));
+ SDValue Mask = getValue(I.getOperand(2));
setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE,
TLI.getValueType(I.getType()),
@@ -2712,23 +2712,23 @@
unsigned NumAggValues = AggValueVTs.size();
unsigned NumValValues = ValValueVTs.size();
- SmallVector<SDOperand, 4> Values(NumAggValues);
+ SmallVector<SDValue, 4> Values(NumAggValues);
- SDOperand Agg = getValue(Op0);
- SDOperand Val = getValue(Op1);
+ SDValue Agg = getValue(Op0);
+ SDValue Val = getValue(Op1);
unsigned i = 0;
// Copy the beginning value(s) from the original aggregate.
for (; i != LinearIndex; ++i)
Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
- SDOperand(Agg.Val, Agg.ResNo + i);
+ SDValue(Agg.Val, Agg.ResNo + i);
// Copy values from the inserted value(s).
for (; i != LinearIndex + NumValValues; ++i)
Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
- SDOperand(Val.Val, Val.ResNo + i - LinearIndex);
+ SDValue(Val.Val, Val.ResNo + i - LinearIndex);
// Copy remaining value(s) from the original aggregate.
for (; i != NumAggValues; ++i)
Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
- SDOperand(Agg.Val, Agg.ResNo + i);
+ SDValue(Agg.Val, Agg.ResNo + i);
setValue(&I, DAG.getMergeValues(DAG.getVTList(&AggValueVTs[0], NumAggValues),
&Values[0], NumAggValues));
@@ -2747,14 +2747,14 @@
ComputeValueVTs(TLI, ValTy, ValValueVTs);
unsigned NumValValues = ValValueVTs.size();
- SmallVector<SDOperand, 4> Values(NumValValues);
+ SmallVector<SDValue, 4> Values(NumValValues);
- SDOperand Agg = getValue(Op0);
+ SDValue Agg = getValue(Op0);
// Copy out the selected value(s).
for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
Values[i - LinearIndex] =
OutOfUndef ? DAG.getNode(ISD::UNDEF, Agg.Val->getValueType(Agg.ResNo + i)) :
- SDOperand(Agg.Val, Agg.ResNo + i);
+ SDValue(Agg.Val, Agg.ResNo + i);
setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValValueVTs[0], NumValValues),
&Values[0], NumValValues));
@@ -2762,7 +2762,7 @@
void SelectionDAGLowering::visitGetElementPtr(User &I) {
- SDOperand N = getValue(I.getOperand(0));
+ SDValue N = getValue(I.getOperand(0));
const Type *Ty = I.getOperand(0)->getType();
for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
@@ -2792,7 +2792,7 @@
// N = N + Idx * ElementSize;
uint64_t ElementSize = TD->getABITypeSize(Ty);
- SDOperand IdxN = getValue(Idx);
+ SDValue IdxN = getValue(Idx);
// If the index is smaller or larger than intptr_t, truncate or extend
// it.
@@ -2811,7 +2811,7 @@
continue;
}
- SDOperand Scale = DAG.getIntPtrConstant(ElementSize);
+ SDValue Scale = DAG.getIntPtrConstant(ElementSize);
IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
}
@@ -2831,7 +2831,7 @@
std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
I.getAlignment());
- SDOperand AllocSize = getValue(I.getArraySize());
+ SDValue AllocSize = getValue(I.getArraySize());
MVT IntPtr = TLI.getPointerTy();
if (IntPtr.bitsLT(AllocSize.getValueType()))
AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
@@ -2857,10 +2857,10 @@
AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
- SDOperand Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
+ SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
const MVT *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
MVT::Other);
- SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
+ SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
setValue(&I, DSA);
DAG.setRoot(DSA.getValue(1));
@@ -2871,7 +2871,7 @@
void SelectionDAGLowering::visitLoad(LoadInst &I) {
const Value *SV = I.getOperand(0);
- SDOperand Ptr = getValue(SV);
+ SDValue Ptr = getValue(SV);
const Type *Ty = I.getType();
bool isVolatile = I.isVolatile();
@@ -2884,7 +2884,7 @@
if (NumValues == 0)
return;
- SDOperand Root;
+ SDValue Root;
bool ConstantMemory = false;
if (I.isVolatile())
// Serialize volatile loads with other side effects.
@@ -2898,11 +2898,11 @@
Root = DAG.getRoot();
}
- SmallVector<SDOperand, 4> Values(NumValues);
- SmallVector<SDOperand, 4> Chains(NumValues);
+ SmallVector<SDValue, 4> Values(NumValues);
+ SmallVector<SDValue, 4> Chains(NumValues);
MVT PtrVT = Ptr.getValueType();
for (unsigned i = 0; i != NumValues; ++i) {
- SDOperand L = DAG.getLoad(ValueVTs[i], Root,
+ SDValue L = DAG.getLoad(ValueVTs[i], Root,
DAG.getNode(ISD::ADD, PtrVT, Ptr,
DAG.getConstant(Offsets[i], PtrVT)),
SV, Offsets[i],
@@ -2912,7 +2912,7 @@
}
if (!ConstantMemory) {
- SDOperand Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
+ SDValue Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
&Chains[0], NumValues);
if (isVolatile)
DAG.setRoot(Chain);
@@ -2927,9 +2927,9 @@
void SelectionDAGLowering::visitStore(StoreInst &I) {
Value *SrcV = I.getOperand(0);
- SDOperand Src = getValue(SrcV);
+ SDValue Src = getValue(SrcV);
Value *PtrV = I.getOperand(1);
- SDOperand Ptr = getValue(PtrV);
+ SDValue Ptr = getValue(PtrV);
SmallVector<MVT, 4> ValueVTs;
SmallVector<uint64_t, 4> Offsets;
@@ -2938,13 +2938,13 @@
if (NumValues == 0)
return;
- SDOperand Root = getRoot();
- SmallVector<SDOperand, 4> Chains(NumValues);
+ SDValue Root = getRoot();
+ SmallVector<SDValue, 4> Chains(NumValues);
MVT PtrVT = Ptr.getValueType();
bool isVolatile = I.isVolatile();
unsigned Alignment = I.getAlignment();
for (unsigned i = 0; i != NumValues; ++i)
- Chains[i] = DAG.getStore(Root, SDOperand(Src.Val, Src.ResNo + i),
+ Chains[i] = DAG.getStore(Root, SDValue(Src.Val, Src.ResNo + i),
DAG.getNode(ISD::ADD, PtrVT, Ptr,
DAG.getConstant(Offsets[i], PtrVT)),
PtrV, Offsets[i],
@@ -2961,7 +2961,7 @@
bool OnlyLoad = HasChain && I.onlyReadsMemory();
// Build the operand list.
- SmallVector<SDOperand, 8> Ops;
+ SmallVector<SDValue, 8> Ops;
if (HasChain) { // If this intrinsic has side-effects, chainify it.
if (OnlyLoad) {
// We don't need to serialize loads against other loads.
@@ -2976,7 +2976,7 @@
// Add all operands of the call to the operand list.
for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
- SDOperand Op = getValue(I.getOperand(i));
+ SDValue Op = getValue(I.getOperand(i));
assert(TLI.isTypeLegal(Op.getValueType()) &&
"Intrinsic uses a non-legal type?");
Ops.push_back(Op);
@@ -3002,7 +3002,7 @@
const MVT *VTList = DAG.getNodeValueTypes(VTs);
// Create the node.
- SDOperand Result;
+ SDValue Result;
if (!HasChain)
Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
&Ops[0], Ops.size());
@@ -3014,7 +3014,7 @@
&Ops[0], Ops.size());
if (HasChain) {
- SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
+ SDValue Chain = Result.getValue(Result.Val->getNumValues()-1);
if (OnlyLoad)
PendingLoads.push_back(Chain);
else
@@ -3098,8 +3098,8 @@
// Op is the associated NodeType for I
const char *
SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
- SDOperand Root = getRoot();
- SDOperand L = DAG.getAtomic(Op, Root,
+ SDValue Root = getRoot();
+ SDValue L = DAG.getAtomic(Op, Root,
getValue(I.getOperand(1)),
getValue(I.getOperand(2)),
I.getOperand(1));
@@ -3137,9 +3137,9 @@
break;
case Intrinsic::memcpy_i32:
case Intrinsic::memcpy_i64: {
- SDOperand Op1 = getValue(I.getOperand(1));
- SDOperand Op2 = getValue(I.getOperand(2));
- SDOperand Op3 = getValue(I.getOperand(3));
+ SDValue Op1 = getValue(I.getOperand(1));
+ SDValue Op2 = getValue(I.getOperand(2));
+ SDValue Op3 = getValue(I.getOperand(3));
unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
I.getOperand(1), 0, I.getOperand(2), 0));
@@ -3147,9 +3147,9 @@
}
case Intrinsic::memset_i32:
case Intrinsic::memset_i64: {
- SDOperand Op1 = getValue(I.getOperand(1));
- SDOperand Op2 = getValue(I.getOperand(2));
- SDOperand Op3 = getValue(I.getOperand(3));
+ SDValue Op1 = getValue(I.getOperand(1));
+ SDValue Op2 = getValue(I.getOperand(2));
+ SDValue Op3 = getValue(I.getOperand(3));
unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
DAG.setRoot(DAG.getMemset(getRoot(), Op1, Op2, Op3, Align,
I.getOperand(1), 0));
@@ -3157,9 +3157,9 @@
}
case Intrinsic::memmove_i32:
case Intrinsic::memmove_i64: {
- SDOperand Op1 = getValue(I.getOperand(1));
- SDOperand Op2 = getValue(I.getOperand(2));
- SDOperand Op3 = getValue(I.getOperand(3));
+ SDValue Op1 = getValue(I.getOperand(1));
+ SDValue Op2 = getValue(I.getOperand(2));
+ SDValue Op3 = getValue(I.getOperand(3));
unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
// If the source and destination are known to not be aliases, we can
@@ -3250,9 +3250,9 @@
}
// Insert the EXCEPTIONADDR instruction.
SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
- SDOperand Ops[1];
+ SDValue Ops[1];
Ops[0] = DAG.getRoot();
- SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
+ SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
setValue(&I, Op);
DAG.setRoot(Op.getValue(1));
return 0;
@@ -3278,10 +3278,10 @@
// Insert the EHSELECTION instruction.
SDVTList VTs = DAG.getVTList(VT, MVT::Other);
- SDOperand Ops[2];
+ SDValue Ops[2];
Ops[0] = getValue(I.getOperand(1));
Ops[1] = getRoot();
- SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
+ SDValue Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
setValue(&I, Op);
DAG.setRoot(Op.getValue(1));
} else {
@@ -3338,7 +3338,7 @@
case Intrinsic::eh_dwarf_cfa: {
MVT VT = getValue(I.getOperand(1)).getValueType();
- SDOperand CfaArg;
+ SDValue CfaArg;
if (VT.bitsGT(TLI.getPointerTy()))
CfaArg = DAG.getNode(ISD::TRUNCATE,
TLI.getPointerTy(), getValue(I.getOperand(1)));
@@ -3346,7 +3346,7 @@
CfaArg = DAG.getNode(ISD::SIGN_EXTEND,
TLI.getPointerTy(), getValue(I.getOperand(1)));
- SDOperand Offset = DAG.getNode(ISD::ADD,
+ SDValue Offset = DAG.getNode(ISD::ADD,
TLI.getPointerTy(),
DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET,
TLI.getPointerTy()),
@@ -3389,13 +3389,13 @@
getValue(I.getOperand(2))));
return 0;
case Intrinsic::pcmarker: {
- SDOperand Tmp = getValue(I.getOperand(1));
+ SDValue Tmp = getValue(I.getOperand(1));
DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
return 0;
}
case Intrinsic::readcyclecounter: {
- SDOperand Op = getRoot();
- SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
+ SDValue Op = getRoot();
+ SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
&Op, 1);
setValue(&I, Tmp);
@@ -3418,36 +3418,36 @@
getValue(I.getOperand(1))));
return 0;
case Intrinsic::cttz: {
- SDOperand Arg = getValue(I.getOperand(1));
+ SDValue Arg = getValue(I.getOperand(1));
MVT Ty = Arg.getValueType();
- SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg);
+ SDValue result = DAG.getNode(ISD::CTTZ, Ty, Arg);
setValue(&I, result);
return 0;
}
case Intrinsic::ctlz: {
- SDOperand Arg = getValue(I.getOperand(1));
+ SDValue Arg = getValue(I.getOperand(1));
MVT Ty = Arg.getValueType();
- SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg);
+ SDValue result = DAG.getNode(ISD::CTLZ, Ty, Arg);
setValue(&I, result);
return 0;
}
case Intrinsic::ctpop: {
- SDOperand Arg = getValue(I.getOperand(1));
+ SDValue Arg = getValue(I.getOperand(1));
MVT Ty = Arg.getValueType();
- SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg);
+ SDValue result = DAG.getNode(ISD::CTPOP, Ty, Arg);
setValue(&I, result);
return 0;
}
case Intrinsic::stacksave: {
- SDOperand Op = getRoot();
- SDOperand Tmp = DAG.getNode(ISD::STACKSAVE,
+ SDValue Op = getRoot();
+ SDValue Tmp = DAG.getNode(ISD::STACKSAVE,
DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
setValue(&I, Tmp);
DAG.setRoot(Tmp.getValue(1));
return 0;
}
case Intrinsic::stackrestore: {
- SDOperand Tmp = getValue(I.getOperand(1));
+ SDValue Tmp = getValue(I.getOperand(1));
DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
return 0;
}
@@ -3458,7 +3458,7 @@
case Intrinsic::init_trampoline: {
const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
- SDOperand Ops[6];
+ SDValue Ops[6];
Ops[0] = getRoot();
Ops[1] = getValue(I.getOperand(1));
Ops[2] = getValue(I.getOperand(2));
@@ -3466,7 +3466,7 @@
Ops[4] = DAG.getSrcValue(I.getOperand(1));
Ops[5] = DAG.getSrcValue(F);
- SDOperand Tmp = DAG.getNode(ISD::TRAMPOLINE,
+ SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE,
DAG.getNodeValueTypes(TLI.getPointerTy(),
MVT::Other), 2,
Ops, 6);
@@ -3501,7 +3501,7 @@
return 0;
}
case Intrinsic::prefetch: {
- SDOperand Ops[4];
+ SDValue Ops[4];
Ops[0] = getRoot();
Ops[1] = getValue(I.getOperand(1));
Ops[2] = getValue(I.getOperand(2));
@@ -3511,7 +3511,7 @@
}
case Intrinsic::memory_barrier: {
- SDOperand Ops[6];
+ SDValue Ops[6];
Ops[0] = getRoot();
for (int x = 1; x < 6; ++x)
Ops[x] = getValue(I.getOperand(x));
@@ -3520,8 +3520,8 @@
return 0;
}
case Intrinsic::atomic_cmp_swap: {
- SDOperand Root = getRoot();
- SDOperand L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, Root,
+ SDValue Root = getRoot();
+ SDValue L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, Root,
getValue(I.getOperand(1)),
getValue(I.getOperand(2)),
getValue(I.getOperand(3)),
@@ -3556,7 +3556,7 @@
}
-void SelectionDAGLowering::LowerCallTo(CallSite CS, SDOperand Callee,
+void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
bool IsTailCall,
MachineBasicBlock *LandingPad) {
const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
@@ -3569,7 +3569,7 @@
Args.reserve(CS.arg_size());
for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
i != e; ++i) {
- SDOperand ArgNode = getValue(*i);
+ SDValue ArgNode = getValue(*i);
Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
unsigned attrInd = i - CS.arg_begin() + 1;
@@ -3593,7 +3593,7 @@
DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getControlRoot(), BeginLabel));
}
- std::pair<SDOperand,SDOperand> Result =
+ std::pair<SDValue,SDValue> Result =
TLI.LowerCallTo(getRoot(), CS.getType(),
CS.paramHasAttr(0, ParamAttr::SExt),
CS.paramHasAttr(0, ParamAttr::ZExt),
@@ -3638,8 +3638,8 @@
I.getOperand(1)->getType()->isFloatingPoint() &&
I.getType() == I.getOperand(1)->getType() &&
I.getType() == I.getOperand(2)->getType()) {
- SDOperand LHS = getValue(I.getOperand(1));
- SDOperand RHS = getValue(I.getOperand(2));
+ SDValue LHS = getValue(I.getOperand(1));
+ SDValue RHS = getValue(I.getOperand(2));
setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
LHS, RHS));
return;
@@ -3651,7 +3651,7 @@
if (I.getNumOperands() == 2 && // Basic sanity checks.
I.getOperand(1)->getType()->isFloatingPoint() &&
I.getType() == I.getOperand(1)->getType()) {
- SDOperand Tmp = getValue(I.getOperand(1));
+ SDValue Tmp = getValue(I.getOperand(1));
setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
return;
}
@@ -3662,7 +3662,7 @@
if (I.getNumOperands() == 2 && // Basic sanity checks.
I.getOperand(1)->getType()->isFloatingPoint() &&
I.getType() == I.getOperand(1)->getType()) {
- SDOperand Tmp = getValue(I.getOperand(1));
+ SDValue Tmp = getValue(I.getOperand(1));
setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
return;
}
@@ -3673,7 +3673,7 @@
if (I.getNumOperands() == 2 && // Basic sanity checks.
I.getOperand(1)->getType()->isFloatingPoint() &&
I.getType() == I.getOperand(1)->getType()) {
- SDOperand Tmp = getValue(I.getOperand(1));
+ SDValue Tmp = getValue(I.getOperand(1));
setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
return;
}
@@ -3684,7 +3684,7 @@
return;
}
- SDOperand Callee;
+ SDValue Callee;
if (!RenameFn)
Callee = getValue(I.getOperand(0));
else
@@ -3698,12 +3698,12 @@
/// this value and returns the result as a ValueVT value. This uses
/// Chain/Flag as the input and updates them for the output Chain/Flag.
/// If the Flag pointer is NULL, no flag is used.
-SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
- SDOperand &Chain,
- SDOperand *Flag) const {
+SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
+ SDValue &Chain,
+ SDValue *Flag) const {
// Assemble the legal parts into the final values.
- SmallVector<SDOperand, 4> Values(ValueVTs.size());
- SmallVector<SDOperand, 8> Parts;
+ SmallVector<SDValue, 4> Values(ValueVTs.size());
+ SmallVector<SDValue, 8> Parts;
for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
// Copy the legal parts from the registers.
MVT ValueVT = ValueVTs[Value];
@@ -3712,7 +3712,7 @@
Parts.resize(NumRegs);
for (unsigned i = 0; i != NumRegs; ++i) {
- SDOperand P;
+ SDValue P;
if (Flag == 0)
P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT);
else {
@@ -3779,11 +3779,11 @@
/// specified value into the registers specified by this object. This uses
/// Chain/Flag as the input and updates them for the output Chain/Flag.
/// If the Flag pointer is NULL, no flag is used.
-void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
- SDOperand &Chain, SDOperand *Flag) const {
+void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG,
+ SDValue &Chain, SDValue *Flag) const {
// Get the list of the values's legal parts.
unsigned NumRegs = Regs.size();
- SmallVector<SDOperand, 8> Parts(NumRegs);
+ SmallVector<SDValue, 8> Parts(NumRegs);
for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
MVT ValueVT = ValueVTs[Value];
unsigned NumParts = TLI->getNumRegisters(ValueVT);
@@ -3795,9 +3795,9 @@
}
// Copy the parts into the registers.
- SmallVector<SDOperand, 8> Chains(NumRegs);
+ SmallVector<SDValue, 8> Chains(NumRegs);
for (unsigned i = 0; i != NumRegs; ++i) {
- SDOperand Part;
+ SDValue Part;
if (Flag == 0)
Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
else {
@@ -3827,7 +3827,7 @@
/// operand list. This adds the code marker and includes the number of
/// values added into it.
void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
- std::vector<SDOperand> &Ops) const {
+ std::vector<SDValue> &Ops) const {
MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
@@ -3894,7 +3894,7 @@
/// CallOperand - If this is the result output operand or a clobber
/// this is null, otherwise it is the incoming operand to the CallInst.
/// This gets modified as the asm is processed.
- SDOperand CallOperand;
+ SDValue CallOperand;
/// AssignedRegs - If this is a register or register class operand, this
/// contains the set of register corresponding to the operand.
@@ -4115,8 +4115,8 @@
/// ConstraintOperands - Information about all of the constraints.
std::vector<SDISelAsmOperandInfo> ConstraintOperands;
- SDOperand Chain = getRoot();
- SDOperand Flag;
+ SDValue Chain = getRoot();
+ SDValue Flag;
std::set<unsigned> OutputRegs, InputRegs;
@@ -4247,7 +4247,7 @@
unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
MachineFunction &MF = DAG.getMachineFunction();
int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
- SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
+ SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0);
OpInfo.CallOperand = StackSlot;
}
@@ -4278,8 +4278,8 @@
}
// AsmNodeOperands - The operands for the ISD::INLINEASM node.
- std::vector<SDOperand> AsmNodeOperands;
- AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
+ std::vector<SDValue> AsmNodeOperands;
+ AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
AsmNodeOperands.push_back(
DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
@@ -4338,7 +4338,7 @@
break;
}
case InlineAsm::isInput: {
- SDOperand InOperandVal = OpInfo.CallOperand;
+ SDValue InOperandVal = OpInfo.CallOperand;
if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint?
// If this is required to match an output register we have already set,
@@ -4392,7 +4392,7 @@
assert(!OpInfo.isIndirect &&
"Don't know how to handle indirect other inputs yet!");
- std::vector<SDOperand> Ops;
+ std::vector<SDValue> Ops;
TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
Ops, DAG);
if (Ops.empty()) {
@@ -4459,7 +4459,7 @@
// If this asm returns a register value, copy the result from that register
// and set it as the value of the call.
if (!RetValRegs.Regs.empty()) {
- SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag);
+ SDValue Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag);
// If any of the results of the inline asm is a vector, it may have the
// wrong width/num elts. This can happen for register classes that can
@@ -4481,19 +4481,19 @@
setValue(CS.getInstruction(), Val);
}
- std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
+ std::vector<std::pair<SDValue, Value*> > StoresToEmit;
// Process indirect outputs, first output all of the flagged copies out of
// physregs.
for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
Value *Ptr = IndirectStoresToEmit[i].second;
- SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag);
+ SDValue OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag);
StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
}
// Emit the non-flagged stores from the physregs.
- SmallVector<SDOperand, 8> OutChains;
+ SmallVector<SDValue, 8> OutChains;
for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
getValue(StoresToEmit[i].second),
@@ -4506,7 +4506,7 @@
void SelectionDAGLowering::visitMalloc(MallocInst &I) {
- SDOperand Src = getValue(I.getOperand(0));
+ SDValue Src = getValue(I.getOperand(0));
MVT IntPtr = TLI.getPointerTy();
@@ -4526,7 +4526,7 @@
Entry.Ty = TLI.getTargetData()->getIntPtrType();
Args.push_back(Entry);
- std::pair<SDOperand,SDOperand> Result =
+ std::pair<SDValue,SDValue> Result =
TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, CallingConv::C,
true, DAG.getExternalSymbol("malloc", IntPtr), Args, DAG);
setValue(&I, Result.first); // Pointers always fit in registers
@@ -4540,7 +4540,7 @@
Entry.Ty = TLI.getTargetData()->getIntPtrType();
Args.push_back(Entry);
MVT IntPtr = TLI.getPointerTy();
- std::pair<SDOperand,SDOperand> Result =
+ std::pair<SDValue,SDValue> Result =
TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false,
CallingConv::C, true,
DAG.getExternalSymbol("free", IntPtr), Args, DAG);
@@ -4568,7 +4568,7 @@
}
void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
- SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
+ SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
getValue(I.getOperand(0)),
DAG.getSrcValue(I.getOperand(0)));
setValue(&I, V);
@@ -4594,9 +4594,9 @@
/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
/// integrated into SDISel.
void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
- SmallVectorImpl<SDOperand> &ArgValues) {
+ SmallVectorImpl<SDValue> &ArgValues) {
// Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
- SmallVector<SDOperand, 3+16> Ops;
+ SmallVector<SDValue, 3+16> Ops;
Ops.push_back(DAG.getRoot());
Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
@@ -4666,7 +4666,7 @@
// Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
// allows exposing the loads that may be part of the argument access to the
// first DAGCombiner pass.
- SDOperand TmpRes = LowerOperation(SDOperand(Result, 0), DAG);
+ SDValue TmpRes = LowerOperation(SDValue(Result, 0), DAG);
// The number of results should match up, except that the lowered one may have
// an extra flag result.
@@ -4684,7 +4684,7 @@
Result = TmpRes.Val;
unsigned NumArgRegs = Result->getNumValues() - 1;
- DAG.setRoot(SDOperand(Result, NumArgRegs));
+ DAG.setRoot(SDValue(Result, NumArgRegs));
// Set up the return result vector.
unsigned i = 0;
@@ -4699,9 +4699,9 @@
MVT PartVT = getRegisterType(VT);
unsigned NumParts = getNumRegisters(VT);
- SmallVector<SDOperand, 4> Parts(NumParts);
+ SmallVector<SDValue, 4> Parts(NumParts);
for (unsigned j = 0; j != NumParts; ++j)
- Parts[j] = SDOperand(Result, i++);
+ Parts[j] = SDValue(Result, i++);
ISD::NodeType AssertOp = ISD::DELETED_NODE;
if (F.paramHasAttr(Idx, ParamAttr::SExt))
@@ -4721,13 +4721,13 @@
/// implementation, which just inserts an ISD::CALL node, which is later custom
/// lowered by the target to something concrete. FIXME: When all targets are
/// migrated to using ISD::CALL, this hook should be integrated into SDISel.
-std::pair<SDOperand, SDOperand>
-TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
+std::pair<SDValue, SDValue>
+TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
bool RetSExt, bool RetZExt, bool isVarArg,
unsigned CallingConv, bool isTailCall,
- SDOperand Callee,
+ SDValue Callee,
ArgListTy &Args, SelectionDAG &DAG) {
- SmallVector<SDOperand, 32> Ops;
+ SmallVector<SDValue, 32> Ops;
Ops.push_back(Chain); // Op#0 - Chain
Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
@@ -4742,7 +4742,7 @@
Value != NumValues; ++Value) {
MVT VT = ValueVTs[Value];
const Type *ArgTy = VT.getTypeForMVT();
- SDOperand Op = SDOperand(Args[i].Node.Val, Args[i].Node.ResNo + Value);
+ SDValue Op = SDValue(Args[i].Node.Val, Args[i].Node.ResNo + Value);
ISD::ArgFlagsTy Flags;
unsigned OriginalAlignment =
getTargetData()->getABITypeAlignment(ArgTy);
@@ -4774,7 +4774,7 @@
MVT PartVT = getRegisterType(VT);
unsigned NumParts = getNumRegisters(VT);
- SmallVector<SDOperand, 4> Parts(NumParts);
+ SmallVector<SDValue, 4> Parts(NumParts);
ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
if (Args[i].isSExt)
@@ -4816,7 +4816,7 @@
LoweredRetTys.push_back(MVT::Other); // Always has a chain.
// Create the CALL node.
- SDOperand Res = DAG.getNode(ISD::CALL,
+ SDValue Res = DAG.getNode(ISD::CALL,
DAG.getVTList(&LoweredRetTys[0],
LoweredRetTys.size()),
&Ops[0], Ops.size());
@@ -4831,17 +4831,17 @@
else if (RetZExt)
AssertOp = ISD::AssertZext;
- SmallVector<SDOperand, 4> ReturnValues;
+ SmallVector<SDValue, 4> ReturnValues;
unsigned RegNo = 0;
for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
MVT VT = RetTys[I];
MVT RegisterVT = getRegisterType(VT);
unsigned NumRegs = getNumRegisters(VT);
unsigned RegNoEnd = NumRegs + RegNo;
- SmallVector<SDOperand, 4> Results;
+ SmallVector<SDValue, 4> Results;
for (; RegNo != RegNoEnd; ++RegNo)
Results.push_back(Res.getValue(RegNo));
- SDOperand ReturnValue =
+ SDValue ReturnValue =
getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT,
AssertOp);
ReturnValues.push_back(ReturnValue);
@@ -4853,10 +4853,10 @@
return std::make_pair(Res, Chain);
}
-SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
+SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
assert(0 && "LowerOperation not implemented for this target!");
abort();
- return SDOperand();
+ return SDValue();
}
@@ -4912,14 +4912,14 @@
}
void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
- SDOperand Op = getValue(V);
+ SDValue Op = getValue(V);
assert((Op.getOpcode() != ISD::CopyFromReg ||
cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
"Copy from a reg to the same reg!");
assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
RegsForValue RFV(TLI, Reg, V->getType());
- SDOperand Chain = DAG.getEntryNode();
+ SDValue Chain = DAG.getEntryNode();
RFV.getCopyToRegs(Op, DAG, Chain, 0);
PendingExports.push_back(Chain);
}
@@ -4929,8 +4929,8 @@
// If this is the entry block, emit arguments.
Function &F = *LLVMBB->getParent();
FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
- SDOperand OldRoot = SDL.DAG.getRoot();
- SmallVector<SDOperand, 16> Args;
+ SDValue OldRoot = SDL.DAG.getRoot();
+ SmallVector<SDValue, 16> Args;
TLI.LowerArguments(F, SDL.DAG, Args);
unsigned a = 0;
@@ -4972,7 +4972,7 @@
/// IsFixedFrameObjectWithPosOffset - Check if object is a fixed frame object and
/// whether object offset >= 0.
static bool
-IsFixedFrameObjectWithPosOffset(MachineFrameInfo * MFI, SDOperand Op) {
+IsFixedFrameObjectWithPosOffset(MachineFrameInfo * MFI, SDValue Op) {
if (!isa<FrameIndexSDNode>(Op)) return false;
FrameIndexSDNode * FrameIdxNode = dyn_cast<FrameIndexSDNode>(Op);
@@ -4986,7 +4986,7 @@
/// call. Currently the implementation of this call is very conservative and
/// assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with
/// virtual registers would be overwritten by direct lowering.
-static bool IsPossiblyOverwrittenArgumentOfTailCall(SDOperand Op,
+static bool IsPossiblyOverwrittenArgumentOfTailCall(SDValue Op,
MachineFrameInfo * MFI) {
RegisterSDNode * OpReg = NULL;
if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS ||
@@ -5008,7 +5008,7 @@
static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
TargetLowering& TLI) {
SDNode * Ret = NULL;
- SDOperand Terminator = DAG.getRoot();
+ SDValue Terminator = DAG.getRoot();
// Find RET node.
if (Terminator.getOpcode() == ISD::RET) {
@@ -5020,8 +5020,8 @@
BI = DAG.allnodes_end(); BI != BE; ) {
--BI;
if (BI->getOpcode() == ISD::CALL) {
- SDOperand OpRet(Ret, 0);
- SDOperand OpCall(BI, 0);
+ SDValue OpRet(Ret, 0);
+ SDValue OpCall(BI, 0);
bool isMarkedTailCall =
cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0;
// If CALL node has tail call attribute set to true and the call is not
@@ -5032,7 +5032,7 @@
if (Ret==NULL ||
!TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG)) {
// Not eligible. Mark CALL node as non tail call.
- SmallVector<SDOperand, 32> Ops;
+ SmallVector<SDValue, 32> Ops;
unsigned idx=0;
for(SDNode::op_iterator I =OpCall.Val->op_begin(),
E = OpCall.Val->op_end(); I != E; I++, idx++) {
@@ -5045,12 +5045,12 @@
} else {
// Look for tail call clobbered arguments. Emit a series of
// copyto/copyfrom virtual register nodes to protect them.
- SmallVector<SDOperand, 32> Ops;
- SDOperand Chain = OpCall.getOperand(0), InFlag;
+ SmallVector<SDValue, 32> Ops;
+ SDValue Chain = OpCall.getOperand(0), InFlag;
unsigned idx=0;
for(SDNode::op_iterator I = OpCall.Val->op_begin(),
E = OpCall.Val->op_end(); I != E; I++, idx++) {
- SDOperand Arg = *I;
+ SDValue Arg = *I;
if (idx > 4 && (idx % 2)) {
bool isByVal = cast<ARG_FLAGSSDNode>(OpCall.getOperand(idx+1))->
getArgFlags().isByVal();
@@ -5271,7 +5271,7 @@
continue;
// Ignore non-scalar or non-integer values.
- SDOperand Src = N->getOperand(2);
+ SDValue Src = N->getOperand(2);
MVT SrcVT = Src.getValueType();
if (!SrcVT.isInteger() || SrcVT.isVector())
continue;
@@ -5692,7 +5692,7 @@
/// the dag combiner simplified the 255, we still want to match. RHS is the
/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
/// specified in the .td file (e.g. 255).
-bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
+bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
int64_t DesiredMaskS) const {
const APInt &ActualMask = RHS->getAPIntValue();
const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
@@ -5721,7 +5721,7 @@
/// the dag combiner simplified the 255, we still want to match. RHS is the
/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
/// specified in the .td file (e.g. 255).
-bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
+bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
int64_t DesiredMaskS) const {
const APInt &ActualMask = RHS->getAPIntValue();
const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
@@ -5755,8 +5755,8 @@
/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
/// by tblgen. Others should not call it.
void SelectionDAGISel::
-SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
- std::vector<SDOperand> InOps;
+SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops, SelectionDAG &DAG) {
+ std::vector<SDValue> InOps;
std::swap(InOps, Ops);
Ops.push_back(InOps[0]); // input chain.
@@ -5775,7 +5775,7 @@
} else {
assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
// Otherwise, this is a memory operand. Ask the target to select it.
- std::vector<SDOperand> SelOps;
+ std::vector<SDValue> SelOps;
if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
cerr << "Could not match memory address. Inline asm failure!\n";
exit(1);
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp Sun Jul 27 16:46:04 2008
@@ -80,7 +80,7 @@
/// edge, override this method.
template<typename EdgeIter>
static std::string getEdgeAttributes(const void *Node, EdgeIter EI) {
- SDOperand Op = EI.getNode()->getOperand(EI.getOperand());
+ SDValue Op = EI.getNode()->getOperand(EI.getOperand());
MVT VT = Op.getValueType();
if (VT == MVT::Flag)
return "color=red,style=bold";
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Sun Jul 27 16:46:04 2008
@@ -516,7 +516,7 @@
}
-MVT TargetLowering::getSetCCResultType(const SDOperand &) const {
+MVT TargetLowering::getSetCCResultType(const SDValue &) const {
return getValueType(TD->getIntPtrType());
}
@@ -582,8 +582,8 @@
return TD->getCallFrameTypeAlignment(Ty);
}
-SDOperand TargetLowering::getPICJumpTableRelocBase(SDOperand Table,
- SelectionDAG &DAG) const {
+SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
+ SelectionDAG &DAG) const {
if (usesGlobalOffsetTable())
return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy());
return Table;
@@ -597,7 +597,7 @@
/// specified instruction is a constant integer. If so, check to see if there
/// are any bits set in the constant that are not demanded. If so, shrink the
/// constant and return true.
-bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op,
+bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
const APInt &Demanded) {
// FIXME: ISD::SELECT, ISD::SELECT_CC
switch(Op.getOpcode()) {
@@ -608,7 +608,7 @@
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
if (C->getAPIntValue().intersects(~Demanded)) {
MVT VT = Op.getValueType();
- SDOperand New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0),
+ SDValue New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0),
DAG.getConstant(Demanded &
C->getAPIntValue(),
VT));
@@ -626,7 +626,7 @@
/// analyze the expression and return a mask of KnownOne and KnownZero bits for
/// the expression (used to simplify the caller). The KnownZero/One bits may
/// only be accurate for those bits in the DemandedMask.
-bool TargetLowering::SimplifyDemandedBits(SDOperand Op,
+bool TargetLowering::SimplifyDemandedBits(SDValue Op,
const APInt &DemandedMask,
APInt &KnownZero,
APInt &KnownOne,
@@ -780,7 +780,7 @@
if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known
if ((KnownOne & KnownOne2) == KnownOne) {
MVT VT = Op.getValueType();
- SDOperand ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
+ SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0),
ANDC));
}
@@ -795,7 +795,7 @@
if (Expanded.isAllOnesValue()) {
if (Expanded != C->getAPIntValue()) {
MVT VT = Op.getValueType();
- SDOperand New = TLO.DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0),
+ SDValue New = TLO.DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0),
TLO.DAG.getConstant(Expanded, VT));
return TLO.CombineTo(Op, New);
}
@@ -848,7 +848,7 @@
case ISD::SHL:
if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
unsigned ShAmt = SA->getValue();
- SDOperand InOp = Op.getOperand(0);
+ SDValue InOp = Op.getOperand(0);
// If the shift count is an invalid immediate, don't do anything.
if (ShAmt >= BitWidth)
@@ -868,7 +868,7 @@
Opc = ISD::SRL;
}
- SDOperand NewSA =
+ SDValue NewSA =
TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
MVT VT = Op.getValueType();
return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT,
@@ -890,7 +890,7 @@
MVT VT = Op.getValueType();
unsigned ShAmt = SA->getValue();
unsigned VTSize = VT.getSizeInBits();
- SDOperand InOp = Op.getOperand(0);
+ SDValue InOp = Op.getOperand(0);
// If the shift count is an invalid immediate, don't do anything.
if (ShAmt >= BitWidth)
@@ -910,7 +910,7 @@
Opc = ISD::SHL;
}
- SDOperand NewSA =
+ SDValue NewSA =
TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT,
InOp.getOperand(0), NewSA));
@@ -1099,7 +1099,7 @@
// If the input is only used by this truncate, see if we can shrink it based
// on the known demanded bits.
if (Op.getOperand(0).Val->hasOneUse()) {
- SDOperand In = Op.getOperand(0);
+ SDValue In = Op.getOperand(0);
unsigned InBitWidth = In.getValueSizeInBits();
switch (In.getOpcode()) {
default: break;
@@ -1115,7 +1115,7 @@
if (ShAmt->getValue() < BitWidth && !(HighBits & NewMask)) {
// None of the shifted in bits are needed. Add a truncate of the
// shift input, then shift it.
- SDOperand NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE,
+ SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE,
Op.getValueType(),
In.getOperand(0));
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL,Op.getValueType(),
@@ -1152,10 +1152,10 @@
isOperationLegal(ISD::FGETSIGN, Op.getValueType())) {
// Make a FGETSIGN + SHL to move the sign bit into the appropriate
// place. We expect the SHL to be eliminated by other optimizations.
- SDOperand Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(),
+ SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(),
Op.getOperand(0));
unsigned ShVal = Op.getValueType().getSizeInBits()-1;
- SDOperand ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy());
+ SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy());
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(),
Sign, ShAmt));
}
@@ -1179,7 +1179,7 @@
/// computeMaskedBitsForTargetNode - Determine which of the bits specified
/// in Mask are known to be either zero or one and return them in the
/// KnownZero/KnownOne bitsets.
-void TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
+void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
const APInt &Mask,
APInt &KnownZero,
APInt &KnownOne,
@@ -1197,7 +1197,7 @@
/// ComputeNumSignBitsForTargetNode - This method can be implemented by
/// targets that want to expose additional information about sign bits to the
/// DAG Combiner.
-unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDOperand Op,
+unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
unsigned Depth) const {
assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
@@ -1210,9 +1210,9 @@
/// SimplifySetCC - Try to simplify a setcc built with the specified operands
-/// and cc. If it is unable to simplify it, return a null SDOperand.
-SDOperand
-TargetLowering::SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1,
+/// and cc. If it is unable to simplify it, return a null SDValue.
+SDValue
+TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
ISD::CondCode Cond, bool foldBooleans,
DAGCombinerInfo &DCI) const {
SelectionDAG &DAG = DCI.DAG;
@@ -1249,7 +1249,7 @@
// (srl (ctlz x), 5) == 1 -> X == 0
Cond = ISD::SETEQ;
}
- SDOperand Zero = DAG.getConstant(0, N0.getValueType());
+ SDValue Zero = DAG.getConstant(0, N0.getValueType());
return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0),
Zero, Cond);
}
@@ -1313,7 +1313,7 @@
if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
return DAG.getConstant(Cond == ISD::SETNE, VT);
- SDOperand ZextOp;
+ SDValue ZextOp;
MVT Op0Ty = N0.getOperand(0).getValueType();
if (Op0Ty == ExtSrcTy) {
ZextOp = N0.getOperand(0);
@@ -1360,7 +1360,7 @@
APInt::getHighBitsSet(BitWidth,
BitWidth-1))) {
// Okay, get the un-inverted input value.
- SDOperand Val;
+ SDValue Val;
if (N0.getOpcode() == ISD::XOR)
Val = N0.getOperand(0);
else {
@@ -1467,7 +1467,7 @@
if (isa<ConstantFPSDNode>(N0.Val)) {
// Constant fold or commute setcc.
- SDOperand O = DAG.FoldSetCC(VT, N0, N1, Cond);
+ SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond);
if (O.Val) return O;
} else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.Val)) {
// If the RHS of an FP comparison is a constant, simplify it away in
@@ -1574,7 +1574,7 @@
else if (N0.Val->hasOneUse()) {
assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
// (Z-X) == X --> Z == X<<1
- SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
+ SDValue SH = DAG.getNode(ISD::SHL, N1.getValueType(),
N1,
DAG.getConstant(1, getShiftAmountTy()));
if (!DCI.isCalledByLegalizer())
@@ -1597,7 +1597,7 @@
} else if (N1.Val->hasOneUse()) {
assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
// X == (Z-X) --> X<<1 == Z
- SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
+ SDValue SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
DAG.getConstant(1, getShiftAmountTy()));
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(SH.Val);
@@ -1608,7 +1608,7 @@
}
// Fold away ALL boolean setcc's.
- SDOperand Temp;
+ SDValue Temp;
if (N0.getValueType() == MVT::i1 && foldBooleans) {
switch (Cond) {
default: assert(0 && "Unknown integer setcc!");
@@ -1658,7 +1658,7 @@
}
// Could not fold it.
- return SDOperand();
+ return SDValue();
}
/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
@@ -1673,8 +1673,8 @@
}
if (N->getOpcode() == ISD::ADD) {
- SDOperand N1 = N->getOperand(0);
- SDOperand N2 = N->getOperand(1);
+ SDValue N1 = N->getOperand(0);
+ SDValue N2 = N->getOperand(1);
if (isGAPlusOffset(N1.Val, GA, Offset)) {
ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
if (V) {
@@ -1705,8 +1705,8 @@
if (VT.getSizeInBits() / 8 != Bytes)
return false;
- SDOperand Loc = LD->getOperand(1);
- SDOperand BaseLoc = Base->getOperand(1);
+ SDValue Loc = LD->getOperand(1);
+ SDValue BaseLoc = Base->getOperand(1);
if (Loc.getOpcode() == ISD::FrameIndex) {
if (BaseLoc.getOpcode() != ISD::FrameIndex)
return false;
@@ -1730,10 +1730,10 @@
}
-SDOperand TargetLowering::
+SDValue TargetLowering::
PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
// Default implementation: no optimization.
- return SDOperand();
+ return SDValue();
}
//===----------------------------------------------------------------------===//
@@ -1787,9 +1787,9 @@
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
/// vector. If it is invalid, don't add anything to Ops.
-void TargetLowering::LowerAsmOperandForConstraint(SDOperand Op,
+void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
char ConstraintLetter,
- std::vector<SDOperand> &Ops,
+ std::vector<SDValue> &Ops,
SelectionDAG &DAG) const {
switch (ConstraintLetter) {
default: break;
@@ -1931,7 +1931,7 @@
///
static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
const TargetLowering &TLI,
- SDOperand Op, SelectionDAG *DAG) {
+ SDValue Op, SelectionDAG *DAG) {
assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
unsigned BestIdx = 0;
TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
@@ -1949,7 +1949,7 @@
if (CType == TargetLowering::C_Other && Op.Val) {
assert(OpInfo.Codes[i].size() == 1 &&
"Unhandled multi-letter 'other' constraint");
- std::vector<SDOperand> ResultOps;
+ std::vector<SDValue> ResultOps;
TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0],
ResultOps, *DAG);
if (!ResultOps.empty()) {
@@ -1976,7 +1976,7 @@
/// type to use for the specific AsmOperandInfo, setting
/// OpInfo.ConstraintCode and OpInfo.ConstraintType.
void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
- SDOperand Op,
+ SDValue Op,
SelectionDAG *DAG) const {
assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
@@ -2221,28 +2221,28 @@
/// return a DAG expression to select that will generate the same value by
/// multiplying by a magic number. See:
/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
-SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
- std::vector<SDNode*>* Created) const {
+SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
+ std::vector<SDNode*>* Created) const {
MVT VT = N->getValueType(0);
// Check to see if we can do this.
if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
- return SDOperand(); // BuildSDIV only operates on i32 or i64
+ return SDValue(); // BuildSDIV only operates on i32 or i64
int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended();
ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d);
// Multiply the numerator (operand 0) by the magic value
- SDOperand Q;
+ SDValue Q;
if (isOperationLegal(ISD::MULHS, VT))
Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0),
DAG.getConstant(magics.m, VT));
else if (isOperationLegal(ISD::SMUL_LOHI, VT))
- Q = SDOperand(DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(VT, VT),
+ Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(VT, VT),
N->getOperand(0),
DAG.getConstant(magics.m, VT)).Val, 1);
else
- return SDOperand(); // No mulhs or equvialent
+ return SDValue(); // No mulhs or equvialent
// If d > 0 and m < 0, add the numerator
if (d > 0 && magics.m < 0) {
Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0));
@@ -2263,7 +2263,7 @@
Created->push_back(Q.Val);
}
// Extract the sign bit and add it to the quotient
- SDOperand T =
+ SDValue T =
DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
getShiftAmountTy()));
if (Created)
@@ -2275,28 +2275,28 @@
/// return a DAG expression to select that will generate the same value by
/// multiplying by a magic number. See:
/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
-SDOperand TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
- std::vector<SDNode*>* Created) const {
+SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
+ std::vector<SDNode*>* Created) const {
MVT VT = N->getValueType(0);
// Check to see if we can do this.
if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
- return SDOperand(); // BuildUDIV only operates on i32 or i64
+ return SDValue(); // BuildUDIV only operates on i32 or i64
uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue();
mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d);
// Multiply the numerator (operand 0) by the magic value
- SDOperand Q;
+ SDValue Q;
if (isOperationLegal(ISD::MULHU, VT))
Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0),
DAG.getConstant(magics.m, VT));
else if (isOperationLegal(ISD::UMUL_LOHI, VT))
- Q = SDOperand(DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(VT, VT),
+ Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(VT, VT),
N->getOperand(0),
DAG.getConstant(magics.m, VT)).Val, 1);
else
- return SDOperand(); // No mulhu or equvialent
+ return SDValue(); // No mulhu or equvialent
if (Created)
Created->push_back(Q.Val);
@@ -2304,7 +2304,7 @@
return DAG.getNode(ISD::SRL, VT, Q,
DAG.getConstant(magics.s, getShiftAmountTy()));
} else {
- SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q);
+ SDValue NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q);
if (Created)
Created->push_back(NPQ.Val);
NPQ = DAG.getNode(ISD::SRL, VT, NPQ,
Modified: llvm/trunk/lib/Target/ARM/ARMAddressingModes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAddressingModes.h?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAddressingModes.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMAddressingModes.h Sun Jul 27 16:46:04 2008
@@ -46,7 +46,7 @@
}
}
- static inline ShiftOpc getShiftOpcForNode(SDOperand N) {
+ static inline ShiftOpc getShiftOpcForNode(SDValue N) {
switch (N.getOpcode()) {
default: return ARM_AM::no_shift;
case ISD::SHL: return ARM_AM::lsl;
Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Sun Jul 27 16:46:04 2008
@@ -53,38 +53,38 @@
return "ARM Instruction Selection";
}
- SDNode *Select(SDOperand Op);
+ SDNode *Select(SDValue Op);
virtual void InstructionSelect(SelectionDAG &DAG);
- bool SelectAddrMode2(SDOperand Op, SDOperand N, SDOperand &Base,
- SDOperand &Offset, SDOperand &Opc);
- bool SelectAddrMode2Offset(SDOperand Op, SDOperand N,
- SDOperand &Offset, SDOperand &Opc);
- bool SelectAddrMode3(SDOperand Op, SDOperand N, SDOperand &Base,
- SDOperand &Offset, SDOperand &Opc);
- bool SelectAddrMode3Offset(SDOperand Op, SDOperand N,
- SDOperand &Offset, SDOperand &Opc);
- bool SelectAddrMode5(SDOperand Op, SDOperand N, SDOperand &Base,
- SDOperand &Offset);
-
- bool SelectAddrModePC(SDOperand Op, SDOperand N, SDOperand &Offset,
- SDOperand &Label);
-
- bool SelectThumbAddrModeRR(SDOperand Op, SDOperand N, SDOperand &Base,
- SDOperand &Offset);
- bool SelectThumbAddrModeRI5(SDOperand Op, SDOperand N, unsigned Scale,
- SDOperand &Base, SDOperand &OffImm,
- SDOperand &Offset);
- bool SelectThumbAddrModeS1(SDOperand Op, SDOperand N, SDOperand &Base,
- SDOperand &OffImm, SDOperand &Offset);
- bool SelectThumbAddrModeS2(SDOperand Op, SDOperand N, SDOperand &Base,
- SDOperand &OffImm, SDOperand &Offset);
- bool SelectThumbAddrModeS4(SDOperand Op, SDOperand N, SDOperand &Base,
- SDOperand &OffImm, SDOperand &Offset);
- bool SelectThumbAddrModeSP(SDOperand Op, SDOperand N, SDOperand &Base,
- SDOperand &OffImm);
+ bool SelectAddrMode2(SDValue Op, SDValue N, SDValue &Base,
+ SDValue &Offset, SDValue &Opc);
+ bool SelectAddrMode2Offset(SDValue Op, SDValue N,
+ SDValue &Offset, SDValue &Opc);
+ bool SelectAddrMode3(SDValue Op, SDValue N, SDValue &Base,
+ SDValue &Offset, SDValue &Opc);
+ bool SelectAddrMode3Offset(SDValue Op, SDValue N,
+ SDValue &Offset, SDValue &Opc);
+ bool SelectAddrMode5(SDValue Op, SDValue N, SDValue &Base,
+ SDValue &Offset);
+
+ bool SelectAddrModePC(SDValue Op, SDValue N, SDValue &Offset,
+ SDValue &Label);
+
+ bool SelectThumbAddrModeRR(SDValue Op, SDValue N, SDValue &Base,
+ SDValue &Offset);
+ bool SelectThumbAddrModeRI5(SDValue Op, SDValue N, unsigned Scale,
+ SDValue &Base, SDValue &OffImm,
+ SDValue &Offset);
+ bool SelectThumbAddrModeS1(SDValue Op, SDValue N, SDValue &Base,
+ SDValue &OffImm, SDValue &Offset);
+ bool SelectThumbAddrModeS2(SDValue Op, SDValue N, SDValue &Base,
+ SDValue &OffImm, SDValue &Offset);
+ bool SelectThumbAddrModeS4(SDValue Op, SDValue N, SDValue &Base,
+ SDValue &OffImm, SDValue &Offset);
+ bool SelectThumbAddrModeSP(SDValue Op, SDValue N, SDValue &Base,
+ SDValue &OffImm);
- bool SelectShifterOperandReg(SDOperand Op, SDOperand N, SDOperand &A,
- SDOperand &B, SDOperand &C);
+ bool SelectShifterOperandReg(SDValue Op, SDValue N, SDValue &A,
+ SDValue &B, SDValue &C);
// Include the pieces autogenerated from the target description.
#include "ARMGenDAGISel.inc"
@@ -98,9 +98,9 @@
DAG.RemoveDeadNodes();
}
-bool ARMDAGToDAGISel::SelectAddrMode2(SDOperand Op, SDOperand N,
- SDOperand &Base, SDOperand &Offset,
- SDOperand &Opc) {
+bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N,
+ SDValue &Base, SDValue &Offset,
+ SDValue &Opc) {
if (N.getOpcode() == ISD::MUL) {
if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
// X * [3,5,9] -> X + X * [2,4,8] etc.
@@ -206,8 +206,8 @@
return true;
}
-bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDOperand Op, SDOperand N,
- SDOperand &Offset, SDOperand &Opc) {
+bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDValue Op, SDValue N,
+ SDValue &Offset, SDValue &Opc) {
unsigned Opcode = Op.getOpcode();
ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
? cast<LoadSDNode>(Op)->getAddressingMode()
@@ -245,9 +245,9 @@
}
-bool ARMDAGToDAGISel::SelectAddrMode3(SDOperand Op, SDOperand N,
- SDOperand &Base, SDOperand &Offset,
- SDOperand &Opc) {
+bool ARMDAGToDAGISel::SelectAddrMode3(SDValue Op, SDValue N,
+ SDValue &Base, SDValue &Offset,
+ SDValue &Opc) {
if (N.getOpcode() == ISD::SUB) {
// X - C is canonicalize to X + -C, no need to handle it here.
Base = N.getOperand(0);
@@ -295,8 +295,8 @@
return true;
}
-bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDOperand Op, SDOperand N,
- SDOperand &Offset, SDOperand &Opc) {
+bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDValue Op, SDValue N,
+ SDValue &Offset, SDValue &Opc) {
unsigned Opcode = Op.getOpcode();
ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
? cast<LoadSDNode>(Op)->getAddressingMode()
@@ -318,8 +318,8 @@
}
-bool ARMDAGToDAGISel::SelectAddrMode5(SDOperand Op, SDOperand N,
- SDOperand &Base, SDOperand &Offset) {
+bool ARMDAGToDAGISel::SelectAddrMode5(SDValue Op, SDValue N,
+ SDValue &Base, SDValue &Offset) {
if (N.getOpcode() != ISD::ADD) {
Base = N;
if (N.getOpcode() == ISD::FrameIndex) {
@@ -364,11 +364,11 @@
return true;
}
-bool ARMDAGToDAGISel::SelectAddrModePC(SDOperand Op, SDOperand N,
- SDOperand &Offset, SDOperand &Label) {
+bool ARMDAGToDAGISel::SelectAddrModePC(SDValue Op, SDValue N,
+ SDValue &Offset, SDValue &Label) {
if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
Offset = N.getOperand(0);
- SDOperand N1 = N.getOperand(1);
+ SDValue N1 = N.getOperand(1);
Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getValue(),
MVT::i32);
return true;
@@ -376,14 +376,14 @@
return false;
}
-bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDOperand Op, SDOperand N,
- SDOperand &Base, SDOperand &Offset){
+bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue Op, SDValue N,
+ SDValue &Base, SDValue &Offset){
if (N.getOpcode() != ISD::ADD) {
Base = N;
// We must materialize a zero in a reg! Returning an constant here won't
// work since its node is -1 so it won't get added to the selection queue.
// Explicitly issue a tMOVri8 node!
- Offset = SDOperand(CurDAG->getTargetNode(ARM::tMOVi8, MVT::i32,
+ Offset = SDValue(CurDAG->getTargetNode(ARM::tMOVi8, MVT::i32,
CurDAG->getTargetConstant(0, MVT::i32)), 0);
return true;
}
@@ -394,11 +394,11 @@
}
bool
-ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDOperand Op, SDOperand N,
- unsigned Scale, SDOperand &Base,
- SDOperand &OffImm, SDOperand &Offset) {
+ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue Op, SDValue N,
+ unsigned Scale, SDValue &Base,
+ SDValue &OffImm, SDValue &Offset) {
if (Scale == 4) {
- SDOperand TmpBase, TmpOffImm;
+ SDValue TmpBase, TmpOffImm;
if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm))
return false; // We want to select tLDRspi / tSTRspi instead.
if (N.getOpcode() == ARMISD::Wrapper &&
@@ -444,26 +444,26 @@
return true;
}
-bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDOperand Op, SDOperand N,
- SDOperand &Base, SDOperand &OffImm,
- SDOperand &Offset) {
+bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue Op, SDValue N,
+ SDValue &Base, SDValue &OffImm,
+ SDValue &Offset) {
return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset);
}
-bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDOperand Op, SDOperand N,
- SDOperand &Base, SDOperand &OffImm,
- SDOperand &Offset) {
+bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue Op, SDValue N,
+ SDValue &Base, SDValue &OffImm,
+ SDValue &Offset) {
return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset);
}
-bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDOperand Op, SDOperand N,
- SDOperand &Base, SDOperand &OffImm,
- SDOperand &Offset) {
+bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue Op, SDValue N,
+ SDValue &Base, SDValue &OffImm,
+ SDValue &Offset) {
return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset);
}
-bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDOperand Op, SDOperand N,
- SDOperand &Base, SDOperand &OffImm) {
+bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue Op, SDValue N,
+ SDValue &Base, SDValue &OffImm) {
if (N.getOpcode() == ISD::FrameIndex) {
int FI = cast<FrameIndexSDNode>(N)->getIndex();
Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
@@ -498,11 +498,11 @@
return false;
}
-bool ARMDAGToDAGISel::SelectShifterOperandReg(SDOperand Op,
- SDOperand N,
- SDOperand &BaseReg,
- SDOperand &ShReg,
- SDOperand &Opc) {
+bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue Op,
+ SDValue N,
+ SDValue &BaseReg,
+ SDValue &ShReg,
+ SDValue &Opc) {
ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
// Don't match base register only case. That is matched to a separate
@@ -523,12 +523,12 @@
}
/// getAL - Returns a ARMCC::AL immediate node.
-static inline SDOperand getAL(SelectionDAG *CurDAG) {
+static inline SDValue getAL(SelectionDAG *CurDAG) {
return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
}
-SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
+SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
SDNode *N = Op.Val;
if (N->isMachineOpcode())
@@ -548,7 +548,7 @@
ARM_AM::getSOImmVal(~Val) == -1 && // MVN
!ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
if (UseCP) {
- SDOperand CPIdx =
+ SDValue CPIdx =
CurDAG->getTargetConstantPool(ConstantInt::get(Type::Int32Ty, Val),
TLI.getPointerTy());
@@ -557,7 +557,7 @@
ResNode = CurDAG->getTargetNode(ARM::tLDRcp, MVT::i32, MVT::Other,
CPIdx, CurDAG->getEntryNode());
else {
- SDOperand Ops[] = {
+ SDValue Ops[] = {
CPIdx,
CurDAG->getRegister(0, MVT::i32),
CurDAG->getTargetConstant(0, MVT::i32),
@@ -567,7 +567,7 @@
};
ResNode=CurDAG->getTargetNode(ARM::LDRcp, MVT::i32, MVT::Other, Ops, 6);
}
- ReplaceUses(Op, SDOperand(ResNode, 0));
+ ReplaceUses(Op, SDValue(ResNode, 0));
return NULL;
}
@@ -577,12 +577,12 @@
case ISD::FrameIndex: {
// Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
int FI = cast<FrameIndexSDNode>(N)->getIndex();
- SDOperand TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
+ SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
if (Subtarget->isThumb())
return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
CurDAG->getTargetConstant(0, MVT::i32));
else {
- SDOperand Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
+ SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
CurDAG->getRegister(0, MVT::i32) };
return CurDAG->SelectNodeTo(N, ARM::ADDri, MVT::i32, Ops, 5);
@@ -590,8 +590,8 @@
}
case ISD::ADD: {
// Select add sp, c to tADDhirr.
- SDOperand N0 = Op.getOperand(0);
- SDOperand N1 = Op.getOperand(1);
+ SDValue N0 = Op.getOperand(0);
+ SDValue N1 = Op.getOperand(1);
RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(Op.getOperand(0));
RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(Op.getOperand(1));
if (LHSR && LHSR->getReg() == ARM::SP) {
@@ -612,20 +612,20 @@
unsigned RHSV = C->getValue();
if (!RHSV) break;
if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
- SDOperand V = Op.getOperand(0);
+ SDValue V = Op.getOperand(0);
AddToISelQueue(V);
unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV-1));
- SDOperand Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
+ SDValue Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
CurDAG->getTargetConstant(ShImm, MVT::i32),
getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
CurDAG->getRegister(0, MVT::i32) };
return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
}
if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
- SDOperand V = Op.getOperand(0);
+ SDValue V = Op.getOperand(0);
AddToISelQueue(V);
unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV+1));
- SDOperand Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
+ SDValue Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
CurDAG->getTargetConstant(ShImm, MVT::i32),
getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
CurDAG->getRegister(0, MVT::i32) };
@@ -641,7 +641,7 @@
case ISD::UMUL_LOHI: {
AddToISelQueue(Op.getOperand(0));
AddToISelQueue(Op.getOperand(1));
- SDOperand Ops[] = { Op.getOperand(0), Op.getOperand(1),
+ SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
CurDAG->getRegister(0, MVT::i32) };
return CurDAG->getTargetNode(ARM::UMULL, MVT::i32, MVT::i32, Ops, 5);
@@ -649,7 +649,7 @@
case ISD::SMUL_LOHI: {
AddToISelQueue(Op.getOperand(0));
AddToISelQueue(Op.getOperand(1));
- SDOperand Ops[] = { Op.getOperand(0), Op.getOperand(1),
+ SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
CurDAG->getRegister(0, MVT::i32) };
return CurDAG->getTargetNode(ARM::SMULL, MVT::i32, MVT::i32, Ops, 5);
@@ -659,7 +659,7 @@
ISD::MemIndexedMode AM = LD->getAddressingMode();
MVT LoadedVT = LD->getMemoryVT();
if (AM != ISD::UNINDEXED) {
- SDOperand Offset, AMOpc;
+ SDValue Offset, AMOpc;
bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
unsigned Opcode = 0;
bool Match = false;
@@ -688,12 +688,12 @@
}
if (Match) {
- SDOperand Chain = LD->getChain();
- SDOperand Base = LD->getBasePtr();
+ SDValue Chain = LD->getChain();
+ SDValue Base = LD->getBasePtr();
AddToISelQueue(Chain);
AddToISelQueue(Base);
AddToISelQueue(Offset);
- SDOperand Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
+ SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
CurDAG->getRegister(0, MVT::i32), Chain };
return CurDAG->getTargetNode(Opcode, MVT::i32, MVT::i32,
MVT::Other, Ops, 6);
@@ -712,11 +712,11 @@
// Pattern complexity = 6 cost = 1 size = 0
unsigned Opc = Subtarget->isThumb() ? ARM::tBcc : ARM::Bcc;
- SDOperand Chain = Op.getOperand(0);
- SDOperand N1 = Op.getOperand(1);
- SDOperand N2 = Op.getOperand(2);
- SDOperand N3 = Op.getOperand(3);
- SDOperand InFlag = Op.getOperand(4);
+ SDValue Chain = Op.getOperand(0);
+ SDValue N1 = Op.getOperand(1);
+ SDValue N2 = Op.getOperand(2);
+ SDValue N3 = Op.getOperand(3);
+ SDValue InFlag = Op.getOperand(4);
assert(N1.getOpcode() == ISD::BasicBlock);
assert(N2.getOpcode() == ISD::Constant);
assert(N3.getOpcode() == ISD::Register);
@@ -724,35 +724,35 @@
AddToISelQueue(Chain);
AddToISelQueue(N1);
AddToISelQueue(InFlag);
- SDOperand Tmp2 = CurDAG->getTargetConstant(((unsigned)
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N2)->getValue()), MVT::i32);
- SDOperand Ops[] = { N1, Tmp2, N3, Chain, InFlag };
+ SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
SDNode *ResNode = CurDAG->getTargetNode(Opc, MVT::Other, MVT::Flag, Ops, 5);
- Chain = SDOperand(ResNode, 0);
+ Chain = SDValue(ResNode, 0);
if (Op.Val->getNumValues() == 2) {
- InFlag = SDOperand(ResNode, 1);
- ReplaceUses(SDOperand(Op.Val, 1), InFlag);
+ InFlag = SDValue(ResNode, 1);
+ ReplaceUses(SDValue(Op.Val, 1), InFlag);
}
- ReplaceUses(SDOperand(Op.Val, 0), SDOperand(Chain.Val, Chain.ResNo));
+ ReplaceUses(SDValue(Op.Val, 0), SDValue(Chain.Val, Chain.ResNo));
return NULL;
}
case ARMISD::CMOV: {
bool isThumb = Subtarget->isThumb();
MVT VT = Op.getValueType();
- SDOperand N0 = Op.getOperand(0);
- SDOperand N1 = Op.getOperand(1);
- SDOperand N2 = Op.getOperand(2);
- SDOperand N3 = Op.getOperand(3);
- SDOperand InFlag = Op.getOperand(4);
+ SDValue N0 = Op.getOperand(0);
+ SDValue N1 = Op.getOperand(1);
+ SDValue N2 = Op.getOperand(2);
+ SDValue N3 = Op.getOperand(3);
+ SDValue InFlag = Op.getOperand(4);
assert(N2.getOpcode() == ISD::Constant);
assert(N3.getOpcode() == ISD::Register);
// Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
// Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
// Pattern complexity = 18 cost = 1 size = 0
- SDOperand CPTmp0;
- SDOperand CPTmp1;
- SDOperand CPTmp2;
+ SDValue CPTmp0;
+ SDValue CPTmp1;
+ SDValue CPTmp2;
if (!isThumb && VT == MVT::i32 &&
SelectShifterOperandReg(Op, N1, CPTmp0, CPTmp1, CPTmp2)) {
AddToISelQueue(N0);
@@ -760,9 +760,9 @@
AddToISelQueue(CPTmp1);
AddToISelQueue(CPTmp2);
AddToISelQueue(InFlag);
- SDOperand Tmp2 = CurDAG->getTargetConstant(((unsigned)
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N2)->getValue()), MVT::i32);
- SDOperand Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag };
+ SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag };
return CurDAG->SelectNodeTo(Op.Val, ARM::MOVCCs, MVT::i32, Ops, 7);
}
@@ -777,12 +777,12 @@
Predicate_so_imm(N3.Val)) {
AddToISelQueue(N0);
AddToISelQueue(InFlag);
- SDOperand Tmp1 = CurDAG->getTargetConstant(((unsigned)
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N1)->getValue()), MVT::i32);
Tmp1 = Transform_so_imm_XFORM(Tmp1.Val);
- SDOperand Tmp2 = CurDAG->getTargetConstant(((unsigned)
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N2)->getValue()), MVT::i32);
- SDOperand Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
+ SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
return CurDAG->SelectNodeTo(Op.Val, ARM::MOVCCi, MVT::i32, Ops, 5);
}
@@ -798,9 +798,9 @@
AddToISelQueue(N0);
AddToISelQueue(N1);
AddToISelQueue(InFlag);
- SDOperand Tmp2 = CurDAG->getTargetConstant(((unsigned)
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N2)->getValue()), MVT::i32);
- SDOperand Ops[] = { N0, N1, Tmp2, N3, InFlag };
+ SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
unsigned Opc = 0;
switch (VT.getSimpleVT()) {
default: assert(false && "Illegal conditional move type!");
@@ -819,20 +819,20 @@
}
case ARMISD::CNEG: {
MVT VT = Op.getValueType();
- SDOperand N0 = Op.getOperand(0);
- SDOperand N1 = Op.getOperand(1);
- SDOperand N2 = Op.getOperand(2);
- SDOperand N3 = Op.getOperand(3);
- SDOperand InFlag = Op.getOperand(4);
+ SDValue N0 = Op.getOperand(0);
+ SDValue N1 = Op.getOperand(1);
+ SDValue N2 = Op.getOperand(2);
+ SDValue N3 = Op.getOperand(3);
+ SDValue InFlag = Op.getOperand(4);
assert(N2.getOpcode() == ISD::Constant);
assert(N3.getOpcode() == ISD::Register);
AddToISelQueue(N0);
AddToISelQueue(N1);
AddToISelQueue(InFlag);
- SDOperand Tmp2 = CurDAG->getTargetConstant(((unsigned)
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N2)->getValue()), MVT::i32);
- SDOperand Ops[] = { N0, N1, Tmp2, N3, InFlag };
+ SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
unsigned Opc = 0;
switch (VT.getSimpleVT()) {
default: assert(false && "Illegal conditional move type!");
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Sun Jul 27 16:46:04 2008
@@ -399,13 +399,13 @@
/// LowerCALL - Lowering a ISD::CALL node into a callseq_start <-
/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
/// nodes.
-SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
+SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
MVT RetVT= Op.Val->getValueType(0);
- SDOperand Chain = Op.getOperand(0);
+ SDValue Chain = Op.getOperand(0);
unsigned CallConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
assert((CallConv == CallingConv::C ||
CallConv == CallingConv::Fast) && "unknown calling convention");
- SDOperand Callee = Op.getOperand(4);
+ SDValue Callee = Op.getOperand(4);
unsigned NumOps = (Op.getNumOperands() - 5) / 2;
unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
unsigned NumGPRs = 0; // GPRs used for parameter passing.
@@ -433,17 +433,17 @@
Chain = DAG.getCALLSEQ_START(Chain,
DAG.getConstant(NumBytes, MVT::i32));
- SDOperand StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
+ SDValue StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
static const unsigned GPRArgRegs[] = {
ARM::R0, ARM::R1, ARM::R2, ARM::R3
};
NumGPRs = 0;
- std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
- std::vector<SDOperand> MemOpChains;
+ std::vector<std::pair<unsigned, SDValue> > RegsToPass;
+ std::vector<SDValue> MemOpChains;
for (unsigned i = 0; i != NumOps; ++i) {
- SDOperand Arg = Op.getOperand(5+2*i);
+ SDValue Arg = Op.getOperand(5+2*i);
ISD::ArgFlagsTy Flags =
cast<ARG_FLAGSSDNode>(Op.getOperand(5+2*i+1))->getArgFlags();
MVT ArgVT = Arg.getValueType();
@@ -467,22 +467,22 @@
DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Arg)));
break;
case MVT::i64: {
- SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg,
+ SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg,
DAG.getConstant(0, getPointerTy()));
- SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg,
+ SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg,
DAG.getConstant(1, getPointerTy()));
RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Lo));
if (ObjGPRs == 2)
RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1], Hi));
else {
- SDOperand PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType());
+ SDValue PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType());
PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
MemOpChains.push_back(DAG.getStore(Chain, Hi, PtrOff, NULL, 0));
}
break;
}
case MVT::f64: {
- SDOperand Cvt = DAG.getNode(ARMISD::FMRRD,
+ SDValue Cvt = DAG.getNode(ARMISD::FMRRD,
DAG.getVTList(MVT::i32, MVT::i32),
&Arg, 1);
RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Cvt));
@@ -490,7 +490,7 @@
RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1],
Cvt.getValue(1)));
else {
- SDOperand PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType());
+ SDValue PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType());
PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
MemOpChains.push_back(DAG.getStore(Chain, Cvt.getValue(1), PtrOff,
NULL, 0));
@@ -500,7 +500,7 @@
}
} else {
assert(ObjSize != 0);
- SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
+ SDValue PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
}
@@ -515,7 +515,7 @@
// Build a sequence of copy-to-reg nodes chained together with token chain
// and flag operands which copy the outgoing args into the appropriate regs.
- SDOperand InFlag;
+ SDValue InFlag;
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
InFlag);
@@ -542,10 +542,10 @@
if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
ARMCP::CPStub, 4);
- SDOperand CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2);
+ SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2);
CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0);
- SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
+ SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel);
} else
Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
@@ -559,10 +559,10 @@
if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex,
ARMCP::CPStub, 4);
- SDOperand CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2);
+ SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2);
CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0);
- SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
+ SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel);
} else
Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
@@ -587,7 +587,7 @@
InFlag = Chain.getValue(1);
}
- std::vector<SDOperand> Ops;
+ std::vector<SDValue> Ops;
Ops.push_back(Chain);
Ops.push_back(Callee);
@@ -611,7 +611,7 @@
if (RetVT != MVT::Other)
InFlag = Chain.getValue(1);
- std::vector<SDOperand> ResultVals;
+ std::vector<SDValue> ResultVals;
// If the call has results, copy the values out of the ret val registers.
switch (RetVT.getSimpleVT()) {
@@ -634,8 +634,8 @@
Chain.getValue(0)));
break;
case MVT::f64: {
- SDOperand Lo = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag);
- SDOperand Hi = DAG.getCopyFromReg(Lo, ARM::R1, MVT::i32, Lo.getValue(2));
+ SDValue Lo = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag);
+ SDValue Hi = DAG.getCopyFromReg(Lo, ARM::R1, MVT::i32, Lo.getValue(2));
ResultVals.push_back(DAG.getNode(ARMISD::FMDRR, MVT::f64, Lo, Hi));
break;
}
@@ -645,19 +645,19 @@
return Chain;
ResultVals.push_back(Chain);
- SDOperand Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size());
+ SDValue Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size());
return Res.getValue(Op.ResNo);
}
-static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
- SDOperand Copy;
- SDOperand Chain = Op.getOperand(0);
+static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) {
+ SDValue Copy;
+ SDValue Chain = Op.getOperand(0);
switch(Op.getNumOperands()) {
default:
assert(0 && "Do not know how to return this many arguments!");
abort();
case 1: {
- SDOperand LR = DAG.getRegister(ARM::LR, MVT::i32);
+ SDValue LR = DAG.getRegister(ARM::LR, MVT::i32);
return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Chain);
}
case 3:
@@ -668,16 +668,16 @@
// Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
// available.
Op = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32), &Op,1);
- SDOperand Sign = DAG.getConstant(0, MVT::i32);
+ SDValue Sign = DAG.getConstant(0, MVT::i32);
return DAG.getNode(ISD::RET, MVT::Other, Chain, Op, Sign,
Op.getValue(1), Sign);
}
- Copy = DAG.getCopyToReg(Chain, ARM::R0, Op, SDOperand());
+ Copy = DAG.getCopyToReg(Chain, ARM::R0, Op, SDValue());
if (DAG.getMachineFunction().getRegInfo().liveout_empty())
DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0);
break;
case 5:
- Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDOperand());
+ Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDValue());
Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1));
// If we haven't noted the R0+R1 are live out, do so now.
if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
@@ -686,7 +686,7 @@
}
break;
case 9: // i128 -> 4 regs
- Copy = DAG.getCopyToReg(Chain, ARM::R3, Op.getOperand(7), SDOperand());
+ Copy = DAG.getCopyToReg(Chain, ARM::R3, Op.getOperand(7), SDValue());
Copy = DAG.getCopyToReg(Copy , ARM::R2, Op.getOperand(5), Copy.getValue(1));
Copy = DAG.getCopyToReg(Copy , ARM::R1, Op.getOperand(3), Copy.getValue(1));
Copy = DAG.getCopyToReg(Copy , ARM::R0, Op.getOperand(1), Copy.getValue(1));
@@ -711,10 +711,10 @@
// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
// be used to form addressing mode. These wrapped nodes will be selected
// into MOVi.
-static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
+static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
MVT PtrVT = Op.getValueType();
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
- SDOperand Res;
+ SDValue Res;
if (CP->isMachineConstantPoolEntry())
Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
CP->getAlignment());
@@ -725,7 +725,7 @@
}
// Lower ISD::GlobalTLSAddress using the "general dynamic" model
-SDOperand
+SDValue
ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
SelectionDAG &DAG) {
MVT PtrVT = getPointerTy();
@@ -733,12 +733,12 @@
ARMConstantPoolValue *CPV =
new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
PCAdj, "tlsgd", true);
- SDOperand Argument = DAG.getTargetConstantPool(CPV, PtrVT, 2);
+ SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 2);
Argument = DAG.getNode(ARMISD::Wrapper, MVT::i32, Argument);
Argument = DAG.getLoad(PtrVT, DAG.getEntryNode(), Argument, NULL, 0);
- SDOperand Chain = Argument.getValue(1);
+ SDValue Chain = Argument.getValue(1);
- SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
+ SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
Argument = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Argument, PICLabel);
// call __tls_get_addr.
@@ -747,7 +747,7 @@
Entry.Node = Argument;
Entry.Ty = (const Type *) Type::Int32Ty;
Args.push_back(Entry);
- std::pair<SDOperand, SDOperand> CallResult =
+ std::pair<SDValue, SDValue> CallResult =
LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false, false,
CallingConv::C, false,
DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG);
@@ -756,15 +756,15 @@
// Lower ISD::GlobalTLSAddress using the "initial exec" or
// "local exec" model.
-SDOperand
+SDValue
ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
SelectionDAG &DAG) {
GlobalValue *GV = GA->getGlobal();
- SDOperand Offset;
- SDOperand Chain = DAG.getEntryNode();
+ SDValue Offset;
+ SDValue Chain = DAG.getEntryNode();
MVT PtrVT = getPointerTy();
// Get the Thread Pointer
- SDOperand ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, PtrVT);
+ SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, PtrVT);
if (GV->isDeclaration()){
// initial exec model
@@ -777,7 +777,7 @@
Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0);
Chain = Offset.getValue(1);
- SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
+ SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
Offset = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Offset, PICLabel);
Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0);
@@ -795,8 +795,8 @@
return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset);
}
-SDOperand
-ARMTargetLowering::LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) {
+SDValue
+ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
// TODO: implement the "local dynamic" model
assert(Subtarget->isTargetELF() &&
"TLS not implemented for non-ELF targets");
@@ -809,7 +809,7 @@
return LowerToTLSExecModels(GA, DAG);
}
-SDOperand ARMTargetLowering::LowerGlobalAddressELF(SDOperand Op,
+SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
SelectionDAG &DAG) {
MVT PtrVT = getPointerTy();
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
@@ -818,17 +818,17 @@
bool UseGOTOFF = GV->hasInternalLinkage() || GV->hasHiddenVisibility();
ARMConstantPoolValue *CPV =
new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT");
- SDOperand CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
+ SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
- SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
- SDOperand Chain = Result.getValue(1);
- SDOperand GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PtrVT);
+ SDValue Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
+ SDValue Chain = Result.getValue(1);
+ SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PtrVT);
Result = DAG.getNode(ISD::ADD, PtrVT, Result, GOT);
if (!UseGOTOFF)
Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0);
return Result;
} else {
- SDOperand CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
+ SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
return DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
}
@@ -842,13 +842,13 @@
(GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode()));
}
-SDOperand ARMTargetLowering::LowerGlobalAddressDarwin(SDOperand Op,
+SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
SelectionDAG &DAG) {
MVT PtrVT = getPointerTy();
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
Reloc::Model RelocM = getTargetMachine().getRelocationModel();
bool IsIndirect = GVIsIndirectSymbol(GV, RelocM);
- SDOperand CPAddr;
+ SDValue CPAddr;
if (RelocM == Reloc::Static)
CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
else {
@@ -862,11 +862,11 @@
}
CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
- SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
- SDOperand Chain = Result.getValue(1);
+ SDValue Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
+ SDValue Chain = Result.getValue(1);
if (RelocM == Reloc::PIC_) {
- SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
+ SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
Result = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel);
}
if (IsIndirect)
@@ -875,7 +875,7 @@
return Result;
}
-SDOperand ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDOperand Op,
+SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
SelectionDAG &DAG){
assert(Subtarget->isTargetELF() &&
"GLOBAL OFFSET TABLE not implemented for non-ELF targets");
@@ -884,40 +884,40 @@
ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_",
ARMPCLabelIndex,
ARMCP::CPValue, PCAdj);
- SDOperand CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
+ SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
- SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
- SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
+ SDValue Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
+ SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
return DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel);
}
-static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
+static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
switch (IntNo) {
- default: return SDOperand(); // Don't custom lower most intrinsics.
+ default: return SDValue(); // Don't custom lower most intrinsics.
case Intrinsic::arm_thread_pointer:
return DAG.getNode(ARMISD::THREAD_POINTER, PtrVT);
}
}
-static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
+static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
unsigned VarArgsFrameIndex) {
// vastart just stores the address of the VarArgsFrameIndex slot into the
// memory location argument.
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
- SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
+ SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0);
}
-static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG,
+static SDValue LowerFORMAL_ARGUMENT(SDValue Op, SelectionDAG &DAG,
unsigned ArgNo, unsigned &NumGPRs,
unsigned &ArgOffset) {
MachineFunction &MF = DAG.getMachineFunction();
MVT ObjectVT = Op.getValue(ArgNo).getValueType();
- SDOperand Root = Op.getOperand(0);
- std::vector<SDOperand> ArgValues;
+ SDValue Root = Op.getOperand(0);
+ std::vector<SDValue> ArgValues;
MachineRegisterInfo &RegInfo = MF.getRegInfo();
static const unsigned GPRArgRegs[] = {
@@ -935,7 +935,7 @@
NumGPRs += GPRPad;
ArgOffset += StackPad;
- SDOperand ArgValue;
+ SDValue ArgValue;
if (ObjGPRs == 1) {
unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
@@ -949,7 +949,7 @@
VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
RegInfo.addLiveIn(GPRArgRegs[NumGPRs+1], VReg);
- SDOperand ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32);
+ SDValue ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32);
assert(ObjectVT != MVT::i64 && "i64 should already be lowered");
ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2);
@@ -959,11 +959,11 @@
if (ObjSize) {
MachineFrameInfo *MFI = MF.getFrameInfo();
int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
- SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
+ SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
if (ObjGPRs == 0)
ArgValue = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
else {
- SDOperand ArgValue2 = DAG.getLoad(MVT::i32, Root, FIN, NULL, 0);
+ SDValue ArgValue2 = DAG.getLoad(MVT::i32, Root, FIN, NULL, 0);
assert(ObjectVT != MVT::i64 && "i64 should already be lowered");
ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2);
}
@@ -974,10 +974,10 @@
return ArgValue;
}
-SDOperand
-ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
- std::vector<SDOperand> ArgValues;
- SDOperand Root = Op.getOperand(0);
+SDValue
+ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
+ std::vector<SDValue> ArgValues;
+ SDValue Root = Op.getOperand(0);
unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
unsigned NumGPRs = 0; // GPRs used for parameter passing.
@@ -1006,14 +1006,14 @@
AFI->setVarArgsRegSaveSize(VARegSaveSize);
VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset +
VARegSaveSize - VARegSize);
- SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
+ SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
- SmallVector<SDOperand, 4> MemOps;
+ SmallVector<SDValue, 4> MemOps;
for (; NumGPRs < 4; ++NumGPRs) {
unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
- SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32);
- SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
+ SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::i32);
+ SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
MemOps.push_back(Store);
FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
DAG.getConstant(4, getPointerTy()));
@@ -1034,13 +1034,13 @@
}
/// isFloatingPointZero - Return true if this is +0.0.
-static bool isFloatingPointZero(SDOperand Op) {
+static bool isFloatingPointZero(SDValue Op) {
if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
return CFP->getValueAPF().isPosZero();
else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
// Maybe this has already been legalized into the constant pool?
if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
- SDOperand WrapperOp = Op.getOperand(1).getOperand(0);
+ SDValue WrapperOp = Op.getOperand(1).getOperand(0);
if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
return CFP->getValueAPF().isPosZero();
@@ -1056,8 +1056,8 @@
/// Returns appropriate ARM CMP (cmp) and corresponding condition code for
/// the given operands.
-static SDOperand getARMCmp(SDOperand LHS, SDOperand RHS, ISD::CondCode CC,
- SDOperand &ARMCC, SelectionDAG &DAG, bool isThumb) {
+static SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
+ SDValue &ARMCC, SelectionDAG &DAG, bool isThumb) {
if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.Val)) {
unsigned C = RHSC->getValue();
if (!isLegalCmpImmediate(C, isThumb)) {
@@ -1115,8 +1115,8 @@
}
/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
-static SDOperand getVFPCmp(SDOperand LHS, SDOperand RHS, SelectionDAG &DAG) {
- SDOperand Cmp;
+static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG) {
+ SDValue Cmp;
if (!isFloatingPointZero(RHS))
Cmp = DAG.getNode(ARMISD::CMPFP, MVT::Flag, LHS, RHS);
else
@@ -1124,19 +1124,19 @@
return DAG.getNode(ARMISD::FMSTAT, MVT::Flag, Cmp);
}
-static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG,
+static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
const ARMSubtarget *ST) {
MVT VT = Op.getValueType();
- SDOperand LHS = Op.getOperand(0);
- SDOperand RHS = Op.getOperand(1);
+ SDValue LHS = Op.getOperand(0);
+ SDValue RHS = Op.getOperand(1);
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
- SDOperand TrueVal = Op.getOperand(2);
- SDOperand FalseVal = Op.getOperand(3);
+ SDValue TrueVal = Op.getOperand(2);
+ SDValue FalseVal = Op.getOperand(3);
if (LHS.getValueType() == MVT::i32) {
- SDOperand ARMCC;
- SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
- SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb());
+ SDValue ARMCC;
+ SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
+ SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb());
return DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, ARMCC, CCR, Cmp);
}
@@ -1144,32 +1144,32 @@
if (FPCCToARMCC(CC, CondCode, CondCode2))
std::swap(TrueVal, FalseVal);
- SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32);
- SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
- SDOperand Cmp = getVFPCmp(LHS, RHS, DAG);
- SDOperand Result = DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal,
+ SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
+ SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
+ SDValue Cmp = getVFPCmp(LHS, RHS, DAG);
+ SDValue Result = DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal,
ARMCC, CCR, Cmp);
if (CondCode2 != ARMCC::AL) {
- SDOperand ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
+ SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
// FIXME: Needs another CMP because flag can have but one use.
- SDOperand Cmp2 = getVFPCmp(LHS, RHS, DAG);
+ SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG);
Result = DAG.getNode(ARMISD::CMOV, VT, Result, TrueVal, ARMCC2, CCR, Cmp2);
}
return Result;
}
-static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG,
+static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
const ARMSubtarget *ST) {
- SDOperand Chain = Op.getOperand(0);
+ SDValue Chain = Op.getOperand(0);
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
- SDOperand LHS = Op.getOperand(2);
- SDOperand RHS = Op.getOperand(3);
- SDOperand Dest = Op.getOperand(4);
+ SDValue LHS = Op.getOperand(2);
+ SDValue RHS = Op.getOperand(3);
+ SDValue Dest = Op.getOperand(4);
if (LHS.getValueType() == MVT::i32) {
- SDOperand ARMCC;
- SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
- SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb());
+ SDValue ARMCC;
+ SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
+ SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb());
return DAG.getNode(ARMISD::BRCOND, MVT::Other, Chain, Dest, ARMCC, CCR,Cmp);
}
@@ -1179,33 +1179,33 @@
// Swap the LHS/RHS of the comparison if needed.
std::swap(LHS, RHS);
- SDOperand Cmp = getVFPCmp(LHS, RHS, DAG);
- SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32);
- SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
+ SDValue Cmp = getVFPCmp(LHS, RHS, DAG);
+ SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
+ SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
- SDOperand Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
- SDOperand Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5);
+ SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
+ SDValue Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5);
if (CondCode2 != ARMCC::AL) {
ARMCC = DAG.getConstant(CondCode2, MVT::i32);
- SDOperand Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
+ SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5);
}
return Res;
}
-SDOperand ARMTargetLowering::LowerBR_JT(SDOperand Op, SelectionDAG &DAG) {
- SDOperand Chain = Op.getOperand(0);
- SDOperand Table = Op.getOperand(1);
- SDOperand Index = Op.getOperand(2);
+SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) {
+ SDValue Chain = Op.getOperand(0);
+ SDValue Table = Op.getOperand(1);
+ SDValue Index = Op.getOperand(2);
MVT PTy = getPointerTy();
JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
- SDOperand UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
- SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
+ SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
+ SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
Table = DAG.getNode(ARMISD::WrapperJT, MVT::i32, JTI, UId);
Index = DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(4, PTy));
- SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
+ SDValue Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
Addr = DAG.getLoad(isPIC ? (MVT)MVT::i32 : PTy,
Chain, Addr, NULL, 0);
@@ -1215,14 +1215,14 @@
return DAG.getNode(ARMISD::BR_JT, MVT::Other, Chain, Addr, JTI, UId);
}
-static SDOperand LowerFP_TO_INT(SDOperand Op, SelectionDAG &DAG) {
+static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
unsigned Opc =
Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI;
Op = DAG.getNode(Opc, MVT::f32, Op.getOperand(0));
return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
}
-static SDOperand LowerINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
+static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
MVT VT = Op.getValueType();
unsigned Opc =
Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF;
@@ -1231,39 +1231,39 @@
return DAG.getNode(Opc, VT, Op);
}
-static SDOperand LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
+static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
// Implement fcopysign with a fabs and a conditional fneg.
- SDOperand Tmp0 = Op.getOperand(0);
- SDOperand Tmp1 = Op.getOperand(1);
+ SDValue Tmp0 = Op.getOperand(0);
+ SDValue Tmp1 = Op.getOperand(1);
MVT VT = Op.getValueType();
MVT SrcVT = Tmp1.getValueType();
- SDOperand AbsVal = DAG.getNode(ISD::FABS, VT, Tmp0);
- SDOperand Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG);
- SDOperand ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
- SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
+ SDValue AbsVal = DAG.getNode(ISD::FABS, VT, Tmp0);
+ SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG);
+ SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
+ SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
return DAG.getNode(ARMISD::CNEG, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
}
-SDOperand
+SDValue
ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG,
- SDOperand Chain,
- SDOperand Dst, SDOperand Src,
- SDOperand Size, unsigned Align,
+ SDValue Chain,
+ SDValue Dst, SDValue Src,
+ SDValue Size, unsigned Align,
bool AlwaysInline,
const Value *DstSV, uint64_t DstSVOff,
const Value *SrcSV, uint64_t SrcSVOff){
// Do repeated 4-byte loads and stores. To be improved.
// This requires 4-byte alignment.
if ((Align & 3) != 0)
- return SDOperand();
+ return SDValue();
// This requires the copy size to be a constant, preferrably
// within a subtarget-specific limit.
ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
if (!ConstantSize)
- return SDOperand();
+ return SDValue();
uint64_t SizeVal = ConstantSize->getValue();
if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
- return SDOperand();
+ return SDValue();
unsigned BytesLeft = SizeVal & 3;
unsigned NumMemOps = SizeVal >> 2;
@@ -1272,8 +1272,8 @@
unsigned VTSize = 4;
unsigned i = 0;
const unsigned MAX_LOADS_IN_LDM = 6;
- SDOperand TFOps[MAX_LOADS_IN_LDM];
- SDOperand Loads[MAX_LOADS_IN_LDM];
+ SDValue TFOps[MAX_LOADS_IN_LDM];
+ SDValue Loads[MAX_LOADS_IN_LDM];
uint64_t SrcOff = 0, DstOff = 0;
// Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the
@@ -1357,8 +1357,8 @@
assert(N->getValueType(0) == MVT::i64 &&
N->getOperand(0).getValueType() == MVT::f64);
- SDOperand Op = N->getOperand(0);
- SDOperand Cvt = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32),
+ SDValue Op = N->getOperand(0);
+ SDValue Cvt = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32),
&Op, 1);
// Merge the pieces into a single i64 value.
@@ -1379,9 +1379,9 @@
if (ST->isThumb()) return 0;
// Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
- SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0),
+ SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0),
DAG.getConstant(0, MVT::i32));
- SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0),
+ SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0),
DAG.getConstant(1, MVT::i32));
// First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
@@ -1397,7 +1397,7 @@
}
-SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
+SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
switch (Op.getOpcode()) {
default: assert(0 && "Don't know how to custom lower this!"); abort();
case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
@@ -1424,11 +1424,11 @@
// FIXME: Remove these when LegalizeDAGTypes lands.
- case ISD::BIT_CONVERT: return SDOperand(ExpandBIT_CONVERT(Op.Val, DAG), 0);
+ case ISD::BIT_CONVERT: return SDValue(ExpandBIT_CONVERT(Op.Val, DAG), 0);
case ISD::SRL:
- case ISD::SRA: return SDOperand(ExpandSRx(Op.Val, DAG,Subtarget),0);
+ case ISD::SRA: return SDValue(ExpandSRx(Op.Val, DAG,Subtarget),0);
}
- return SDOperand();
+ return SDValue();
}
@@ -1516,23 +1516,23 @@
//===----------------------------------------------------------------------===//
/// PerformFMRRDCombine - Target-specific dag combine xforms for ARMISD::FMRRD.
-static SDOperand PerformFMRRDCombine(SDNode *N,
+static SDValue PerformFMRRDCombine(SDNode *N,
TargetLowering::DAGCombinerInfo &DCI) {
// fmrrd(fmdrr x, y) -> x,y
- SDOperand InDouble = N->getOperand(0);
+ SDValue InDouble = N->getOperand(0);
if (InDouble.getOpcode() == ARMISD::FMDRR)
return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
- return SDOperand();
+ return SDValue();
}
-SDOperand ARMTargetLowering::PerformDAGCombine(SDNode *N,
+SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
DAGCombinerInfo &DCI) const {
switch (N->getOpcode()) {
default: break;
case ARMISD::FMRRD: return PerformFMRRDCombine(N, DCI);
}
- return SDOperand();
+ return SDValue();
}
@@ -1654,8 +1654,8 @@
static bool getIndexedAddressParts(SDNode *Ptr, MVT VT,
- bool isSEXTLoad, SDOperand &Base,
- SDOperand &Offset, bool &isInc,
+ bool isSEXTLoad, SDValue &Base,
+ SDValue &Offset, bool &isInc,
SelectionDAG &DAG) {
if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
return false;
@@ -1713,15 +1713,15 @@
/// offset pointer and addressing mode by reference if the node's address
/// can be legally represented as pre-indexed load / store address.
bool
-ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
- SDOperand &Offset,
+ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
+ SDValue &Offset,
ISD::MemIndexedMode &AM,
SelectionDAG &DAG) {
if (Subtarget->isThumb())
return false;
MVT VT;
- SDOperand Ptr;
+ SDValue Ptr;
bool isSEXTLoad = false;
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
Ptr = LD->getBasePtr();
@@ -1747,15 +1747,15 @@
/// offset pointer and addressing mode by reference if this node can be
/// combined with a load / store to form a post-indexed load / store.
bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
- SDOperand &Base,
- SDOperand &Offset,
+ SDValue &Base,
+ SDValue &Offset,
ISD::MemIndexedMode &AM,
SelectionDAG &DAG) {
if (Subtarget->isThumb())
return false;
MVT VT;
- SDOperand Ptr;
+ SDValue Ptr;
bool isSEXTLoad = false;
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
VT = LD->getMemoryVT();
@@ -1775,7 +1775,7 @@
return false;
}
-void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
+void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
const APInt &Mask,
APInt &KnownZero,
APInt &KnownOne,
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Sun Jul 27 16:46:04 2008
@@ -75,10 +75,10 @@
public:
explicit ARMTargetLowering(TargetMachine &TM);
- virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
+ virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
virtual SDNode *ReplaceNodeResults(SDNode *N, SelectionDAG &DAG);
- virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
+ virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
virtual const char *getTargetNodeName(unsigned Opcode) const;
@@ -92,8 +92,8 @@
/// getPreIndexedAddressParts - returns true by value, base pointer and
/// offset pointer and addressing mode by reference if the node's address
/// can be legally represented as pre-indexed load / store address.
- virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
- SDOperand &Offset,
+ virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
+ SDValue &Offset,
ISD::MemIndexedMode &AM,
SelectionDAG &DAG);
@@ -101,11 +101,11 @@
/// offset pointer and addressing mode by reference if this node can be
/// combined with a load / store to form a post-indexed load / store.
virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
- SDOperand &Base, SDOperand &Offset,
+ SDValue &Base, SDValue &Offset,
ISD::MemIndexedMode &AM,
SelectionDAG &DAG);
- virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
+ virtual void computeMaskedBitsForTargetNode(const SDValue Op,
const APInt &Mask,
APInt &KnownZero,
APInt &KnownOne,
@@ -132,22 +132,22 @@
///
unsigned ARMPCLabelIndex;
- SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerGlobalAddressDarwin(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerGlobalAddressELF(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
+ SDValue LowerCALL(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
SelectionDAG &DAG);
- SDOperand LowerToTLSExecModels(GlobalAddressSDNode *GA,
+ SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
SelectionDAG &DAG);
- SDOperand LowerGLOBAL_OFFSET_TABLE(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerBR_JT(SDOperand Op, SelectionDAG &DAG);
-
- SDOperand EmitTargetCodeForMemcpy(SelectionDAG &DAG,
- SDOperand Chain,
- SDOperand Dst, SDOperand Src,
- SDOperand Size, unsigned Align,
+ SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG);
+
+ SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG,
+ SDValue Chain,
+ SDValue Dst, SDValue Src,
+ SDValue Size, unsigned Align,
bool AlwaysInline,
const Value *DstSV, uint64_t DstSVOff,
const Value *SrcSV, uint64_t SrcSVOff);
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Sun Jul 27 16:46:04 2008
@@ -152,7 +152,7 @@
// sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
def sext_16_node : PatLeaf<(i32 GPR:$a), [{
- return CurDAG->ComputeNumSignBits(SDOperand(N,0)) >= 17;
+ return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
}]>;
Modified: llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp Sun Jul 27 16:46:04 2008
@@ -65,7 +65,7 @@
/// that the bits 1-7 of LHS are already zero. If LHS is non-null, we are
/// in checking mode. If LHS is null, we assume that the mask has already
/// been validated before.
- uint64_t get_zapImm(SDOperand LHS, uint64_t Constant) {
+ uint64_t get_zapImm(SDValue LHS, uint64_t Constant) {
uint64_t BitsToCheck = 0;
unsigned Result = 0;
for (unsigned i = 0; i != 8; ++i) {
@@ -132,15 +132,15 @@
return (x - y) == r;
}
- static bool isFPZ(SDOperand N) {
+ static bool isFPZ(SDValue N) {
ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
return (CN && (CN->getValueAPF().isZero()));
}
- static bool isFPZn(SDOperand N) {
+ static bool isFPZn(SDValue N) {
ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
return (CN && CN->getValueAPF().isNegZero());
}
- static bool isFPZp(SDOperand N) {
+ static bool isFPZp(SDValue N) {
ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
return (CN && CN->getValueAPF().isPosZero());
}
@@ -153,13 +153,13 @@
/// getI64Imm - Return a target constant with the specified value, of type
/// i64.
- inline SDOperand getI64Imm(int64_t Imm) {
+ inline SDValue getI64Imm(int64_t Imm) {
return CurDAG->getTargetConstant(Imm, MVT::i64);
}
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
- SDNode *Select(SDOperand Op);
+ SDNode *Select(SDValue Op);
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
@@ -171,11 +171,11 @@
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
- virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
+ virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
char ConstraintCode,
- std::vector<SDOperand> &OutOps,
+ std::vector<SDValue> &OutOps,
SelectionDAG &DAG) {
- SDOperand Op0;
+ SDValue Op0;
switch (ConstraintCode) {
default: return true;
case 'm': // memory
@@ -192,9 +192,9 @@
#include "AlphaGenDAGISel.inc"
private:
- SDOperand getGlobalBaseReg();
- SDOperand getGlobalRetAddr();
- void SelectCALL(SDOperand Op);
+ SDValue getGlobalBaseReg();
+ SDValue getGlobalRetAddr();
+ void SelectCALL(SDValue Op);
};
}
@@ -202,7 +202,7 @@
/// getGlobalBaseReg - Output the instructions required to put the
/// GOT address into a register.
///
-SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() {
+SDValue AlphaDAGToDAGISel::getGlobalBaseReg() {
unsigned GP = 0;
for(MachineRegisterInfo::livein_iterator ii = RegInfo->livein_begin(),
ee = RegInfo->livein_end(); ii != ee; ++ii)
@@ -217,7 +217,7 @@
/// getRASaveReg - Grab the return address
///
-SDOperand AlphaDAGToDAGISel::getGlobalRetAddr() {
+SDValue AlphaDAGToDAGISel::getGlobalRetAddr() {
unsigned RA = 0;
for(MachineRegisterInfo::livein_iterator ii = RegInfo->livein_begin(),
ee = RegInfo->livein_end(); ii != ee; ++ii)
@@ -242,7 +242,7 @@
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
-SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
+SDNode *AlphaDAGToDAGISel::Select(SDValue Op) {
SDNode *N = Op.Val;
if (N->isMachineOpcode()) {
return NULL; // Already selected.
@@ -261,26 +261,26 @@
getI64Imm(0));
}
case ISD::GLOBAL_OFFSET_TABLE: {
- SDOperand Result = getGlobalBaseReg();
+ SDValue Result = getGlobalBaseReg();
ReplaceUses(Op, Result);
return NULL;
}
case AlphaISD::GlobalRetAddr: {
- SDOperand Result = getGlobalRetAddr();
+ SDValue Result = getGlobalRetAddr();
ReplaceUses(Op, Result);
return NULL;
}
case AlphaISD::DivCall: {
- SDOperand Chain = CurDAG->getEntryNode();
- SDOperand N0 = Op.getOperand(0);
- SDOperand N1 = Op.getOperand(1);
- SDOperand N2 = Op.getOperand(2);
+ SDValue Chain = CurDAG->getEntryNode();
+ SDValue N0 = Op.getOperand(0);
+ SDValue N1 = Op.getOperand(1);
+ SDValue N2 = Op.getOperand(2);
AddToISelQueue(N0);
AddToISelQueue(N1);
AddToISelQueue(N2);
Chain = CurDAG->getCopyToReg(Chain, Alpha::R24, N1,
- SDOperand(0,0));
+ SDValue(0,0));
Chain = CurDAG->getCopyToReg(Chain, Alpha::R25, N2,
Chain.getValue(1));
Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, N0,
@@ -289,12 +289,12 @@
CurDAG->getTargetNode(Alpha::JSRs, MVT::Other, MVT::Flag,
Chain, Chain.getValue(1));
Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64,
- SDOperand(CNode, 1));
+ SDValue(CNode, 1));
return CurDAG->SelectNodeTo(N, Alpha::BISr, MVT::i64, Chain, Chain);
}
case ISD::READCYCLECOUNTER: {
- SDOperand Chain = N->getOperand(0);
+ SDValue Chain = N->getOperand(0);
AddToISelQueue(Chain); //Select chain
return CurDAG->getTargetNode(Alpha::RPCC, MVT::i64, MVT::Other,
Chain);
@@ -304,7 +304,7 @@
uint64_t uval = cast<ConstantSDNode>(N)->getValue();
if (uval == 0) {
- SDOperand Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
+ SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
Alpha::R31, MVT::i64);
ReplaceUses(Op, Result);
return NULL;
@@ -321,11 +321,11 @@
break; //(zext (LDAH (LDA)))
//Else use the constant pool
ConstantInt *C = ConstantInt::get(Type::Int64Ty, uval);
- SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
+ SDValue CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI,
getGlobalBaseReg());
return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other,
- CPI, SDOperand(Tmp, 0), CurDAG->getEntryNode());
+ CPI, SDValue(Tmp, 0), CurDAG->getEntryNode());
}
case ISD::TargetConstantFP: {
ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
@@ -371,13 +371,13 @@
case ISD::SETUO:
Opc = Alpha::CMPTUN; break;
};
- SDOperand tmp1 = N->getOperand(rev?1:0);
- SDOperand tmp2 = N->getOperand(rev?0:1);
+ SDValue tmp1 = N->getOperand(rev?1:0);
+ SDValue tmp2 = N->getOperand(rev?0:1);
AddToISelQueue(tmp1);
AddToISelQueue(tmp2);
SDNode *cmp = CurDAG->getTargetNode(Opc, MVT::f64, tmp1, tmp2);
if (inv)
- cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, SDOperand(cmp, 0),
+ cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, SDValue(cmp, 0),
CurDAG->getRegister(Alpha::F31, MVT::f64));
switch(CC) {
case ISD::SETUEQ: case ISD::SETULT: case ISD::SETULE:
@@ -386,16 +386,16 @@
SDNode* cmp2 = CurDAG->getTargetNode(Alpha::CMPTUN, MVT::f64,
tmp1, tmp2);
cmp = CurDAG->getTargetNode(Alpha::ADDT, MVT::f64,
- SDOperand(cmp2, 0), SDOperand(cmp, 0));
+ SDValue(cmp2, 0), SDValue(cmp, 0));
break;
}
default: break;
}
- SDNode* LD = CurDAG->getTargetNode(Alpha::FTOIT, MVT::i64, SDOperand(cmp, 0));
+ SDNode* LD = CurDAG->getTargetNode(Alpha::FTOIT, MVT::i64, SDValue(cmp, 0));
return CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64,
CurDAG->getRegister(Alpha::R31, MVT::i64),
- SDOperand(LD,0));
+ SDValue(LD,0));
}
break;
@@ -408,16 +408,16 @@
// so that things like this can be caught in fall though code
//move int to fp
bool isDouble = N->getValueType(0) == MVT::f64;
- SDOperand cond = N->getOperand(0);
- SDOperand TV = N->getOperand(1);
- SDOperand FV = N->getOperand(2);
+ SDValue cond = N->getOperand(0);
+ SDValue TV = N->getOperand(1);
+ SDValue FV = N->getOperand(2);
AddToISelQueue(cond);
AddToISelQueue(TV);
AddToISelQueue(FV);
SDNode* LD = CurDAG->getTargetNode(Alpha::ITOFT, MVT::f64, cond);
return CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES,
- MVT::f64, FV, TV, SDOperand(LD,0));
+ MVT::f64, FV, TV, SDValue(LD,0));
}
break;
@@ -442,8 +442,8 @@
if (get_zapImm(mask)) {
AddToISelQueue(N->getOperand(0).getOperand(0));
- SDOperand Z =
- SDOperand(CurDAG->getTargetNode(Alpha::ZAPNOTi, MVT::i64,
+ SDValue Z =
+ SDValue(CurDAG->getTargetNode(Alpha::ZAPNOTi, MVT::i64,
N->getOperand(0).getOperand(0),
getI64Imm(get_zapImm(mask))), 0);
return CurDAG->getTargetNode(Alpha::SRLr, MVT::i64, Z,
@@ -458,16 +458,16 @@
return SelectCode(Op);
}
-void AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
+void AlphaDAGToDAGISel::SelectCALL(SDValue Op) {
//TODO: add flag stuff to prevent nondeturministic breakage!
SDNode *N = Op.Val;
- SDOperand Chain = N->getOperand(0);
- SDOperand Addr = N->getOperand(1);
- SDOperand InFlag(0,0); // Null incoming flag value.
+ SDValue Chain = N->getOperand(0);
+ SDValue Addr = N->getOperand(1);
+ SDValue InFlag(0,0); // Null incoming flag value.
AddToISelQueue(Chain);
- std::vector<SDOperand> CallOperands;
+ std::vector<SDValue> CallOperands;
std::vector<MVT> TypeOperands;
//grab the arguments
@@ -494,10 +494,10 @@
} else
assert(0 && "Unknown operand");
- SDOperand Ops[] = { CallOperands[i], getI64Imm((i - 6) * 8),
+ SDValue Ops[] = { CallOperands[i], getI64Imm((i - 6) * 8),
CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64),
Chain };
- Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, Ops, 4), 0);
+ Chain = SDValue(CurDAG->getTargetNode(Opc, MVT::Other, Ops, 4), 0);
}
for (int i = 0; i < std::min(6, count); ++i) {
if (TypeOperands[i].isInteger()) {
@@ -513,21 +513,21 @@
// Finally, once everything is in registers to pass to the call, emit the
// call itself.
if (Addr.getOpcode() == AlphaISD::GPRelLo) {
- SDOperand GOT = getGlobalBaseReg();
+ SDValue GOT = getGlobalBaseReg();
Chain = CurDAG->getCopyToReg(Chain, Alpha::R29, GOT, InFlag);
InFlag = Chain.getValue(1);
- Chain = SDOperand(CurDAG->getTargetNode(Alpha::BSR, MVT::Other, MVT::Flag,
+ Chain = SDValue(CurDAG->getTargetNode(Alpha::BSR, MVT::Other, MVT::Flag,
Addr.getOperand(0), Chain, InFlag), 0);
} else {
AddToISelQueue(Addr);
Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr, InFlag);
InFlag = Chain.getValue(1);
- Chain = SDOperand(CurDAG->getTargetNode(Alpha::JSR, MVT::Other, MVT::Flag,
+ Chain = SDValue(CurDAG->getTargetNode(Alpha::JSR, MVT::Other, MVT::Flag,
Chain, InFlag), 0);
}
InFlag = Chain.getValue(1);
- std::vector<SDOperand> CallResults;
+ std::vector<SDValue> CallResults;
switch (N->getValueType(0).getSimpleVT()) {
default: assert(0 && "Unexpected ret value!");
Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Sun Jul 27 16:46:04 2008
@@ -146,7 +146,7 @@
computeRegisterProperties();
}
-MVT AlphaTargetLowering::getSetCCResultType(const SDOperand &) const {
+MVT AlphaTargetLowering::getSetCCResultType(const SDValue &) const {
return MVT::i64;
}
@@ -168,15 +168,15 @@
}
}
-static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
+static SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
MVT PtrVT = Op.getValueType();
JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
- SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
- SDOperand Zero = DAG.getConstant(0, PtrVT);
+ SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
+ SDValue Zero = DAG.getConstant(0, PtrVT);
- SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, JTI,
+ SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, JTI,
DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
- SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, JTI, Hi);
+ SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, JTI, Hi);
return Lo;
}
@@ -199,13 +199,13 @@
// //#define GP $29
// //#define SP $30
-static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
+static SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG,
int &VarArgsBase,
int &VarArgsOffset) {
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo();
- std::vector<SDOperand> ArgValues;
- SDOperand Root = Op.getOperand(0);
+ std::vector<SDValue> ArgValues;
+ SDValue Root = Op.getOperand(0);
AddLiveIn(MF, Alpha::R29, &Alpha::GPRCRegClass); //GP
AddLiveIn(MF, Alpha::R26, &Alpha::GPRCRegClass); //RA
@@ -216,9 +216,9 @@
Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
- SDOperand argt;
+ SDValue argt;
MVT ObjectVT = Op.getValue(ArgNo).getValueType();
- SDOperand ArgVal;
+ SDValue ArgVal;
if (ArgNo < 6) {
switch (ObjectVT.getSimpleVT()) {
@@ -246,7 +246,7 @@
// Create the SelectionDAG nodes corresponding to a load
//from this parameter
- SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
+ SDValue FIN = DAG.getFrameIndex(FI, MVT::i64);
ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
}
ArgValues.push_back(ArgVal);
@@ -256,14 +256,14 @@
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
if (isVarArg) {
VarArgsOffset = (Op.Val->getNumValues()-1) * 8;
- std::vector<SDOperand> LS;
+ std::vector<SDValue> LS;
for (int i = 0; i < 6; ++i) {
if (TargetRegisterInfo::isPhysicalRegister(args_int[i]))
args_int[i] = AddLiveIn(MF, args_int[i], &Alpha::GPRCRegClass);
- SDOperand argt = DAG.getCopyFromReg(Root, args_int[i], MVT::i64);
+ SDValue argt = DAG.getCopyFromReg(Root, args_int[i], MVT::i64);
int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
if (i == 0) VarArgsBase = FI;
- SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64);
+ SDValue SDFI = DAG.getFrameIndex(FI, MVT::i64);
LS.push_back(DAG.getStore(Root, argt, SDFI, NULL, 0));
if (TargetRegisterInfo::isPhysicalRegister(args_float[i]))
@@ -285,18 +285,18 @@
ArgValues.size());
}
-static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
- SDOperand Copy = DAG.getCopyToReg(Op.getOperand(0), Alpha::R26,
+static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) {
+ SDValue Copy = DAG.getCopyToReg(Op.getOperand(0), Alpha::R26,
DAG.getNode(AlphaISD::GlobalRetAddr,
MVT::i64),
- SDOperand());
+ SDValue());
switch (Op.getNumOperands()) {
default:
assert(0 && "Do not know how to return this many arguments!");
abort();
case 1:
break;
- //return SDOperand(); // ret void is legal
+ //return SDValue(); // ret void is legal
case 3: {
MVT ArgVT = Op.getOperand(1).getValueType();
unsigned ArgReg;
@@ -315,11 +315,11 @@
return DAG.getNode(AlphaISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
}
-std::pair<SDOperand, SDOperand>
-AlphaTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
+std::pair<SDValue, SDValue>
+AlphaTargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
bool RetSExt, bool RetZExt, bool isVarArg,
unsigned CallingConv, bool isTailCall,
- SDOperand Callee, ArgListTy &Args,
+ SDValue Callee, ArgListTy &Args,
SelectionDAG &DAG) {
int NumBytes = 0;
if (Args.size() > 6)
@@ -327,7 +327,7 @@
Chain = DAG.getCALLSEQ_START(Chain,
DAG.getConstant(NumBytes, getPointerTy()));
- std::vector<SDOperand> args_to_use;
+ std::vector<SDValue> args_to_use;
for (unsigned i = 0, e = Args.size(); i != e; ++i)
{
switch (getValueType(Args[i].Ty).getSimpleVT()) {
@@ -363,17 +363,17 @@
RetVals.push_back(ActualRetTyVT);
RetVals.push_back(MVT::Other);
- std::vector<SDOperand> Ops;
+ std::vector<SDValue> Ops;
Ops.push_back(Chain);
Ops.push_back(Callee);
Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end());
- SDOperand TheCall = DAG.getNode(AlphaISD::CALL, RetVals, &Ops[0], Ops.size());
+ SDValue TheCall = DAG.getNode(AlphaISD::CALL, RetVals, &Ops[0], Ops.size());
Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
Chain = DAG.getCALLSEQ_END(Chain,
DAG.getConstant(NumBytes, getPointerTy()),
DAG.getConstant(0, getPointerTy()),
- SDOperand());
- SDOperand RetVal = TheCall;
+ SDValue());
+ SDValue RetVal = TheCall;
if (RetTyVT != ActualRetTyVT) {
ISD::NodeType AssertKind = ISD::DELETED_NODE;
@@ -392,29 +392,29 @@
return std::make_pair(RetVal, Chain);
}
-void AlphaTargetLowering::LowerVAARG(SDNode *N, SDOperand &Chain,
- SDOperand &DataPtr, SelectionDAG &DAG) {
+void AlphaTargetLowering::LowerVAARG(SDNode *N, SDValue &Chain,
+ SDValue &DataPtr, SelectionDAG &DAG) {
Chain = N->getOperand(0);
- SDOperand VAListP = N->getOperand(1);
+ SDValue VAListP = N->getOperand(1);
const Value *VAListS = cast<SrcValueSDNode>(N->getOperand(2))->getValue();
- SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS, 0);
- SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
+ SDValue Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS, 0);
+ SDValue Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
DAG.getConstant(8, MVT::i64));
- SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1),
+ SDValue Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1),
Tmp, NULL, 0, MVT::i32);
DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset);
if (N->getValueType(0).isFloatingPoint())
{
//if fp && Offset < 6*8, then subtract 6*8 from DataPtr
- SDOperand FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr,
+ SDValue FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr,
DAG.getConstant(8*6, MVT::i64));
- SDOperand CC = DAG.getSetCC(MVT::i64, Offset,
+ SDValue CC = DAG.getSetCC(MVT::i64, Offset,
DAG.getConstant(8*6, MVT::i64), ISD::SETLT);
DataPtr = DAG.getNode(ISD::SELECT, MVT::i64, CC, FPDataPtr, DataPtr);
}
- SDOperand NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset,
+ SDValue NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset,
DAG.getConstant(8, MVT::i64));
Chain = DAG.getTruncStore(Offset.getValue(1), NewOffset, Tmp, NULL, 0,
MVT::i32);
@@ -422,7 +422,7 @@
/// LowerOperation - Provide custom lowering hooks for some operations.
///
-SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
+SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
switch (Op.getOpcode()) {
default: assert(0 && "Wasn't expecting to be able to lower this!");
case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG,
@@ -435,16 +435,16 @@
case ISD::SINT_TO_FP: {
assert(Op.getOperand(0).getValueType() == MVT::i64 &&
"Unhandled SINT_TO_FP type in custom expander!");
- SDOperand LD;
+ SDValue LD;
bool isDouble = Op.getValueType() == MVT::f64;
LD = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
- SDOperand FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_,
+ SDValue FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_,
isDouble?MVT::f64:MVT::f32, LD);
return FP;
}
case ISD::FP_TO_SINT: {
bool isDouble = Op.getOperand(0).getValueType() == MVT::f64;
- SDOperand src = Op.getOperand(0);
+ SDValue src = Op.getOperand(0);
if (!isDouble) //Promote
src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, src);
@@ -456,11 +456,11 @@
case ISD::ConstantPool: {
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
Constant *C = CP->getConstVal();
- SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment());
+ SDValue CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment());
- SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI,
+ SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI,
DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
- SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi);
+ SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi);
return Lo;
}
case ISD::GlobalTLSAddress:
@@ -468,13 +468,13 @@
case ISD::GlobalAddress: {
GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
GlobalValue *GV = GSDN->getGlobal();
- SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
+ SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
// if (!GV->hasWeakLinkage() && !GV->isDeclaration() && !GV->hasLinkOnceLinkage()) {
if (GV->hasInternalLinkage()) {
- SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA,
+ SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA,
DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
- SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);
+ SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);
return Lo;
} else
return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA,
@@ -492,7 +492,7 @@
//Expand only on constant case
if (Op.getOperand(1).getOpcode() == ISD::Constant) {
MVT VT = Op.Val->getValueType(0);
- SDOperand Tmp1 = Op.Val->getOpcode() == ISD::UREM ?
+ SDValue Tmp1 = Op.Val->getOpcode() == ISD::UREM ?
BuildUDIV(Op.Val, DAG, NULL) :
BuildSDIV(Op.Val, DAG, NULL);
Tmp1 = DAG.getNode(ISD::MUL, VT, Tmp1, Op.getOperand(1));
@@ -513,7 +513,7 @@
case ISD::UDIV: opstr = "__divqu"; break;
case ISD::SDIV: opstr = "__divq"; break;
}
- SDOperand Tmp1 = Op.getOperand(0),
+ SDValue Tmp1 = Op.getOperand(0),
Tmp2 = Op.getOperand(1),
Addr = DAG.getExternalSymbol(opstr, MVT::i64);
return DAG.getNode(AlphaISD::DivCall, MVT::i64, Addr, Tmp1, Tmp2);
@@ -521,10 +521,10 @@
break;
case ISD::VAARG: {
- SDOperand Chain, DataPtr;
+ SDValue Chain, DataPtr;
LowerVAARG(Op.Val, Chain, DataPtr, DAG);
- SDOperand Result;
+ SDValue Result;
if (Op.getValueType() == MVT::i32)
Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Chain, DataPtr,
NULL, 0, MVT::i32);
@@ -533,30 +533,30 @@
return Result;
}
case ISD::VACOPY: {
- SDOperand Chain = Op.getOperand(0);
- SDOperand DestP = Op.getOperand(1);
- SDOperand SrcP = Op.getOperand(2);
+ SDValue Chain = Op.getOperand(0);
+ SDValue DestP = Op.getOperand(1);
+ SDValue SrcP = Op.getOperand(2);
const Value *DestS = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
const Value *SrcS = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
- SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP, SrcS, 0);
- SDOperand Result = DAG.getStore(Val.getValue(1), Val, DestP, DestS, 0);
- SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP,
+ SDValue Val = DAG.getLoad(getPointerTy(), Chain, SrcP, SrcS, 0);
+ SDValue Result = DAG.getStore(Val.getValue(1), Val, DestP, DestS, 0);
+ SDValue NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP,
DAG.getConstant(8, MVT::i64));
Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP, NULL,0, MVT::i32);
- SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP,
+ SDValue NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP,
DAG.getConstant(8, MVT::i64));
return DAG.getTruncStore(Val.getValue(1), Val, NPD, NULL, 0, MVT::i32);
}
case ISD::VASTART: {
- SDOperand Chain = Op.getOperand(0);
- SDOperand VAListP = Op.getOperand(1);
+ SDValue Chain = Op.getOperand(0);
+ SDValue VAListP = Op.getOperand(1);
const Value *VAListS = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
// vastart stores the address of the VarArgsBase and VarArgsOffset
- SDOperand FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
- SDOperand S1 = DAG.getStore(Chain, FR, VAListP, VAListS, 0);
- SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
+ SDValue FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
+ SDValue S1 = DAG.getStore(Chain, FR, VAListP, VAListS, 0);
+ SDValue SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
DAG.getConstant(8, MVT::i64));
return DAG.getTruncStore(S1, DAG.getConstant(VarArgsOffset, MVT::i64),
SA2, NULL, 0, MVT::i32);
@@ -567,7 +567,7 @@
case ISD::FRAMEADDR: break;
}
- return SDOperand();
+ return SDValue();
}
SDNode *AlphaTargetLowering::ReplaceNodeResults(SDNode *N,
@@ -576,7 +576,7 @@
N->getOpcode() == ISD::VAARG &&
"Unknown node to custom promote!");
- SDOperand Chain, DataPtr;
+ SDValue Chain, DataPtr;
LowerVAARG(N, Chain, DataPtr, DAG);
return DAG.getLoad(N->getValueType(0), Chain, DataPtr, NULL, 0).Val;
}
Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.h?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.h (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.h Sun Jul 27 16:46:04 2008
@@ -67,11 +67,11 @@
explicit AlphaTargetLowering(TargetMachine &TM);
/// getSetCCResultType - Get the SETCC result ValueType
- virtual MVT getSetCCResultType(const SDOperand &) const;
+ virtual MVT getSetCCResultType(const SDValue &) const;
/// LowerOperation - Provide custom lowering hooks for some operations.
///
- virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
+ virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
virtual SDNode *ReplaceNodeResults(SDNode *N, SelectionDAG &DAG);
// Friendly names for dumps
@@ -79,9 +79,9 @@
/// LowerCallTo - This hook lowers an abstract call to a function into an
/// actual call.
- virtual std::pair<SDOperand, SDOperand>
- LowerCallTo(SDOperand Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
- bool isVarArg, unsigned CC, bool isTailCall, SDOperand Callee,
+ virtual std::pair<SDValue, SDValue>
+ LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
+ bool isVarArg, unsigned CC, bool isTailCall, SDValue Callee,
ArgListTy &Args, SelectionDAG &DAG);
ConstraintType getConstraintType(const std::string &Constraint) const;
@@ -97,7 +97,7 @@
private:
// Helpers for custom lowering.
- void LowerVAARG(SDNode *N, SDOperand &Chain, SDOperand &DataPtr,
+ void LowerVAARG(SDNode *N, SDValue &Chain, SDValue &DataPtr,
SelectionDAG &DAG);
};
Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td Sun Jul 27 16:46:04 2008
@@ -62,7 +62,7 @@
}]>;
def iZAPX : SDNodeXForm<and, [{ // get imm to ZAPi
ConstantSDNode *RHS = cast<ConstantSDNode>(N->getOperand(1));
- return getI64Imm(get_zapImm(SDOperand(), RHS->getValue()));
+ return getI64Imm(get_zapImm(SDValue(), RHS->getValue()));
}]>;
def nearP2X : SDNodeXForm<imm, [{
return getI64Imm(Log2_64(getNearPower2((uint64_t)N->getValue())));
Modified: llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp Sun Jul 27 16:46:04 2008
@@ -151,7 +151,7 @@
}
bool
- isHighLow(const SDOperand &Op)
+ isHighLow(const SDValue &Op)
{
return (Op.getOpcode() == SPUISD::IndirectAddr
&& ((Op.getOperand(0).getOpcode() == SPUISD::Hi
@@ -242,52 +242,52 @@
/// getI32Imm - Return a target constant with the specified value, of type
/// i32.
- inline SDOperand getI32Imm(uint32_t Imm) {
+ inline SDValue getI32Imm(uint32_t Imm) {
return CurDAG->getTargetConstant(Imm, MVT::i32);
}
/// getI64Imm - Return a target constant with the specified value, of type
/// i64.
- inline SDOperand getI64Imm(uint64_t Imm) {
+ inline SDValue getI64Imm(uint64_t Imm) {
return CurDAG->getTargetConstant(Imm, MVT::i64);
}
/// getSmallIPtrImm - Return a target constant of pointer type.
- inline SDOperand getSmallIPtrImm(unsigned Imm) {
+ inline SDValue getSmallIPtrImm(unsigned Imm) {
return CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
}
/// Select - Convert the specified operand from a target-independent to a
/// target-specific node if it hasn't already been changed.
- SDNode *Select(SDOperand Op);
+ SDNode *Select(SDValue Op);
//! Returns true if the address N is an A-form (local store) address
- bool SelectAFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
- SDOperand &Index);
+ bool SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base,
+ SDValue &Index);
//! D-form address predicate
- bool SelectDFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
- SDOperand &Index);
+ bool SelectDFormAddr(SDValue Op, SDValue N, SDValue &Base,
+ SDValue &Index);
/// Alternate D-form address using i7 offset predicate
- bool SelectDForm2Addr(SDOperand Op, SDOperand N, SDOperand &Disp,
- SDOperand &Base);
+ bool SelectDForm2Addr(SDValue Op, SDValue N, SDValue &Disp,
+ SDValue &Base);
/// D-form address selection workhorse
- bool DFormAddressPredicate(SDOperand Op, SDOperand N, SDOperand &Disp,
- SDOperand &Base, int minOffset, int maxOffset);
+ bool DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Disp,
+ SDValue &Base, int minOffset, int maxOffset);
//! Address predicate if N can be expressed as an indexed [r+r] operation.
- bool SelectXFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
- SDOperand &Index);
+ bool SelectXFormAddr(SDValue Op, SDValue N, SDValue &Base,
+ SDValue &Index);
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
- virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
+ virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
char ConstraintCode,
- std::vector<SDOperand> &OutOps,
+ std::vector<SDValue> &OutOps,
SelectionDAG &DAG) {
- SDOperand Op0, Op1;
+ SDValue Op0, Op1;
switch (ConstraintCode) {
default: return true;
case 'm': // memory
@@ -358,11 +358,11 @@
\arg Index The base address index
*/
bool
-SPUDAGToDAGISel::SelectAFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
- SDOperand &Index) {
+SPUDAGToDAGISel::SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base,
+ SDValue &Index) {
// These match the addr256k operand type:
MVT OffsVT = MVT::i16;
- SDOperand Zero = CurDAG->getTargetConstant(0, OffsVT);
+ SDValue Zero = CurDAG->getTargetConstant(0, OffsVT);
switch (N.getOpcode()) {
case ISD::Constant:
@@ -384,7 +384,7 @@
// Just load from memory if there's only a single use of the location,
// otherwise, this will get handled below with D-form offset addresses
if (N.hasOneUse()) {
- SDOperand Op0 = N.getOperand(0);
+ SDValue Op0 = N.getOperand(0);
switch (Op0.getOpcode()) {
case ISD::TargetConstantPool:
case ISD::TargetJumpTable:
@@ -410,8 +410,8 @@
}
bool
-SPUDAGToDAGISel::SelectDForm2Addr(SDOperand Op, SDOperand N, SDOperand &Disp,
- SDOperand &Base) {
+SPUDAGToDAGISel::SelectDForm2Addr(SDValue Op, SDValue N, SDValue &Disp,
+ SDValue &Base) {
const int minDForm2Offset = -(1 << 7);
const int maxDForm2Offset = (1 << 7) - 1;
return DFormAddressPredicate(Op, N, Disp, Base, minDForm2Offset,
@@ -428,19 +428,19 @@
displacement, [r+I10] (D-form address).
\return true if \a N is a D-form address with \a Base and \a Index set
- to non-empty SDOperand instances.
+ to non-empty SDValue instances.
*/
bool
-SPUDAGToDAGISel::SelectDFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
- SDOperand &Index) {
+SPUDAGToDAGISel::SelectDFormAddr(SDValue Op, SDValue N, SDValue &Base,
+ SDValue &Index) {
return DFormAddressPredicate(Op, N, Base, Index,
SPUFrameInfo::minFrameOffset(),
SPUFrameInfo::maxFrameOffset());
}
bool
-SPUDAGToDAGISel::DFormAddressPredicate(SDOperand Op, SDOperand N, SDOperand &Base,
- SDOperand &Index, int minOffset,
+SPUDAGToDAGISel::DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Base,
+ SDValue &Index, int minOffset,
int maxOffset) {
unsigned Opc = N.getOpcode();
MVT PtrTy = SPUtli.getPointerTy();
@@ -458,8 +458,8 @@
}
} else if (Opc == ISD::ADD) {
// Generated by getelementptr
- const SDOperand Op0 = N.getOperand(0);
- const SDOperand Op1 = N.getOperand(1);
+ const SDValue Op0 = N.getOperand(0);
+ const SDValue Op1 = N.getOperand(1);
if ((Op0.getOpcode() == SPUISD::Hi && Op1.getOpcode() == SPUISD::Lo)
|| (Op1.getOpcode() == SPUISD::Hi && Op0.getOpcode() == SPUISD::Lo)) {
@@ -511,8 +511,8 @@
}
} else if (Opc == SPUISD::IndirectAddr) {
// Indirect with constant offset -> D-Form address
- const SDOperand Op0 = N.getOperand(0);
- const SDOperand Op1 = N.getOperand(1);
+ const SDValue Op0 = N.getOperand(0);
+ const SDValue Op1 = N.getOperand(1);
if (Op0.getOpcode() == SPUISD::Hi
&& Op1.getOpcode() == SPUISD::Lo) {
@@ -522,7 +522,7 @@
return true;
} else if (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1)) {
int32_t offset = 0;
- SDOperand idxOp;
+ SDValue idxOp;
if (isa<ConstantSDNode>(Op1)) {
ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
@@ -563,8 +563,8 @@
address.
*/
bool
-SPUDAGToDAGISel::SelectXFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
- SDOperand &Index) {
+SPUDAGToDAGISel::SelectXFormAddr(SDValue Op, SDValue N, SDValue &Base,
+ SDValue &Index) {
if (SelectAFormAddr(Op, N, Base, Index)
|| SelectDFormAddr(Op, N, Base, Index))
return false;
@@ -579,13 +579,13 @@
/*!
*/
SDNode *
-SPUDAGToDAGISel::Select(SDOperand Op) {
+SPUDAGToDAGISel::Select(SDValue Op) {
SDNode *N = Op.Val;
unsigned Opc = N->getOpcode();
int n_ops = -1;
unsigned NewOpc;
MVT OpVT = Op.getValueType();
- SDOperand Ops[8];
+ SDValue Ops[8];
if (N->isMachineOpcode()) {
return NULL; // Already selected.
@@ -617,7 +617,7 @@
}
} else if (Opc == ISD::ZERO_EXTEND) {
// (zero_extend:i16 (and:i8 <arg>, <const>))
- const SDOperand &Op1 = N->getOperand(0);
+ const SDValue &Op1 = N->getOperand(0);
if (Op.getValueType() == MVT::i16 && Op1.getValueType() == MVT::i8) {
if (Op1.getOpcode() == ISD::AND) {
@@ -634,8 +634,8 @@
} else if (Opc == SPUISD::LDRESULT) {
// Custom select instructions for LDRESULT
MVT VT = N->getValueType(0);
- SDOperand Arg = N->getOperand(0);
- SDOperand Chain = N->getOperand(1);
+ SDValue Arg = N->getOperand(0);
+ SDValue Chain = N->getOperand(1);
SDNode *Result;
const valtype_map_s *vtm = getValueTypeMapEntry(VT);
@@ -649,7 +649,7 @@
AddToISelQueue(Arg);
Opc = vtm->ldresult_ins;
if (vtm->ldresult_imm) {
- SDOperand Zero = CurDAG->getTargetConstant(0, VT);
+ SDValue Zero = CurDAG->getTargetConstant(0, VT);
AddToISelQueue(Zero);
Result = CurDAG->getTargetNode(Opc, VT, MVT::Other, Arg, Zero, Chain);
@@ -657,16 +657,16 @@
Result = CurDAG->getTargetNode(Opc, MVT::Other, Arg, Arg, Chain);
}
- Chain = SDOperand(Result, 1);
+ Chain = SDValue(Result, 1);
AddToISelQueue(Chain);
return Result;
} else if (Opc == SPUISD::IndirectAddr) {
- SDOperand Op0 = Op.getOperand(0);
+ SDValue Op0 = Op.getOperand(0);
if (Op0.getOpcode() == SPUISD::LDRESULT) {
/* || Op0.getOpcode() == SPUISD::AFormAddr) */
// (IndirectAddr (LDRESULT, imm))
- SDOperand Op1 = Op.getOperand(1);
+ SDValue Op1 = Op.getOperand(1);
MVT VT = Op.getValueType();
DEBUG(cerr << "CellSPU: IndirectAddr(LDRESULT, imm):\nOp0 = ");
Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Sun Jul 27 16:46:04 2008
@@ -85,7 +85,7 @@
address, external symbol, constant pool) or an A-form
address.
*/
- bool isMemoryOperand(const SDOperand &Op)
+ bool isMemoryOperand(const SDValue &Op)
{
const unsigned Opc = Op.getOpcode();
return (Opc == ISD::GlobalAddress
@@ -102,7 +102,7 @@
}
//! Predicate that returns true if the operand is an indirect target
- bool isIndirectOperand(const SDOperand &Op)
+ bool isIndirectOperand(const SDValue &Op)
{
const unsigned Opc = Op.getOpcode();
return (Opc == ISD::Register
@@ -453,7 +453,7 @@
return ((i != node_names.end()) ? i->second : 0);
}
-MVT SPUTargetLowering::getSetCCResultType(const SDOperand &Op) const {
+MVT SPUTargetLowering::getSetCCResultType(const SDValue &Op) const {
MVT VT = Op.getValueType();
if (VT.isInteger())
return VT;
@@ -491,19 +491,19 @@
Both load and store lowering load a block of data aligned on a 16-byte
boundary. This is the common aligned load code shared between both.
*/
-static SDOperand
-AlignedLoad(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST,
+static SDValue
+AlignedLoad(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST,
LSBaseSDNode *LSN,
unsigned &alignment, int &alignOffs, int &prefSlotOffs,
MVT &VT, bool &was16aligned)
{
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
const valtype_map_s *vtm = getValueTypeMapEntry(VT);
- SDOperand basePtr = LSN->getBasePtr();
- SDOperand chain = LSN->getChain();
+ SDValue basePtr = LSN->getBasePtr();
+ SDValue chain = LSN->getChain();
if (basePtr.getOpcode() == ISD::ADD) {
- SDOperand Op1 = basePtr.Val->getOperand(1);
+ SDValue Op1 = basePtr.Val->getOperand(1);
if (Op1.getOpcode() == ISD::Constant || Op1.getOpcode() == ISD::TargetConstant) {
const ConstantSDNode *CN = cast<ConstantSDNode>(basePtr.getOperand(1));
@@ -518,7 +518,7 @@
// Loading from memory, can we adjust alignment?
if (basePtr.getOpcode() == SPUISD::AFormAddr) {
- SDOperand APtr = basePtr.getOperand(0);
+ SDValue APtr = basePtr.getOperand(0);
if (APtr.getOpcode() == ISD::TargetGlobalAddress) {
GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(APtr);
alignment = GSDN->getGlobal()->getAlignment();
@@ -574,21 +574,21 @@
All CellSPU loads and stores are aligned to 16-byte boundaries, so for elements
within a 16-byte block, we have to rotate to extract the requested element.
*/
-static SDOperand
-LowerLOAD(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
+static SDValue
+LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
LoadSDNode *LN = cast<LoadSDNode>(Op);
- SDOperand the_chain = LN->getChain();
+ SDValue the_chain = LN->getChain();
MVT VT = LN->getMemoryVT();
MVT OpVT = Op.Val->getValueType(0);
ISD::LoadExtType ExtType = LN->getExtensionType();
unsigned alignment = LN->getAlignment();
- SDOperand Ops[8];
+ SDValue Ops[8];
switch (LN->getAddressingMode()) {
case ISD::UNINDEXED: {
int offset, rotamt;
bool was16aligned;
- SDOperand result =
+ SDValue result =
AlignedLoad(Op, DAG, ST, LN,alignment, offset, rotamt, VT, was16aligned);
if (result.Val == 0)
@@ -652,7 +652,7 @@
}
SDVTList retvts = DAG.getVTList(OpVT, MVT::Other);
- SDOperand retops[2] = {
+ SDValue retops[2] = {
result,
the_chain
};
@@ -673,7 +673,7 @@
/*NOTREACHED*/
}
- return SDOperand();
+ return SDValue();
}
/// Custom lower stores for CellSPU
@@ -682,10 +682,10 @@
within a 16-byte block, we have to generate a shuffle to insert the
requested element into its place, then store the resulting block.
*/
-static SDOperand
-LowerSTORE(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
+static SDValue
+LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
StoreSDNode *SN = cast<StoreSDNode>(Op);
- SDOperand Value = SN->getValue();
+ SDValue Value = SN->getValue();
MVT VT = Value.getValueType();
MVT StVT = (!SN->isTruncatingStore() ? VT : SN->getMemoryVT());
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
@@ -704,7 +704,7 @@
stVecVT = MVT::getVectorVT(StVT, (128 / StVT.getSizeInBits()));
vecVT = MVT::getVectorVT(VT, (128 / VT.getSizeInBits()));
- SDOperand alignLoadVec =
+ SDValue alignLoadVec =
AlignedLoad(Op, DAG, ST, SN, alignment,
chunk_offset, slot_offset, VT, was16aligned);
@@ -712,10 +712,10 @@
return alignLoadVec;
LoadSDNode *LN = cast<LoadSDNode>(alignLoadVec);
- SDOperand basePtr = LN->getBasePtr();
- SDOperand the_chain = alignLoadVec.getValue(1);
- SDOperand theValue = SN->getValue();
- SDOperand result;
+ SDValue basePtr = LN->getBasePtr();
+ SDValue the_chain = alignLoadVec.getValue(1);
+ SDValue theValue = SN->getValue();
+ SDValue result;
if (StVT != VT
&& (theValue.getOpcode() == ISD::AssertZext
@@ -727,9 +727,9 @@
chunk_offset &= 0xf;
- SDOperand insertEltOffs = DAG.getConstant(chunk_offset, PtrVT);
- SDOperand insertEltPtr;
- SDOperand insertEltOp;
+ SDValue insertEltOffs = DAG.getConstant(chunk_offset, PtrVT);
+ SDValue insertEltPtr;
+ SDValue insertEltOp;
// If the base pointer is already a D-form address, then just create
// a new D-form address with a slot offset and the orignal base pointer.
@@ -772,73 +772,73 @@
/*NOTREACHED*/
}
- return SDOperand();
+ return SDValue();
}
/// Generate the address of a constant pool entry.
-static SDOperand
-LowerConstantPool(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
+static SDValue
+LowerConstantPool(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
MVT PtrVT = Op.getValueType();
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
Constant *C = CP->getConstVal();
- SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
- SDOperand Zero = DAG.getConstant(0, PtrVT);
+ SDValue CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
+ SDValue Zero = DAG.getConstant(0, PtrVT);
const TargetMachine &TM = DAG.getTarget();
if (TM.getRelocationModel() == Reloc::Static) {
if (!ST->usingLargeMem()) {
- // Just return the SDOperand with the constant pool address in it.
+ // Just return the SDValue with the constant pool address in it.
return DAG.getNode(SPUISD::AFormAddr, PtrVT, CPI, Zero);
} else {
- SDOperand Hi = DAG.getNode(SPUISD::Hi, PtrVT, CPI, Zero);
- SDOperand Lo = DAG.getNode(SPUISD::Lo, PtrVT, CPI, Zero);
+ SDValue Hi = DAG.getNode(SPUISD::Hi, PtrVT, CPI, Zero);
+ SDValue Lo = DAG.getNode(SPUISD::Lo, PtrVT, CPI, Zero);
return DAG.getNode(SPUISD::IndirectAddr, PtrVT, Hi, Lo);
}
}
assert(0 &&
"LowerConstantPool: Relocation model other than static not supported.");
- return SDOperand();
+ return SDValue();
}
-static SDOperand
-LowerJumpTable(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
+static SDValue
+LowerJumpTable(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
MVT PtrVT = Op.getValueType();
JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
- SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
- SDOperand Zero = DAG.getConstant(0, PtrVT);
+ SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
+ SDValue Zero = DAG.getConstant(0, PtrVT);
const TargetMachine &TM = DAG.getTarget();
if (TM.getRelocationModel() == Reloc::Static) {
if (!ST->usingLargeMem()) {
return DAG.getNode(SPUISD::AFormAddr, PtrVT, JTI, Zero);
} else {
- SDOperand Hi = DAG.getNode(SPUISD::Hi, PtrVT, JTI, Zero);
- SDOperand Lo = DAG.getNode(SPUISD::Lo, PtrVT, JTI, Zero);
+ SDValue Hi = DAG.getNode(SPUISD::Hi, PtrVT, JTI, Zero);
+ SDValue Lo = DAG.getNode(SPUISD::Lo, PtrVT, JTI, Zero);
return DAG.getNode(SPUISD::IndirectAddr, PtrVT, Hi, Lo);
}
}
assert(0 &&
"LowerJumpTable: Relocation model other than static not supported.");
- return SDOperand();
+ return SDValue();
}
-static SDOperand
-LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
+static SDValue
+LowerGlobalAddress(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
MVT PtrVT = Op.getValueType();
GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
GlobalValue *GV = GSDN->getGlobal();
- SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
+ SDValue GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
const TargetMachine &TM = DAG.getTarget();
- SDOperand Zero = DAG.getConstant(0, PtrVT);
+ SDValue Zero = DAG.getConstant(0, PtrVT);
if (TM.getRelocationModel() == Reloc::Static) {
if (!ST->usingLargeMem()) {
return DAG.getNode(SPUISD::AFormAddr, PtrVT, GA, Zero);
} else {
- SDOperand Hi = DAG.getNode(SPUISD::Hi, PtrVT, GA, Zero);
- SDOperand Lo = DAG.getNode(SPUISD::Lo, PtrVT, GA, Zero);
+ SDValue Hi = DAG.getNode(SPUISD::Hi, PtrVT, GA, Zero);
+ SDValue Lo = DAG.getNode(SPUISD::Lo, PtrVT, GA, Zero);
return DAG.getNode(SPUISD::IndirectAddr, PtrVT, Hi, Lo);
}
} else {
@@ -848,7 +848,7 @@
/*NOTREACHED*/
}
- return SDOperand();
+ return SDValue();
}
//! Custom lower i64 integer constants
@@ -856,13 +856,13 @@
This code inserts all of the necessary juggling that needs to occur to load
a 64-bit constant into a register.
*/
-static SDOperand
-LowerConstant(SDOperand Op, SelectionDAG &DAG) {
+static SDValue
+LowerConstant(SDValue Op, SelectionDAG &DAG) {
MVT VT = Op.getValueType();
ConstantSDNode *CN = cast<ConstantSDNode>(Op.Val);
if (VT == MVT::i64) {
- SDOperand T = DAG.getConstant(CN->getValue(), MVT::i64);
+ SDValue T = DAG.getConstant(CN->getValue(), MVT::i64);
return DAG.getNode(SPUISD::EXTRACT_ELT0, VT,
DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i64, T, T));
} else {
@@ -873,12 +873,12 @@
/*NOTREACHED*/
}
- return SDOperand();
+ return SDValue();
}
//! Custom lower double precision floating point constants
-static SDOperand
-LowerConstantFP(SDOperand Op, SelectionDAG &DAG) {
+static SDValue
+LowerConstantFP(SDValue Op, SelectionDAG &DAG) {
MVT VT = Op.getValueType();
ConstantFPSDNode *FP = cast<ConstantFPSDNode>(Op.Val);
@@ -891,14 +891,14 @@
LowerConstant(DAG.getConstant(dbits, MVT::i64), DAG));
}
- return SDOperand();
+ return SDValue();
}
//! Lower MVT::i1, MVT::i8 brcond to a promoted type (MVT::i32, MVT::i16)
-static SDOperand
-LowerBRCOND(SDOperand Op, SelectionDAG &DAG)
+static SDValue
+LowerBRCOND(SDValue Op, SelectionDAG &DAG)
{
- SDOperand Cond = Op.getOperand(1);
+ SDValue Cond = Op.getOperand(1);
MVT CondVT = Cond.getValueType();
MVT CondNVT;
@@ -909,17 +909,17 @@
DAG.getNode(ISD::ZERO_EXTEND, CondNVT, Op.getOperand(1)),
Op.getOperand(2));
} else
- return SDOperand(); // Unchanged
+ return SDValue(); // Unchanged
}
-static SDOperand
-LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex)
+static SDValue
+LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG, int &VarArgsFrameIndex)
{
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo();
MachineRegisterInfo &RegInfo = MF.getRegInfo();
- SmallVector<SDOperand, 8> ArgValues;
- SDOperand Root = Op.getOperand(0);
+ SmallVector<SDValue, 8> ArgValues;
+ SDValue Root = Op.getOperand(0);
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
const unsigned *ArgRegs = SPURegisterInfo::getArgRegs();
@@ -933,7 +933,7 @@
// Add DAG nodes to load the arguments or copy them out of registers.
for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
- SDOperand ArgVal;
+ SDValue ArgVal;
bool needsLoad = false;
MVT ObjectVT = Op.getValue(ArgNo).getValueType();
unsigned ObjSize = ObjectVT.getSizeInBits()/8;
@@ -1026,7 +1026,7 @@
// that we ran out of physical registers of the appropriate type
if (needsLoad) {
int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
- SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
+ SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
ArgOffset += StackSlotSize;
}
@@ -1039,19 +1039,19 @@
if (isVarArg) {
VarArgsFrameIndex = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
ArgOffset);
- SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
+ SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
// If this function is vararg, store any remaining integer argument regs to
// their spots on the stack so that they may be loaded by deferencing the
// result of va_next.
- SmallVector<SDOperand, 8> MemOps;
+ SmallVector<SDValue, 8> MemOps;
for (; ArgRegIdx != NumArgRegs; ++ArgRegIdx) {
unsigned VReg = RegInfo.createVirtualRegister(&SPU::GPRCRegClass);
RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg);
- SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
- SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
+ SDValue Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
+ SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
MemOps.push_back(Store);
// Increment the address by four for the next argument to store
- SDOperand PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
+ SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
}
if (!MemOps.empty())
@@ -1067,7 +1067,7 @@
/// isLSAAddress - Return the immediate to use if the specified
/// value is representable as a LSA address.
-static SDNode *isLSAAddress(SDOperand Op, SelectionDAG &DAG) {
+static SDNode *isLSAAddress(SDValue Op, SelectionDAG &DAG) {
ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
if (!C) return 0;
@@ -1080,14 +1080,14 @@
}
static
-SDOperand
-LowerCALL(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
- SDOperand Chain = Op.getOperand(0);
+SDValue
+LowerCALL(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
+ SDValue Chain = Op.getOperand(0);
#if 0
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
#endif
- SDOperand Callee = Op.getOperand(4);
+ SDValue Callee = Op.getOperand(4);
unsigned NumOps = (Op.getNumOperands() - 5) / 2;
unsigned StackSlotSize = SPUFrameInfo::stackSlotSize();
const unsigned *ArgRegs = SPURegisterInfo::getArgRegs();
@@ -1104,7 +1104,7 @@
// Set up a copy of the stack pointer for use loading and storing any
// arguments that may not fit in the registers available for argument
// passing.
- SDOperand StackPtr = DAG.getRegister(SPU::R1, MVT::i32);
+ SDValue StackPtr = DAG.getRegister(SPU::R1, MVT::i32);
// Figure out which arguments are going to go in registers, and which in
// memory.
@@ -1112,16 +1112,16 @@
unsigned ArgRegIdx = 0;
// Keep track of registers passing arguments
- std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
+ std::vector<std::pair<unsigned, SDValue> > RegsToPass;
// And the arguments passed on the stack
- SmallVector<SDOperand, 8> MemOpChains;
+ SmallVector<SDValue, 8> MemOpChains;
for (unsigned i = 0; i != NumOps; ++i) {
- SDOperand Arg = Op.getOperand(5+2*i);
+ SDValue Arg = Op.getOperand(5+2*i);
// PtrOff will be used to store the current argument to the stack if a
// register cannot be found for it.
- SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
+ SDValue PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff);
switch (Arg.getValueType().getSimpleVT()) {
@@ -1171,14 +1171,14 @@
// Build a sequence of copy-to-reg nodes chained together with token chain
// and flag operands which copy the outgoing args into the appropriate regs.
- SDOperand InFlag;
+ SDValue InFlag;
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
InFlag);
InFlag = Chain.getValue(1);
}
- SmallVector<SDOperand, 8> Ops;
+ SmallVector<SDValue, 8> Ops;
unsigned CallOpc = SPUISD::CALL;
// If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
@@ -1187,8 +1187,8 @@
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
GlobalValue *GV = G->getGlobal();
MVT CalleeVT = Callee.getValueType();
- SDOperand Zero = DAG.getConstant(0, PtrVT);
- SDOperand GA = DAG.getTargetGlobalAddress(GV, CalleeVT);
+ SDValue Zero = DAG.getConstant(0, PtrVT);
+ SDValue GA = DAG.getTargetGlobalAddress(GV, CalleeVT);
if (!ST->usingLargeMem()) {
// Turn calls to targets that are defined (i.e., have bodies) into BRSL
@@ -1214,7 +1214,7 @@
else if (SDNode *Dest = isLSAAddress(Callee, DAG)) {
// If this is an absolute destination address that appears to be a legal
// local store address, use the munged value.
- Callee = SDOperand(Dest, 0);
+ Callee = SDValue(Dest, 0);
}
Ops.push_back(Chain);
@@ -1240,7 +1240,7 @@
if (Op.Val->getValueType(0) != MVT::Other)
InFlag = Chain.getValue(1);
- SDOperand ResultVals[3];
+ SDValue ResultVals[3];
unsigned NumResults = 0;
// If the call has results, copy the values out of the ret val registers.
@@ -1291,12 +1291,12 @@
// Otherwise, merge everything together with a MERGE_VALUES node.
ResultVals[NumResults++] = Chain;
- SDOperand Res = DAG.getMergeValues(ResultVals, NumResults);
+ SDValue Res = DAG.getMergeValues(ResultVals, NumResults);
return Res.getValue(Op.ResNo);
}
-static SDOperand
-LowerRET(SDOperand Op, SelectionDAG &DAG, TargetMachine &TM) {
+static SDValue
+LowerRET(SDValue Op, SelectionDAG &DAG, TargetMachine &TM) {
SmallVector<CCValAssign, 16> RVLocs;
unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
@@ -1310,8 +1310,8 @@
DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
}
- SDOperand Chain = Op.getOperand(0);
- SDOperand Flag;
+ SDValue Chain = Op.getOperand(0);
+ SDValue Flag;
// Copy the result values into the output registers.
for (unsigned i = 0; i != RVLocs.size(); ++i) {
@@ -1334,7 +1334,7 @@
static ConstantSDNode *
getVecImm(SDNode *N) {
- SDOperand OpVal(0, 0);
+ SDValue OpVal(0, 0);
// Check to see if this buildvec has a single non-undef value in its elements.
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
@@ -1357,7 +1357,7 @@
/// get_vec_i18imm - Test if this vector is a vector filled with the same value
/// and the value fits into an unsigned 18-bit constant, and if so, return the
/// constant
-SDOperand SPU::get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
+SDValue SPU::get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
MVT ValueType) {
if (ConstantSDNode *CN = getVecImm(N)) {
uint64_t Value = CN->getValue();
@@ -1366,20 +1366,20 @@
uint32_t upper = uint32_t(UValue >> 32);
uint32_t lower = uint32_t(UValue);
if (upper != lower)
- return SDOperand();
+ return SDValue();
Value = Value >> 32;
}
if (Value <= 0x3ffff)
return DAG.getConstant(Value, ValueType);
}
- return SDOperand();
+ return SDValue();
}
/// get_vec_i16imm - Test if this vector is a vector filled with the same value
/// and the value fits into a signed 16-bit constant, and if so, return the
/// constant
-SDOperand SPU::get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
+SDValue SPU::get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
MVT ValueType) {
if (ConstantSDNode *CN = getVecImm(N)) {
int64_t Value = CN->getSignExtended();
@@ -1388,7 +1388,7 @@
uint32_t upper = uint32_t(UValue >> 32);
uint32_t lower = uint32_t(UValue);
if (upper != lower)
- return SDOperand();
+ return SDValue();
Value = Value >> 32;
}
if (Value >= -(1 << 15) && Value <= ((1 << 15) - 1)) {
@@ -1396,13 +1396,13 @@
}
}
- return SDOperand();
+ return SDValue();
}
/// get_vec_i10imm - Test if this vector is a vector filled with the same value
/// and the value fits into a signed 10-bit constant, and if so, return the
/// constant
-SDOperand SPU::get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
+SDValue SPU::get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
MVT ValueType) {
if (ConstantSDNode *CN = getVecImm(N)) {
int64_t Value = CN->getSignExtended();
@@ -1411,14 +1411,14 @@
uint32_t upper = uint32_t(UValue >> 32);
uint32_t lower = uint32_t(UValue);
if (upper != lower)
- return SDOperand();
+ return SDValue();
Value = Value >> 32;
}
if (isS10Constant(Value))
return DAG.getConstant(Value, ValueType);
}
- return SDOperand();
+ return SDValue();
}
/// get_vec_i8imm - Test if this vector is a vector filled with the same value
@@ -1428,7 +1428,7 @@
/// @note: The incoming vector is v16i8 because that's the only way we can load
/// constant vectors. Thus, we test to see if the upper and lower bytes are the
/// same value.
-SDOperand SPU::get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
+SDValue SPU::get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
MVT ValueType) {
if (ConstantSDNode *CN = getVecImm(N)) {
int Value = (int) CN->getValue();
@@ -1441,13 +1441,13 @@
return DAG.getConstant(Value, ValueType);
}
- return SDOperand();
+ return SDValue();
}
/// get_ILHUvec_imm - Test if this vector is a vector filled with the same value
/// and the value fits into a signed 16-bit constant, and if so, return the
/// constant
-SDOperand SPU::get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG,
+SDValue SPU::get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG,
MVT ValueType) {
if (ConstantSDNode *CN = getVecImm(N)) {
uint64_t Value = CN->getValue();
@@ -1457,25 +1457,25 @@
return DAG.getConstant(Value >> 16, ValueType);
}
- return SDOperand();
+ return SDValue();
}
/// get_v4i32_imm - Catch-all for general 32-bit constant vectors
-SDOperand SPU::get_v4i32_imm(SDNode *N, SelectionDAG &DAG) {
+SDValue SPU::get_v4i32_imm(SDNode *N, SelectionDAG &DAG) {
if (ConstantSDNode *CN = getVecImm(N)) {
return DAG.getConstant((unsigned) CN->getValue(), MVT::i32);
}
- return SDOperand();
+ return SDValue();
}
/// get_v4i32_imm - Catch-all for general 64-bit constant vectors
-SDOperand SPU::get_v2i64_imm(SDNode *N, SelectionDAG &DAG) {
+SDValue SPU::get_v2i64_imm(SDNode *N, SelectionDAG &DAG) {
if (ConstantSDNode *CN = getVecImm(N)) {
return DAG.getConstant((unsigned) CN->getValue(), MVT::i64);
}
- return SDOperand();
+ return SDValue();
}
// If this is a vector of constants or undefs, get the bits. A bit in
@@ -1490,7 +1490,7 @@
unsigned EltBitSize = BV->getOperand(0).getValueType().getSizeInBits();
for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
- SDOperand OpVal = BV->getOperand(i);
+ SDValue OpVal = BV->getOperand(i);
unsigned PartNo = i >= e/2; // In the upper 128 bits?
unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t.
@@ -1589,7 +1589,7 @@
// selects to a single instruction, return Op. Otherwise, if we can codegen
// this case more efficiently than a constant pool load, lower it to the
// sequence of ops that should be used.
-static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
+static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
MVT VT = Op.getValueType();
// If this is a vector of constants or undefs, get the bits. A bit in
// UndefBits is set if the corresponding element of the vector is an
@@ -1603,7 +1603,7 @@
|| !isConstantSplat(VectorBits, UndefBits,
VT.getVectorElementType().getSizeInBits(),
SplatBits, SplatUndef, SplatSize))
- return SDOperand(); // Not a constant vector, not a splat.
+ return SDValue(); // Not a constant vector, not a splat.
switch (VT.getSimpleVT()) {
default:
@@ -1612,7 +1612,7 @@
assert(SplatSize == 4
&& "LowerBUILD_VECTOR: Unexpected floating point vector element.");
// NOTE: pretend the constant is an integer. LLVM won't load FP constants
- SDOperand T = DAG.getConstant(Value32, MVT::i32);
+ SDValue T = DAG.getConstant(Value32, MVT::i32);
return DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32,
DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, T, T, T, T));
break;
@@ -1622,7 +1622,7 @@
assert(SplatSize == 8
&& "LowerBUILD_VECTOR: 64-bit float vector element: unexpected size.");
// NOTE: pretend the constant is an integer. LLVM won't load FP constants
- SDOperand T = DAG.getConstant(f64val, MVT::i64);
+ SDValue T = DAG.getConstant(f64val, MVT::i64);
return DAG.getNode(ISD::BIT_CONVERT, MVT::v2f64,
DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i64, T, T));
break;
@@ -1630,7 +1630,7 @@
case MVT::v16i8: {
// 8-bit constants have to be expanded to 16-bits
unsigned short Value16 = SplatBits | (SplatBits << 8);
- SDOperand Ops[8];
+ SDValue Ops[8];
for (int i = 0; i < 8; ++i)
Ops[i] = DAG.getConstant(Value16, MVT::i16);
return DAG.getNode(ISD::BIT_CONVERT, VT,
@@ -1642,14 +1642,14 @@
Value16 = (unsigned short) (SplatBits & 0xffff);
else
Value16 = (unsigned short) (SplatBits | (SplatBits << 8));
- SDOperand T = DAG.getConstant(Value16, VT.getVectorElementType());
- SDOperand Ops[8];
+ SDValue T = DAG.getConstant(Value16, VT.getVectorElementType());
+ SDValue Ops[8];
for (int i = 0; i < 8; ++i) Ops[i] = T;
return DAG.getNode(ISD::BUILD_VECTOR, VT, Ops, 8);
}
case MVT::v4i32: {
unsigned int Value = SplatBits;
- SDOperand T = DAG.getConstant(Value, VT.getVectorElementType());
+ SDValue T = DAG.getConstant(Value, VT.getVectorElementType());
return DAG.getNode(ISD::BUILD_VECTOR, VT, T, T, T, T);
}
case MVT::v2i64: {
@@ -1659,13 +1659,13 @@
if (upper == lower) {
// Magic constant that can be matched by IL, ILA, et. al.
- SDOperand Val = DAG.getTargetConstant(val, MVT::i64);
+ SDValue Val = DAG.getTargetConstant(val, MVT::i64);
return DAG.getNode(ISD::BUILD_VECTOR, VT, Val, Val);
} else {
- SDOperand LO32;
- SDOperand HI32;
- SmallVector<SDOperand, 16> ShufBytes;
- SDOperand Result;
+ SDValue LO32;
+ SDValue HI32;
+ SmallVector<SDValue, 16> ShufBytes;
+ SDValue Result;
bool upper_special, lower_special;
// NOTE: This code creates common-case shuffle masks that can be easily
@@ -1678,7 +1678,7 @@
// Create lower vector if not a special pattern
if (!lower_special) {
- SDOperand LO32C = DAG.getConstant(lower, MVT::i32);
+ SDValue LO32C = DAG.getConstant(lower, MVT::i32);
LO32 = DAG.getNode(ISD::BIT_CONVERT, VT,
DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32,
LO32C, LO32C, LO32C, LO32C));
@@ -1686,7 +1686,7 @@
// Create upper vector if not a special pattern
if (!upper_special) {
- SDOperand HI32C = DAG.getConstant(upper, MVT::i32);
+ SDValue HI32C = DAG.getConstant(upper, MVT::i32);
HI32 = DAG.getNode(ISD::BIT_CONVERT, VT,
DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32,
HI32C, HI32C, HI32C, HI32C));
@@ -1701,7 +1701,7 @@
if (lower_special && upper_special) {
// Unhappy situation... both upper and lower are special, so punt with
// a target constant:
- SDOperand Zero = DAG.getConstant(0, MVT::i32);
+ SDValue Zero = DAG.getConstant(0, MVT::i32);
HI32 = LO32 = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Zero, Zero,
Zero, Zero);
}
@@ -1709,7 +1709,7 @@
for (int i = 0; i < 4; ++i) {
uint64_t val = 0;
for (int j = 0; j < 4; ++j) {
- SDOperand V;
+ SDValue V;
bool process_upper, process_lower;
val <<= 8;
process_upper = (upper_special && (i & 1) == 0);
@@ -1739,7 +1739,7 @@
}
}
- return SDOperand();
+ return SDValue();
}
/// LowerVECTOR_SHUFFLE - Lower a vector shuffle (V1, V2, V3) to something on
@@ -1755,10 +1755,10 @@
/// element move from V2 into V1.
/// \note
/// SPUISD::SHUFB is eventually selected as Cell's <i>shufb</i> instructions.
-static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
- SDOperand V1 = Op.getOperand(0);
- SDOperand V2 = Op.getOperand(1);
- SDOperand PermMask = Op.getOperand(2);
+static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
+ SDValue V1 = Op.getOperand(0);
+ SDValue V2 = Op.getOperand(1);
+ SDValue PermMask = Op.getOperand(2);
if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
@@ -1806,10 +1806,10 @@
unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
// Initialize temporary register to 0
- SDOperand InitTempReg =
+ SDValue InitTempReg =
DAG.getCopyToReg(DAG.getEntryNode(), VReg, DAG.getConstant(0, PtrVT));
// Copy register's contents as index in INSERT_MASK:
- SDOperand ShufMaskOp =
+ SDValue ShufMaskOp =
DAG.getNode(SPUISD::INSERT_MASK, V1.getValueType(),
DAG.getTargetConstant(V2Elt, MVT::i32),
DAG.getCopyFromReg(InitTempReg, VReg, PtrVT));
@@ -1819,7 +1819,7 @@
// Convert the SHUFFLE_VECTOR mask's input element units to the actual bytes.
unsigned BytesPerElement = EltVT.getSizeInBits()/8;
- SmallVector<SDOperand, 16> ResultMask;
+ SmallVector<SDValue, 16> ResultMask;
for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
unsigned SrcElt;
if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
@@ -1833,21 +1833,21 @@
}
}
- SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8,
+ SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8,
&ResultMask[0], ResultMask.size());
return DAG.getNode(SPUISD::SHUFB, V1.getValueType(), V1, V2, VPermMask);
}
}
-static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
- SDOperand Op0 = Op.getOperand(0); // Op0 = the scalar
+static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
+ SDValue Op0 = Op.getOperand(0); // Op0 = the scalar
if (Op0.Val->getOpcode() == ISD::Constant) {
// For a constant, build the appropriate constant vector, which will
// eventually simplify to a vector register load.
ConstantSDNode *CN = cast<ConstantSDNode>(Op0.Val);
- SmallVector<SDOperand, 16> ConstVecValues;
+ SmallVector<SDValue, 16> ConstVecValues;
MVT VT;
size_t n_copies;
@@ -1863,7 +1863,7 @@
case MVT::v2f64: n_copies = 2; VT = MVT::f64; break;
}
- SDOperand CValue = DAG.getConstant(CN->getValue(), VT);
+ SDValue CValue = DAG.getConstant(CN->getValue(), VT);
for (size_t j = 0; j < n_copies; ++j)
ConstVecValues.push_back(CValue);
@@ -1883,10 +1883,10 @@
}
}
- return SDOperand();
+ return SDValue();
}
-static SDOperand LowerVectorMUL(SDOperand Op, SelectionDAG &DAG) {
+static SDValue LowerVectorMUL(SDValue Op, SelectionDAG &DAG) {
switch (Op.getValueType().getSimpleVT()) {
default:
cerr << "CellSPU: Unknown vector multiplication, got "
@@ -1896,12 +1896,12 @@
/*NOTREACHED*/
case MVT::v4i32: {
- SDOperand rA = Op.getOperand(0);
- SDOperand rB = Op.getOperand(1);
- SDOperand HiProd1 = DAG.getNode(SPUISD::MPYH, MVT::v4i32, rA, rB);
- SDOperand HiProd2 = DAG.getNode(SPUISD::MPYH, MVT::v4i32, rB, rA);
- SDOperand LoProd = DAG.getNode(SPUISD::MPYU, MVT::v4i32, rA, rB);
- SDOperand Residual1 = DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd1);
+ SDValue rA = Op.getOperand(0);
+ SDValue rB = Op.getOperand(1);
+ SDValue HiProd1 = DAG.getNode(SPUISD::MPYH, MVT::v4i32, rA, rB);
+ SDValue HiProd2 = DAG.getNode(SPUISD::MPYH, MVT::v4i32, rB, rA);
+ SDValue LoProd = DAG.getNode(SPUISD::MPYU, MVT::v4i32, rA, rB);
+ SDValue Residual1 = DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd1);
return DAG.getNode(ISD::ADD, MVT::v4i32, Residual1, HiProd2);
break;
@@ -1918,22 +1918,22 @@
case MVT::v8i16: {
MachineFunction &MF = DAG.getMachineFunction();
MachineRegisterInfo &RegInfo = MF.getRegInfo();
- SDOperand Chain = Op.getOperand(0);
- SDOperand rA = Op.getOperand(0);
- SDOperand rB = Op.getOperand(1);
+ SDValue Chain = Op.getOperand(0);
+ SDValue rA = Op.getOperand(0);
+ SDValue rB = Op.getOperand(1);
unsigned FSMBIreg = RegInfo.createVirtualRegister(&SPU::VECREGRegClass);
unsigned HiProdReg = RegInfo.createVirtualRegister(&SPU::VECREGRegClass);
- SDOperand FSMBOp =
+ SDValue FSMBOp =
DAG.getCopyToReg(Chain, FSMBIreg,
DAG.getNode(SPUISD::SELECT_MASK, MVT::v8i16,
DAG.getConstant(0xcccc, MVT::i16)));
- SDOperand HHProd =
+ SDValue HHProd =
DAG.getCopyToReg(FSMBOp, HiProdReg,
DAG.getNode(SPUISD::MPYHH, MVT::v8i16, rA, rB));
- SDOperand HHProd_v4i32 =
+ SDValue HHProd_v4i32 =
DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32,
DAG.getCopyFromReg(HHProd, HiProdReg, MVT::v4i32));
@@ -1952,68 +1952,68 @@
// is to break it all apart, sign extend, and reassemble the various
// intermediate products.
case MVT::v16i8: {
- SDOperand rA = Op.getOperand(0);
- SDOperand rB = Op.getOperand(1);
- SDOperand c8 = DAG.getConstant(8, MVT::i32);
- SDOperand c16 = DAG.getConstant(16, MVT::i32);
+ SDValue rA = Op.getOperand(0);
+ SDValue rB = Op.getOperand(1);
+ SDValue c8 = DAG.getConstant(8, MVT::i32);
+ SDValue c16 = DAG.getConstant(16, MVT::i32);
- SDOperand LLProd =
+ SDValue LLProd =
DAG.getNode(SPUISD::MPY, MVT::v8i16,
DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, rA),
DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, rB));
- SDOperand rALH = DAG.getNode(SPUISD::VEC_SRA, MVT::v8i16, rA, c8);
+ SDValue rALH = DAG.getNode(SPUISD::VEC_SRA, MVT::v8i16, rA, c8);
- SDOperand rBLH = DAG.getNode(SPUISD::VEC_SRA, MVT::v8i16, rB, c8);
+ SDValue rBLH = DAG.getNode(SPUISD::VEC_SRA, MVT::v8i16, rB, c8);
- SDOperand LHProd =
+ SDValue LHProd =
DAG.getNode(SPUISD::VEC_SHL, MVT::v8i16,
DAG.getNode(SPUISD::MPY, MVT::v8i16, rALH, rBLH), c8);
- SDOperand FSMBmask = DAG.getNode(SPUISD::SELECT_MASK, MVT::v8i16,
+ SDValue FSMBmask = DAG.getNode(SPUISD::SELECT_MASK, MVT::v8i16,
DAG.getConstant(0x2222, MVT::i16));
- SDOperand LoProdParts =
+ SDValue LoProdParts =
DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32,
DAG.getNode(SPUISD::SELB, MVT::v8i16,
LLProd, LHProd, FSMBmask));
- SDOperand LoProdMask = DAG.getConstant(0xffff, MVT::i32);
+ SDValue LoProdMask = DAG.getConstant(0xffff, MVT::i32);
- SDOperand LoProd =
+ SDValue LoProd =
DAG.getNode(ISD::AND, MVT::v4i32,
LoProdParts,
DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32,
LoProdMask, LoProdMask,
LoProdMask, LoProdMask));
- SDOperand rAH =
+ SDValue rAH =
DAG.getNode(SPUISD::VEC_SRA, MVT::v4i32,
DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, rA), c16);
- SDOperand rBH =
+ SDValue rBH =
DAG.getNode(SPUISD::VEC_SRA, MVT::v4i32,
DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, rB), c16);
- SDOperand HLProd =
+ SDValue HLProd =
DAG.getNode(SPUISD::MPY, MVT::v8i16,
DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, rAH),
DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, rBH));
- SDOperand HHProd_1 =
+ SDValue HHProd_1 =
DAG.getNode(SPUISD::MPY, MVT::v8i16,
DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16,
DAG.getNode(SPUISD::VEC_SRA, MVT::v4i32, rAH, c8)),
DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16,
DAG.getNode(SPUISD::VEC_SRA, MVT::v4i32, rBH, c8)));
- SDOperand HHProd =
+ SDValue HHProd =
DAG.getNode(SPUISD::SELB, MVT::v8i16,
HLProd,
DAG.getNode(SPUISD::VEC_SHL, MVT::v8i16, HHProd_1, c8),
FSMBmask);
- SDOperand HiProd =
+ SDValue HiProd =
DAG.getNode(SPUISD::VEC_SHL, MVT::v4i32, HHProd, c16);
return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8,
@@ -2022,15 +2022,15 @@
}
}
- return SDOperand();
+ return SDValue();
}
-static SDOperand LowerFDIVf32(SDOperand Op, SelectionDAG &DAG) {
+static SDValue LowerFDIVf32(SDValue Op, SelectionDAG &DAG) {
MachineFunction &MF = DAG.getMachineFunction();
MachineRegisterInfo &RegInfo = MF.getRegInfo();
- SDOperand A = Op.getOperand(0);
- SDOperand B = Op.getOperand(1);
+ SDValue A = Op.getOperand(0);
+ SDValue B = Op.getOperand(1);
MVT VT = Op.getValueType();
unsigned VRegBR, VRegC;
@@ -2047,13 +2047,13 @@
// Computes BRcpl =
// (Floating Interpolate (FP Reciprocal Estimate B))
- SDOperand BRcpl =
+ SDValue BRcpl =
DAG.getCopyToReg(DAG.getEntryNode(), VRegBR,
DAG.getNode(SPUISD::FPInterp, VT, B,
DAG.getNode(SPUISD::FPRecipEst, VT, B)));
// Computes A * BRcpl and stores in a temporary register
- SDOperand AxBRcpl =
+ SDValue AxBRcpl =
DAG.getCopyToReg(BRcpl, VRegC,
DAG.getNode(ISD::FMUL, VT, A,
DAG.getCopyFromReg(BRcpl, VRegBR, VT)));
@@ -2069,11 +2069,11 @@
DAG.getCopyFromReg(AxBRcpl, VRegC, VT)))));
}
-static SDOperand LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
+static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
MVT VT = Op.getValueType();
- SDOperand N = Op.getOperand(0);
- SDOperand Elt = Op.getOperand(1);
- SDOperand ShufMask[16];
+ SDValue N = Op.getOperand(0);
+ SDValue Elt = Op.getOperand(1);
+ SDValue ShufMask[16];
ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt);
assert(C != 0 && "LowerEXTRACT_VECTOR_ELT expecting constant SDNode");
@@ -2139,7 +2139,7 @@
ShufMask[i] = ShufMask[i % (prefslot_end + 1)];
}
- SDOperand ShufMaskVec =
+ SDValue ShufMaskVec =
DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8,
&ShufMask[0],
sizeof(ShufMask) / sizeof(ShufMask[0]));
@@ -2150,10 +2150,10 @@
}
-static SDOperand LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
- SDOperand VecOp = Op.getOperand(0);
- SDOperand ValOp = Op.getOperand(1);
- SDOperand IdxOp = Op.getOperand(2);
+static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
+ SDValue VecOp = Op.getOperand(0);
+ SDValue ValOp = Op.getOperand(1);
+ SDValue IdxOp = Op.getOperand(2);
MVT VT = Op.getValueType();
ConstantSDNode *CN = cast<ConstantSDNode>(IdxOp);
@@ -2161,9 +2161,9 @@
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
// Use $2 because it's always 16-byte aligned and it's available:
- SDOperand PtrBase = DAG.getRegister(SPU::R2, PtrVT);
+ SDValue PtrBase = DAG.getRegister(SPU::R2, PtrVT);
- SDOperand result =
+ SDValue result =
DAG.getNode(SPUISD::SHUFB, VT,
DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, ValOp),
VecOp,
@@ -2176,9 +2176,9 @@
return result;
}
-static SDOperand LowerI8Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc)
+static SDValue LowerI8Math(SDValue Op, SelectionDAG &DAG, unsigned Opc)
{
- SDOperand N0 = Op.getOperand(0); // Everything has at least one operand
+ SDValue N0 = Op.getOperand(0); // Everything has at least one operand
assert(Op.getValueType() == MVT::i8);
switch (Opc) {
@@ -2189,7 +2189,7 @@
case ISD::SUB: {
// 8-bit subtraction: Promote the arguments up to 16-bits and truncate
// the result:
- SDOperand N1 = Op.getOperand(1);
+ SDValue N1 = Op.getOperand(1);
N0 = (N0.getOpcode() != ISD::Constant
? DAG.getNode(ISD::SIGN_EXTEND, MVT::i16, N0)
: DAG.getConstant(cast<ConstantSDNode>(N0)->getValue(), MVT::i16));
@@ -2201,7 +2201,7 @@
}
case ISD::ROTR:
case ISD::ROTL: {
- SDOperand N1 = Op.getOperand(1);
+ SDValue N1 = Op.getOperand(1);
unsigned N1Opc;
N0 = (N0.getOpcode() != ISD::Constant
? DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, N0)
@@ -2210,7 +2210,7 @@
N1 = (N1.getOpcode() != ISD::Constant
? DAG.getNode(N1Opc, MVT::i16, N1)
: DAG.getConstant(cast<ConstantSDNode>(N1)->getValue(), MVT::i16));
- SDOperand ExpandArg =
+ SDValue ExpandArg =
DAG.getNode(ISD::OR, MVT::i16, N0,
DAG.getNode(ISD::SHL, MVT::i16,
N0, DAG.getConstant(8, MVT::i16)));
@@ -2219,7 +2219,7 @@
}
case ISD::SRL:
case ISD::SHL: {
- SDOperand N1 = Op.getOperand(1);
+ SDValue N1 = Op.getOperand(1);
unsigned N1Opc;
N0 = (N0.getOpcode() != ISD::Constant
? DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, N0)
@@ -2232,7 +2232,7 @@
DAG.getNode(Opc, MVT::i16, N0, N1));
}
case ISD::SRA: {
- SDOperand N1 = Op.getOperand(1);
+ SDValue N1 = Op.getOperand(1);
unsigned N1Opc;
N0 = (N0.getOpcode() != ISD::Constant
? DAG.getNode(ISD::SIGN_EXTEND, MVT::i16, N0)
@@ -2245,7 +2245,7 @@
DAG.getNode(Opc, MVT::i16, N0, N1));
}
case ISD::MUL: {
- SDOperand N1 = Op.getOperand(1);
+ SDValue N1 = Op.getOperand(1);
unsigned N1Opc;
N0 = (N0.getOpcode() != ISD::Constant
? DAG.getNode(ISD::SIGN_EXTEND, MVT::i16, N0)
@@ -2260,15 +2260,15 @@
}
}
- return SDOperand();
+ return SDValue();
}
-static SDOperand LowerI64Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc)
+static SDValue LowerI64Math(SDValue Op, SelectionDAG &DAG, unsigned Opc)
{
MVT VT = Op.getValueType();
MVT VecVT = MVT::getVectorVT(VT, (128 / VT.getSizeInBits()));
- SDOperand Op0 = Op.getOperand(0);
+ SDValue Op0 = Op.getOperand(0);
switch (Opc) {
case ISD::ZERO_EXTEND:
@@ -2284,7 +2284,7 @@
unsigned NewOpc = (Opc == ISD::SIGN_EXTEND
? SPUISD::ROTBYTES_RIGHT_S
: SPUISD::ROTQUAD_RZ_BYTES);
- SDOperand PromoteScalar =
+ SDValue PromoteScalar =
DAG.getNode(SPUISD::PROMOTE_SCALAR, Op0VecVT, Op0);
return DAG.getNode(SPUISD::EXTRACT_ELT0, VT,
@@ -2297,11 +2297,11 @@
case ISD::ADD: {
// Turn operands into vectors to satisfy type checking (shufb works on
// vectors)
- SDOperand Op0 =
+ SDValue Op0 =
DAG.getNode(SPUISD::PROMOTE_SCALAR, MVT::v2i64, Op.getOperand(0));
- SDOperand Op1 =
+ SDValue Op1 =
DAG.getNode(SPUISD::PROMOTE_SCALAR, MVT::v2i64, Op.getOperand(1));
- SmallVector<SDOperand, 16> ShufBytes;
+ SmallVector<SDValue, 16> ShufBytes;
// Create the shuffle mask for "rotating" the borrow up one register slot
// once the borrow is generated.
@@ -2310,9 +2310,9 @@
ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32));
ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32));
- SDOperand CarryGen =
+ SDValue CarryGen =
DAG.getNode(SPUISD::CARRY_GENERATE, MVT::v2i64, Op0, Op1);
- SDOperand ShiftedCarry =
+ SDValue ShiftedCarry =
DAG.getNode(SPUISD::SHUFB, MVT::v2i64,
CarryGen, CarryGen,
DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32,
@@ -2326,11 +2326,11 @@
case ISD::SUB: {
// Turn operands into vectors to satisfy type checking (shufb works on
// vectors)
- SDOperand Op0 =
+ SDValue Op0 =
DAG.getNode(SPUISD::PROMOTE_SCALAR, MVT::v2i64, Op.getOperand(0));
- SDOperand Op1 =
+ SDValue Op1 =
DAG.getNode(SPUISD::PROMOTE_SCALAR, MVT::v2i64, Op.getOperand(1));
- SmallVector<SDOperand, 16> ShufBytes;
+ SmallVector<SDValue, 16> ShufBytes;
// Create the shuffle mask for "rotating" the borrow up one register slot
// once the borrow is generated.
@@ -2339,9 +2339,9 @@
ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32));
ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, MVT::i32));
- SDOperand BorrowGen =
+ SDValue BorrowGen =
DAG.getNode(SPUISD::BORROW_GENERATE, MVT::v2i64, Op0, Op1);
- SDOperand ShiftedBorrow =
+ SDValue ShiftedBorrow =
DAG.getNode(SPUISD::SHUFB, MVT::v2i64,
BorrowGen, BorrowGen,
DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32,
@@ -2353,20 +2353,20 @@
}
case ISD::SHL: {
- SDOperand ShiftAmt = Op.getOperand(1);
+ SDValue ShiftAmt = Op.getOperand(1);
MVT ShiftAmtVT = ShiftAmt.getValueType();
- SDOperand Op0Vec = DAG.getNode(SPUISD::PROMOTE_SCALAR, VecVT, Op0);
- SDOperand MaskLower =
+ SDValue Op0Vec = DAG.getNode(SPUISD::PROMOTE_SCALAR, VecVT, Op0);
+ SDValue MaskLower =
DAG.getNode(SPUISD::SELB, VecVT,
Op0Vec,
DAG.getConstant(0, VecVT),
DAG.getNode(SPUISD::SELECT_MASK, VecVT,
DAG.getConstant(0xff00ULL, MVT::i16)));
- SDOperand ShiftAmtBytes =
+ SDValue ShiftAmtBytes =
DAG.getNode(ISD::SRL, ShiftAmtVT,
ShiftAmt,
DAG.getConstant(3, ShiftAmtVT));
- SDOperand ShiftAmtBits =
+ SDValue ShiftAmtBits =
DAG.getNode(ISD::AND, ShiftAmtVT,
ShiftAmt,
DAG.getConstant(7, ShiftAmtVT));
@@ -2380,13 +2380,13 @@
case ISD::SRL: {
MVT VT = Op.getValueType();
- SDOperand ShiftAmt = Op.getOperand(1);
+ SDValue ShiftAmt = Op.getOperand(1);
MVT ShiftAmtVT = ShiftAmt.getValueType();
- SDOperand ShiftAmtBytes =
+ SDValue ShiftAmtBytes =
DAG.getNode(ISD::SRL, ShiftAmtVT,
ShiftAmt,
DAG.getConstant(3, ShiftAmtVT));
- SDOperand ShiftAmtBits =
+ SDValue ShiftAmtBits =
DAG.getNode(ISD::AND, ShiftAmtVT,
ShiftAmt,
DAG.getConstant(7, ShiftAmtVT));
@@ -2399,9 +2399,9 @@
case ISD::SRA: {
// Promote Op0 to vector
- SDOperand Op0 =
+ SDValue Op0 =
DAG.getNode(SPUISD::PROMOTE_SCALAR, MVT::v2i64, Op.getOperand(0));
- SDOperand ShiftAmt = Op.getOperand(1);
+ SDValue ShiftAmt = Op.getOperand(1);
MVT ShiftVT = ShiftAmt.getValueType();
// Negate variable shift amounts
@@ -2410,23 +2410,23 @@
DAG.getConstant(0, ShiftVT), ShiftAmt);
}
- SDOperand UpperHalfSign =
+ SDValue UpperHalfSign =
DAG.getNode(SPUISD::EXTRACT_ELT0, MVT::i32,
DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32,
DAG.getNode(SPUISD::VEC_SRA, MVT::v2i64,
Op0, DAG.getConstant(31, MVT::i32))));
- SDOperand UpperHalfSignMask =
+ SDValue UpperHalfSignMask =
DAG.getNode(SPUISD::SELECT_MASK, MVT::v2i64, UpperHalfSign);
- SDOperand UpperLowerMask =
+ SDValue UpperLowerMask =
DAG.getNode(SPUISD::SELECT_MASK, MVT::v2i64,
DAG.getConstant(0xff00, MVT::i16));
- SDOperand UpperLowerSelect =
+ SDValue UpperLowerSelect =
DAG.getNode(SPUISD::SELB, MVT::v2i64,
UpperHalfSignMask, Op0, UpperLowerMask);
- SDOperand RotateLeftBytes =
+ SDValue RotateLeftBytes =
DAG.getNode(SPUISD::ROTBYTES_LEFT_BITS, MVT::v2i64,
UpperLowerSelect, ShiftAmt);
- SDOperand RotateLeftBits =
+ SDValue RotateLeftBits =
DAG.getNode(SPUISD::ROTBYTES_LEFT, MVT::v2i64,
RotateLeftBytes, ShiftAmt);
@@ -2435,14 +2435,14 @@
}
}
- return SDOperand();
+ return SDValue();
}
//! Lower byte immediate operations for v16i8 vectors:
-static SDOperand
-LowerByteImmed(SDOperand Op, SelectionDAG &DAG) {
- SDOperand ConstVec;
- SDOperand Arg;
+static SDValue
+LowerByteImmed(SDValue Op, SelectionDAG &DAG) {
+ SDValue ConstVec;
+ SDValue Arg;
MVT VT = Op.getValueType();
ConstVec = Op.getOperand(0);
@@ -2469,8 +2469,8 @@
&& isConstantSplat(VectorBits, UndefBits,
VT.getVectorElementType().getSizeInBits(),
SplatBits, SplatUndef, SplatSize)) {
- SDOperand tcVec[16];
- SDOperand tc = DAG.getTargetConstant(SplatBits & 0xff, MVT::i8);
+ SDValue tcVec[16];
+ SDValue tc = DAG.getTargetConstant(SplatBits & 0xff, MVT::i8);
const size_t tcVecSize = sizeof(tcVec) / sizeof(tcVec[0]);
// Turn the BUILD_VECTOR into a set of target constants:
@@ -2482,11 +2482,11 @@
}
}
- return SDOperand();
+ return SDValue();
}
//! Lower i32 multiplication
-static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG, MVT VT,
+static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG, MVT VT,
unsigned Opc) {
switch (VT.getSimpleVT()) {
default:
@@ -2497,8 +2497,8 @@
/*NOTREACHED*/
case MVT::i32: {
- SDOperand rA = Op.getOperand(0);
- SDOperand rB = Op.getOperand(1);
+ SDValue rA = Op.getOperand(0);
+ SDValue rB = Op.getOperand(1);
return DAG.getNode(ISD::ADD, MVT::i32,
DAG.getNode(ISD::ADD, MVT::i32,
@@ -2508,7 +2508,7 @@
}
}
- return SDOperand();
+ return SDValue();
}
//! Custom lowering for CTPOP (count population)
@@ -2517,7 +2517,7 @@
operand. SPU has such an instruction, but it counts the number of
ones per byte, which then have to be accumulated.
*/
-static SDOperand LowerCTPOP(SDOperand Op, SelectionDAG &DAG) {
+static SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) {
MVT VT = Op.getValueType();
MVT vecVT = MVT::getVectorVT(VT, (128 / VT.getSizeInBits()));
@@ -2525,11 +2525,11 @@
default:
assert(false && "Invalid value type!");
case MVT::i8: {
- SDOperand N = Op.getOperand(0);
- SDOperand Elt0 = DAG.getConstant(0, MVT::i32);
+ SDValue N = Op.getOperand(0);
+ SDValue Elt0 = DAG.getConstant(0, MVT::i32);
- SDOperand Promote = DAG.getNode(SPUISD::PROMOTE_SCALAR, vecVT, N, N);
- SDOperand CNTB = DAG.getNode(SPUISD::CNTB, vecVT, Promote);
+ SDValue Promote = DAG.getNode(SPUISD::PROMOTE_SCALAR, vecVT, N, N);
+ SDValue CNTB = DAG.getNode(SPUISD::CNTB, vecVT, Promote);
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i8, CNTB, Elt0);
}
@@ -2540,23 +2540,23 @@
unsigned CNTB_reg = RegInfo.createVirtualRegister(&SPU::R16CRegClass);
- SDOperand N = Op.getOperand(0);
- SDOperand Elt0 = DAG.getConstant(0, MVT::i16);
- SDOperand Mask0 = DAG.getConstant(0x0f, MVT::i16);
- SDOperand Shift1 = DAG.getConstant(8, MVT::i16);
+ SDValue N = Op.getOperand(0);
+ SDValue Elt0 = DAG.getConstant(0, MVT::i16);
+ SDValue Mask0 = DAG.getConstant(0x0f, MVT::i16);
+ SDValue Shift1 = DAG.getConstant(8, MVT::i16);
- SDOperand Promote = DAG.getNode(SPUISD::PROMOTE_SCALAR, vecVT, N, N);
- SDOperand CNTB = DAG.getNode(SPUISD::CNTB, vecVT, Promote);
+ SDValue Promote = DAG.getNode(SPUISD::PROMOTE_SCALAR, vecVT, N, N);
+ SDValue CNTB = DAG.getNode(SPUISD::CNTB, vecVT, Promote);
// CNTB_result becomes the chain to which all of the virtual registers
// CNTB_reg, SUM1_reg become associated:
- SDOperand CNTB_result =
+ SDValue CNTB_result =
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, CNTB, Elt0);
- SDOperand CNTB_rescopy =
+ SDValue CNTB_rescopy =
DAG.getCopyToReg(CNTB_result, CNTB_reg, CNTB_result);
- SDOperand Tmp1 = DAG.getCopyFromReg(CNTB_rescopy, CNTB_reg, MVT::i16);
+ SDValue Tmp1 = DAG.getCopyFromReg(CNTB_rescopy, CNTB_reg, MVT::i16);
return DAG.getNode(ISD::AND, MVT::i16,
DAG.getNode(ISD::ADD, MVT::i16,
@@ -2573,39 +2573,39 @@
unsigned CNTB_reg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
unsigned SUM1_reg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
- SDOperand N = Op.getOperand(0);
- SDOperand Elt0 = DAG.getConstant(0, MVT::i32);
- SDOperand Mask0 = DAG.getConstant(0xff, MVT::i32);
- SDOperand Shift1 = DAG.getConstant(16, MVT::i32);
- SDOperand Shift2 = DAG.getConstant(8, MVT::i32);
+ SDValue N = Op.getOperand(0);
+ SDValue Elt0 = DAG.getConstant(0, MVT::i32);
+ SDValue Mask0 = DAG.getConstant(0xff, MVT::i32);
+ SDValue Shift1 = DAG.getConstant(16, MVT::i32);
+ SDValue Shift2 = DAG.getConstant(8, MVT::i32);
- SDOperand Promote = DAG.getNode(SPUISD::PROMOTE_SCALAR, vecVT, N, N);
- SDOperand CNTB = DAG.getNode(SPUISD::CNTB, vecVT, Promote);
+ SDValue Promote = DAG.getNode(SPUISD::PROMOTE_SCALAR, vecVT, N, N);
+ SDValue CNTB = DAG.getNode(SPUISD::CNTB, vecVT, Promote);
// CNTB_result becomes the chain to which all of the virtual registers
// CNTB_reg, SUM1_reg become associated:
- SDOperand CNTB_result =
+ SDValue CNTB_result =
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, CNTB, Elt0);
- SDOperand CNTB_rescopy =
+ SDValue CNTB_rescopy =
DAG.getCopyToReg(CNTB_result, CNTB_reg, CNTB_result);
- SDOperand Comp1 =
+ SDValue Comp1 =
DAG.getNode(ISD::SRL, MVT::i32,
DAG.getCopyFromReg(CNTB_rescopy, CNTB_reg, MVT::i32), Shift1);
- SDOperand Sum1 =
+ SDValue Sum1 =
DAG.getNode(ISD::ADD, MVT::i32,
Comp1, DAG.getCopyFromReg(CNTB_rescopy, CNTB_reg, MVT::i32));
- SDOperand Sum1_rescopy =
+ SDValue Sum1_rescopy =
DAG.getCopyToReg(CNTB_result, SUM1_reg, Sum1);
- SDOperand Comp2 =
+ SDValue Comp2 =
DAG.getNode(ISD::SRL, MVT::i32,
DAG.getCopyFromReg(Sum1_rescopy, SUM1_reg, MVT::i32),
Shift2);
- SDOperand Sum2 =
+ SDValue Sum2 =
DAG.getNode(ISD::ADD, MVT::i32, Comp2,
DAG.getCopyFromReg(Sum1_rescopy, SUM1_reg, MVT::i32));
@@ -2616,13 +2616,13 @@
break;
}
- return SDOperand();
+ return SDValue();
}
/// LowerOperation - Provide custom lowering hooks for some operations.
///
-SDOperand
-SPUTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG)
+SDValue
+SPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)
{
unsigned Opc = (unsigned) Op.getOpcode();
MVT VT = Op.getValueType();
@@ -2718,14 +2718,14 @@
return LowerCTPOP(Op, DAG);
}
- return SDOperand();
+ return SDValue();
}
//===----------------------------------------------------------------------===//
// Target Optimization Hooks
//===----------------------------------------------------------------------===//
-SDOperand
+SDValue
SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
{
#if 0
@@ -2733,23 +2733,23 @@
#endif
const SPUSubtarget *ST = SPUTM.getSubtargetImpl();
SelectionDAG &DAG = DCI.DAG;
- SDOperand Op0 = N->getOperand(0); // everything has at least one operand
- SDOperand Result; // Initially, NULL result
+ SDValue Op0 = N->getOperand(0); // everything has at least one operand
+ SDValue Result; // Initially, NULL result
switch (N->getOpcode()) {
default: break;
case ISD::ADD: {
- SDOperand Op1 = N->getOperand(1);
+ SDValue Op1 = N->getOperand(1);
if (isa<ConstantSDNode>(Op1) && Op0.getOpcode() == SPUISD::IndirectAddr) {
- SDOperand Op01 = Op0.getOperand(1);
+ SDValue Op01 = Op0.getOperand(1);
if (Op01.getOpcode() == ISD::Constant
|| Op01.getOpcode() == ISD::TargetConstant) {
// (add <const>, (SPUindirect <arg>, <const>)) ->
// (SPUindirect <arg>, <const + const>)
ConstantSDNode *CN0 = cast<ConstantSDNode>(Op1);
ConstantSDNode *CN1 = cast<ConstantSDNode>(Op01);
- SDOperand combinedConst =
+ SDValue combinedConst =
DAG.getConstant(CN0->getValue() + CN1->getValue(),
Op0.getValueType());
@@ -2762,14 +2762,14 @@
}
} else if (isa<ConstantSDNode>(Op0)
&& Op1.getOpcode() == SPUISD::IndirectAddr) {
- SDOperand Op11 = Op1.getOperand(1);
+ SDValue Op11 = Op1.getOperand(1);
if (Op11.getOpcode() == ISD::Constant
|| Op11.getOpcode() == ISD::TargetConstant) {
// (add (SPUindirect <arg>, <const>), <const>) ->
// (SPUindirect <arg>, <const + const>)
ConstantSDNode *CN0 = cast<ConstantSDNode>(Op0);
ConstantSDNode *CN1 = cast<ConstantSDNode>(Op11);
- SDOperand combinedConst =
+ SDValue combinedConst =
DAG.getConstant(CN0->getValue() + CN1->getValue(),
Op0.getValueType());
@@ -2827,7 +2827,7 @@
case SPUISD::VEC_SRA:
case SPUISD::ROTQUAD_RZ_BYTES:
case SPUISD::ROTQUAD_RZ_BITS: {
- SDOperand Op1 = N->getOperand(1);
+ SDValue Op1 = N->getOperand(1);
if (isa<ConstantSDNode>(Op1)) {
// Kill degenerate vector shifts:
@@ -2849,9 +2849,9 @@
// (SPUpromote_scalar (any|sign|zero_extend (SPUextract_elt0 <arg>))) ->
// <arg>
// but only if the SPUpromote_scalar and <arg> types match.
- SDOperand Op00 = Op0.getOperand(0);
+ SDValue Op00 = Op0.getOperand(0);
if (Op00.getOpcode() == SPUISD::EXTRACT_ELT0) {
- SDOperand Op000 = Op00.getOperand(0);
+ SDValue Op000 = Op00.getOperand(0);
if (Op000.getValueType() == N->getValueType(0)) {
Result = Op000;
}
@@ -2932,7 +2932,7 @@
//! Compute used/known bits for a SPU operand
void
-SPUTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
+SPUTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
const APInt &Mask,
APInt &KnownZero,
APInt &KnownOne,
@@ -2955,7 +2955,7 @@
#endif
case SPUISD::PROMOTE_SCALAR: {
- SDOperand Op0 = Op.getOperand(0);
+ SDValue Op0 = Op.getOperand(0);
MVT Op0VT = Op0.getValueType();
unsigned Op0VTBits = Op0VT.getSizeInBits();
uint64_t InMask = Op0VT.getIntegerVTBitMask();
@@ -3007,9 +3007,9 @@
// LowerAsmOperandForConstraint
void
-SPUTargetLowering::LowerAsmOperandForConstraint(SDOperand Op,
+SPUTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
char ConstraintLetter,
- std::vector<SDOperand> &Ops,
+ std::vector<SDValue> &Ops,
SelectionDAG &DAG) const {
// Default, for the time being, to the base class handler
TargetLowering::LowerAsmOperandForConstraint(Op, ConstraintLetter, Ops, DAG);
Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h Sun Jul 27 16:46:04 2008
@@ -78,18 +78,18 @@
/// Predicates that are used for node matching:
namespace SPU {
- SDOperand get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
+ SDValue get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
MVT ValueType);
- SDOperand get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
+ SDValue get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
MVT ValueType);
- SDOperand get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
+ SDValue get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
MVT ValueType);
- SDOperand get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
+ SDValue get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
MVT ValueType);
- SDOperand get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG,
+ SDValue get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG,
MVT ValueType);
- SDOperand get_v4i32_imm(SDNode *N, SelectionDAG &DAG);
- SDOperand get_v2i64_imm(SDNode *N, SelectionDAG &DAG);
+ SDValue get_v4i32_imm(SDNode *N, SelectionDAG &DAG);
+ SDValue get_v2i64_imm(SDNode *N, SelectionDAG &DAG);
}
class SPUTargetMachine; // forward dec'l.
@@ -109,15 +109,15 @@
virtual const char *getTargetNodeName(unsigned Opcode) const;
/// getSetCCResultType - Return the ValueType for ISD::SETCC
- virtual MVT getSetCCResultType(const SDOperand &) const;
+ virtual MVT getSetCCResultType(const SDValue &) const;
/// LowerOperation - Provide custom lowering hooks for some operations.
///
- virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
+ virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
- virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
+ virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
- virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
+ virtual void computeMaskedBitsForTargetNode(const SDValue Op,
const APInt &Mask,
APInt &KnownZero,
APInt &KnownOne,
@@ -130,8 +130,8 @@
getRegForInlineAsmConstraint(const std::string &Constraint,
MVT VT) const;
- void LowerAsmOperandForConstraint(SDOperand Op, char ConstraintLetter,
- std::vector<SDOperand> &Ops,
+ void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
+ std::vector<SDValue> &Ops,
SelectionDAG &DAG) const;
/// isLegalAddressImmediate - Return true if the integer value can be used
Modified: llvm/trunk/lib/Target/CellSPU/SPUOperands.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUOperands.td?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUOperands.td (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUOperands.td Sun Jul 27 16:46:04 2008
@@ -16,7 +16,7 @@
}]>;
def LO16_vec : SDNodeXForm<scalar_to_vector, [{
- SDOperand OpVal(0, 0);
+ SDValue OpVal(0, 0);
// Transformation function: get the low 16 bit immediate from a build_vector
// node.
@@ -43,7 +43,7 @@
// Transformation function: shift the high 16 bit immediate from a build_vector
// node into the low 16 bits, and return a 16-bit constant.
def HI16_vec : SDNodeXForm<scalar_to_vector, [{
- SDOperand OpVal(0, 0);
+ SDValue OpVal(0, 0);
assert(N->getOpcode() == ISD::BUILD_VECTOR
&& "HI16_vec got something other than a BUILD_VECTOR");
Modified: llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp Sun Jul 27 16:46:04 2008
@@ -51,19 +51,19 @@
/// getI64Imm - Return a target constant with the specified value, of type
/// i64.
- inline SDOperand getI64Imm(uint64_t Imm) {
+ inline SDValue getI64Imm(uint64_t Imm) {
return CurDAG->getTargetConstant(Imm, MVT::i64);
}
/// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
/// base register. Return the virtual register that holds this value.
- // SDOperand getGlobalBaseReg(); TODO: hmm
+ // SDValue getGlobalBaseReg(); TODO: hmm
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
- SDNode *Select(SDOperand N);
+ SDNode *Select(SDValue N);
- SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
+ SDNode *SelectIntImmediateExpr(SDValue LHS, SDValue RHS,
unsigned OCHi, unsigned OCLo,
bool IsArithmetic = false,
bool Negate = false);
@@ -71,12 +71,12 @@
/// SelectCC - Select a comparison of the specified values with the
/// specified condition code, returning the CR# of the expression.
- SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
+ SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC);
/// SelectAddr - Given the specified address, return the two operands for a
/// load/store instruction, and return true if it should be an indexed [r+r]
/// operation.
- bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2);
+ bool SelectAddr(SDValue Addr, SDValue &Op1, SDValue &Op2);
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
@@ -90,7 +90,7 @@
#include "IA64GenDAGISel.inc"
private:
- SDNode *SelectDIV(SDOperand Op);
+ SDNode *SelectDIV(SDValue Op);
};
}
@@ -104,11 +104,11 @@
DAG.RemoveDeadNodes();
}
-SDNode *IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
+SDNode *IA64DAGToDAGISel::SelectDIV(SDValue Op) {
SDNode *N = Op.Val;
- SDOperand Chain = N->getOperand(0);
- SDOperand Tmp1 = N->getOperand(0);
- SDOperand Tmp2 = N->getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ SDValue Tmp1 = N->getOperand(0);
+ SDValue Tmp2 = N->getOperand(1);
AddToISelQueue(Chain);
AddToISelQueue(Tmp1);
@@ -133,40 +133,40 @@
// TODO: check for integer divides by powers of 2 (or other simple patterns?)
- SDOperand TmpPR, TmpPR2;
- SDOperand TmpF1, TmpF2, TmpF3, TmpF4, TmpF5, TmpF6, TmpF7, TmpF8;
- SDOperand TmpF9, TmpF10,TmpF11,TmpF12,TmpF13,TmpF14,TmpF15;
+ SDValue TmpPR, TmpPR2;
+ SDValue TmpF1, TmpF2, TmpF3, TmpF4, TmpF5, TmpF6, TmpF7, TmpF8;
+ SDValue TmpF9, TmpF10,TmpF11,TmpF12,TmpF13,TmpF14,TmpF15;
SDNode *Result;
// we'll need copies of F0 and F1
- SDOperand F0 = CurDAG->getRegister(IA64::F0, MVT::f64);
- SDOperand F1 = CurDAG->getRegister(IA64::F1, MVT::f64);
+ SDValue F0 = CurDAG->getRegister(IA64::F0, MVT::f64);
+ SDValue F1 = CurDAG->getRegister(IA64::F1, MVT::f64);
// OK, emit some code:
if(!isFP) {
// first, load the inputs into FP regs.
TmpF1 =
- SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp1), 0);
+ SDValue(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp1), 0);
Chain = TmpF1.getValue(1);
TmpF2 =
- SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp2), 0);
+ SDValue(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp2), 0);
Chain = TmpF2.getValue(1);
// next, convert the inputs to FP
if(isSigned) {
TmpF3 =
- SDOperand(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF1), 0);
+ SDValue(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF1), 0);
Chain = TmpF3.getValue(1);
TmpF4 =
- SDOperand(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2), 0);
+ SDValue(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2), 0);
Chain = TmpF4.getValue(1);
} else { // is unsigned
TmpF3 =
- SDOperand(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1), 0);
+ SDValue(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1), 0);
Chain = TmpF3.getValue(1);
TmpF4 =
- SDOperand(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2), 0);
+ SDValue(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2), 0);
Chain = TmpF4.getValue(1);
}
@@ -179,39 +179,39 @@
// we start by computing an approximate reciprocal (good to 9 bits?)
// note, this instruction writes _both_ TmpF5 (answer) and TmpPR (predicate)
if(isFP)
- TmpF5 = SDOperand(CurDAG->getTargetNode(IA64::FRCPAS0, MVT::f64, MVT::i1,
+ TmpF5 = SDValue(CurDAG->getTargetNode(IA64::FRCPAS0, MVT::f64, MVT::i1,
TmpF3, TmpF4), 0);
else
- TmpF5 = SDOperand(CurDAG->getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1,
+ TmpF5 = SDValue(CurDAG->getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1,
TmpF3, TmpF4), 0);
TmpPR = TmpF5.getValue(1);
Chain = TmpF5.getValue(2);
- SDOperand minusB;
+ SDValue minusB;
if(isModulus) { // for remainders, it'll be handy to have
// copies of -input_b
- minusB = SDOperand(CurDAG->getTargetNode(IA64::SUB, MVT::i64,
+ minusB = SDValue(CurDAG->getTargetNode(IA64::SUB, MVT::i64,
CurDAG->getRegister(IA64::r0, MVT::i64), Tmp2), 0);
Chain = minusB.getValue(1);
}
- SDOperand TmpE0, TmpY1, TmpE1, TmpY2;
+ SDValue TmpE0, TmpY1, TmpE1, TmpY2;
- SDOperand OpsE0[] = { TmpF4, TmpF5, F1, TmpPR };
- TmpE0 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
+ SDValue OpsE0[] = { TmpF4, TmpF5, F1, TmpPR };
+ TmpE0 = SDValue(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
OpsE0, 4), 0);
Chain = TmpE0.getValue(1);
- SDOperand OpsY1[] = { TmpF5, TmpE0, TmpF5, TmpPR };
- TmpY1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
+ SDValue OpsY1[] = { TmpF5, TmpE0, TmpF5, TmpPR };
+ TmpY1 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
OpsY1, 4), 0);
Chain = TmpY1.getValue(1);
- SDOperand OpsE1[] = { TmpE0, TmpE0, F0, TmpPR };
- TmpE1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
+ SDValue OpsE1[] = { TmpE0, TmpE0, F0, TmpPR };
+ TmpE1 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
OpsE1, 4), 0);
Chain = TmpE1.getValue(1);
- SDOperand OpsY2[] = { TmpY1, TmpE1, TmpY1, TmpPR };
- TmpY2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
+ SDValue OpsY2[] = { TmpY1, TmpE1, TmpY1, TmpPR };
+ TmpY2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
OpsY2, 4), 0);
Chain = TmpY2.getValue(1);
@@ -219,53 +219,53 @@
if(isModulus)
assert(0 && "Sorry, try another FORTRAN compiler.");
- SDOperand TmpE2, TmpY3, TmpQ0, TmpR0;
+ SDValue TmpE2, TmpY3, TmpQ0, TmpR0;
- SDOperand OpsE2[] = { TmpE1, TmpE1, F0, TmpPR };
- TmpE2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
+ SDValue OpsE2[] = { TmpE1, TmpE1, F0, TmpPR };
+ TmpE2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
OpsE2, 4), 0);
Chain = TmpE2.getValue(1);
- SDOperand OpsY3[] = { TmpY2, TmpE2, TmpY2, TmpPR };
- TmpY3 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
+ SDValue OpsY3[] = { TmpY2, TmpE2, TmpY2, TmpPR };
+ TmpY3 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
OpsY3, 4), 0);
Chain = TmpY3.getValue(1);
- SDOperand OpsQ0[] = { Tmp1, TmpY3, F0, TmpPR };
+ SDValue OpsQ0[] = { Tmp1, TmpY3, F0, TmpPR };
TmpQ0 =
- SDOperand(CurDAG->getTargetNode(IA64::CFMADS1, MVT::f64, // double prec!
+ SDValue(CurDAG->getTargetNode(IA64::CFMADS1, MVT::f64, // double prec!
OpsQ0, 4), 0);
Chain = TmpQ0.getValue(1);
- SDOperand OpsR0[] = { Tmp2, TmpQ0, Tmp1, TmpPR };
+ SDValue OpsR0[] = { Tmp2, TmpQ0, Tmp1, TmpPR };
TmpR0 =
- SDOperand(CurDAG->getTargetNode(IA64::CFNMADS1, MVT::f64, // double prec!
+ SDValue(CurDAG->getTargetNode(IA64::CFNMADS1, MVT::f64, // double prec!
OpsR0, 4), 0);
Chain = TmpR0.getValue(1);
// we want Result to have the same target register as the frcpa, so
// we two-address hack it. See the comment "for this to work..." on
// page 48 of Intel application note #245415
- SDOperand Ops[] = { TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR };
+ SDValue Ops[] = { TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR };
Result = CurDAG->getTargetNode(IA64::TCFMADS0, MVT::f64, // d.p. s0 rndg!
Ops, 5);
- Chain = SDOperand(Result, 1);
+ Chain = SDValue(Result, 1);
return Result; // XXX: early exit!
} else { // this is *not* an FP divide, so there's a bit left to do:
- SDOperand TmpQ2, TmpR2, TmpQ3, TmpQ;
+ SDValue TmpQ2, TmpR2, TmpQ3, TmpQ;
- SDOperand OpsQ2[] = { TmpF3, TmpY2, F0, TmpPR };
- TmpQ2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
+ SDValue OpsQ2[] = { TmpF3, TmpY2, F0, TmpPR };
+ TmpQ2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
OpsQ2, 4), 0);
Chain = TmpQ2.getValue(1);
- SDOperand OpsR2[] = { TmpF4, TmpQ2, TmpF3, TmpPR };
- TmpR2 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
+ SDValue OpsR2[] = { TmpF4, TmpQ2, TmpF3, TmpPR };
+ TmpR2 = SDValue(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
OpsR2, 4), 0);
Chain = TmpR2.getValue(1);
// we want TmpQ3 to have the same target register as the frcpa? maybe we
// should two-address hack it. See the comment "for this to work..." on page
// 48 of Intel application note #245415
- SDOperand OpsQ3[] = { TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR };
- TmpQ3 = SDOperand(CurDAG->getTargetNode(IA64::TCFMAS1, MVT::f64,
+ SDValue OpsQ3[] = { TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR };
+ TmpQ3 = SDValue(CurDAG->getTargetNode(IA64::TCFMAS1, MVT::f64,
OpsQ3, 5), 0);
Chain = TmpQ3.getValue(1);
@@ -274,27 +274,27 @@
// arguments. Other fun bugs may also appear, e.g. 0/x = x, not 0.
if(isSigned)
- TmpQ = SDOperand(CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1,
+ TmpQ = SDValue(CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1,
MVT::f64, TmpQ3), 0);
else
- TmpQ = SDOperand(CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1,
+ TmpQ = SDValue(CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1,
MVT::f64, TmpQ3), 0);
Chain = TmpQ.getValue(1);
if(isModulus) {
- SDOperand FPminusB =
- SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, minusB), 0);
+ SDValue FPminusB =
+ SDValue(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, minusB), 0);
Chain = FPminusB.getValue(1);
- SDOperand Remainder =
- SDOperand(CurDAG->getTargetNode(IA64::XMAL, MVT::f64,
+ SDValue Remainder =
+ SDValue(CurDAG->getTargetNode(IA64::XMAL, MVT::f64,
TmpQ, FPminusB, TmpF1), 0);
Chain = Remainder.getValue(1);
Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, Remainder);
- Chain = SDOperand(Result, 1);
+ Chain = SDValue(Result, 1);
} else { // just an integer divide
Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, TmpQ);
- Chain = SDOperand(Result, 1);
+ Chain = SDValue(Result, 1);
}
return Result;
@@ -303,7 +303,7 @@
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
-SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
+SDNode *IA64DAGToDAGISel::Select(SDValue Op) {
SDNode *N = Op.Val;
if (N->isMachineOpcode())
return NULL; // Already selected.
@@ -312,8 +312,8 @@
default: break;
case IA64ISD::BRCALL: { // XXX: this is also a hack!
- SDOperand Chain = N->getOperand(0);
- SDOperand InFlag; // Null incoming flag value.
+ SDValue Chain = N->getOperand(0);
+ SDValue InFlag; // Null incoming flag value.
AddToISelQueue(Chain);
if(N->getNumOperands()==3) { // we have an incoming chain, callee and flag
@@ -322,7 +322,7 @@
}
unsigned CallOpcode;
- SDOperand CallOperand;
+ SDValue CallOperand;
// if we can call directly, do so
if (GlobalAddressSDNode *GASD =
@@ -338,22 +338,22 @@
// otherwise we need to load the function descriptor,
// load the branch target (function)'s entry point and GP,
// branch (call) then restore the GP
- SDOperand FnDescriptor = N->getOperand(1);
+ SDValue FnDescriptor = N->getOperand(1);
AddToISelQueue(FnDescriptor);
// load the branch target's entry point [mem] and
// GP value [mem+8]
- SDOperand targetEntryPoint=
- SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, MVT::Other,
+ SDValue targetEntryPoint=
+ SDValue(CurDAG->getTargetNode(IA64::LD8, MVT::i64, MVT::Other,
FnDescriptor, CurDAG->getEntryNode()), 0);
Chain = targetEntryPoint.getValue(1);
- SDOperand targetGPAddr=
- SDOperand(CurDAG->getTargetNode(IA64::ADDS, MVT::i64,
+ SDValue targetGPAddr=
+ SDValue(CurDAG->getTargetNode(IA64::ADDS, MVT::i64,
FnDescriptor,
CurDAG->getConstant(8, MVT::i64)), 0);
Chain = targetGPAddr.getValue(1);
- SDOperand targetGP =
- SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64,MVT::Other,
+ SDValue targetGP =
+ SDValue(CurDAG->getTargetNode(IA64::LD8, MVT::i64,MVT::Other,
targetGPAddr, CurDAG->getEntryNode()), 0);
Chain = targetGP.getValue(1);
@@ -368,14 +368,14 @@
// Finally, once everything is setup, emit the call itself
if(InFlag.Val)
- Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
+ Chain = SDValue(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
CallOperand, InFlag), 0);
else // there might be no arguments
- Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
+ Chain = SDValue(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
CallOperand, Chain), 0);
InFlag = Chain.getValue(1);
- std::vector<SDOperand> CallResults;
+ std::vector<SDValue> CallResults;
CallResults.push_back(Chain);
CallResults.push_back(InFlag);
@@ -386,7 +386,7 @@
}
case IA64ISD::GETFD: {
- SDOperand Input = N->getOperand(0);
+ SDValue Input = N->getOperand(0);
AddToISelQueue(Input);
return CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input);
}
@@ -399,9 +399,9 @@
return SelectDIV(Op);
case ISD::TargetConstantFP: {
- SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so..
+ SDValue Chain = CurDAG->getEntryNode(); // this is a constant, so..
- SDOperand V;
+ SDValue V;
ConstantFPSDNode* N2 = cast<ConstantFPSDNode>(N);
if (N2->getValueAPF().isPosZero()) {
V = CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64);
@@ -411,7 +411,7 @@
} else
assert(0 && "Unexpected FP constant!");
- ReplaceUses(SDOperand(N, 0), V);
+ ReplaceUses(SDValue(N, 0), V);
return 0;
}
@@ -429,7 +429,7 @@
// (ia64 doesn't need one)
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N);
Constant *C = CP->getConstVal();
- SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64,
+ SDValue CPI = CurDAG->getTargetConstantPool(C, MVT::i64,
CP->getAlignment());
return CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ?
CurDAG->getRegister(IA64::r1, MVT::i64), CPI);
@@ -437,9 +437,9 @@
case ISD::GlobalAddress: {
GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
- SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
- SDOperand Tmp =
- SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64,
+ SDValue GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
+ SDValue Tmp =
+ SDValue(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64,
CurDAG->getRegister(IA64::r1,
MVT::i64), GA), 0);
return CurDAG->getTargetNode(IA64::LD8, MVT::i64, MVT::Other, Tmp,
@@ -448,10 +448,10 @@
/* XXX
case ISD::ExternalSymbol: {
- SDOperand EA = CurDAG->getTargetExternalSymbol(
+ SDValue EA = CurDAG->getTargetExternalSymbol(
cast<ExternalSymbolSDNode>(N)->getSymbol(),
MVT::i64);
- SDOperand Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, MVT::i64,
+ SDValue Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, MVT::i64,
CurDAG->getRegister(IA64::r1,
MVT::i64),
EA);
@@ -461,8 +461,8 @@
case ISD::LOAD: { // FIXME: load -1, not 1, for bools?
LoadSDNode *LD = cast<LoadSDNode>(N);
- SDOperand Chain = LD->getChain();
- SDOperand Address = LD->getBasePtr();
+ SDValue Chain = LD->getChain();
+ SDValue Address = LD->getBasePtr();
AddToISelQueue(Chain);
AddToISelQueue(Address);
@@ -478,7 +478,7 @@
Opc = IA64::LD1; // first we load a byte, then compare for != 0
if(N->getValueType(0) == MVT::i1) { // XXX: early exit!
return CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
- SDOperand(CurDAG->getTargetNode(Opc, MVT::i64, Address), 0),
+ SDValue(CurDAG->getTargetNode(Opc, MVT::i64, Address), 0),
CurDAG->getRegister(IA64::r0, MVT::i64),
Chain);
}
@@ -501,8 +501,8 @@
case ISD::STORE: {
StoreSDNode *ST = cast<StoreSDNode>(N);
- SDOperand Address = ST->getBasePtr();
- SDOperand Chain = ST->getChain();
+ SDValue Address = ST->getBasePtr();
+ SDValue Chain = ST->getChain();
AddToISelQueue(Address);
AddToISelQueue(Chain);
@@ -513,13 +513,13 @@
case MVT::i1: { // this is a bool
Opc = IA64::ST1; // we store either 0 or 1 as a byte
// first load zero!
- SDOperand Initial = CurDAG->getCopyFromReg(Chain, IA64::r0, MVT::i64);
+ SDValue Initial = CurDAG->getCopyFromReg(Chain, IA64::r0, MVT::i64);
Chain = Initial.getValue(1);
// then load 1 into the same reg iff the predicate to store is 1
- SDOperand Tmp = ST->getValue();
+ SDValue Tmp = ST->getValue();
AddToISelQueue(Tmp);
Tmp =
- SDOperand(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial,
+ SDValue(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial,
CurDAG->getTargetConstant(1, MVT::i64),
Tmp), 0);
return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
@@ -537,16 +537,16 @@
}
}
- SDOperand N1 = N->getOperand(1);
- SDOperand N2 = N->getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
AddToISelQueue(N1);
AddToISelQueue(N2);
return CurDAG->SelectNodeTo(N, Opc, MVT::Other, N2, N1, Chain);
}
case ISD::BRCOND: {
- SDOperand Chain = N->getOperand(0);
- SDOperand CC = N->getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ SDValue CC = N->getOperand(1);
AddToISelQueue(Chain);
AddToISelQueue(CC);
MachineBasicBlock *Dest =
@@ -561,14 +561,14 @@
int64_t Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
- SDOperand N0 = N->getOperand(0);
+ SDValue N0 = N->getOperand(0);
AddToISelQueue(N0);
return CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0);
}
case ISD::BR:
// FIXME: we don't need long branches all the time!
- SDOperand N0 = N->getOperand(0);
+ SDValue N0 = N->getOperand(0);
AddToISelQueue(N0);
return CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other,
N->getOperand(1), N0);
Modified: llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp Sun Jul 27 16:46:04 2008
@@ -140,12 +140,12 @@
}
}
-MVT IA64TargetLowering::getSetCCResultType(const SDOperand &) const {
+MVT IA64TargetLowering::getSetCCResultType(const SDValue &) const {
return MVT::i1;
}
void IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
- SmallVectorImpl<SDOperand> &ArgValues) {
+ SmallVectorImpl<SDValue> &ArgValues) {
//
// add beautiful description of IA64 stack frame format
// here (from intel 24535803.pdf most likely)
@@ -177,7 +177,7 @@
for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I)
{
- SDOperand newroot, argt;
+ SDValue newroot, argt;
if(count < 8) { // need to fix this logic? maybe.
switch (getValueType(I->getType()).getSimpleVT()) {
@@ -229,7 +229,7 @@
// Create the SelectionDAG nodes corresponding to a load
//from this parameter
- SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
+ SDValue FIN = DAG.getFrameIndex(FI, MVT::i64);
argt = newroot = DAG.getLoad(getValueType(I->getType()),
DAG.getEntryNode(), FIN, NULL, 0);
}
@@ -302,11 +302,11 @@
}
}
-std::pair<SDOperand, SDOperand>
-IA64TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
+std::pair<SDValue, SDValue>
+IA64TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
bool RetSExt, bool RetZExt,
bool isVarArg, unsigned CallingConv,
- bool isTailCall, SDOperand Callee,
+ bool isTailCall, SDValue Callee,
ArgListTy &Args, SelectionDAG &DAG) {
MachineFunction &MF = DAG.getMachineFunction();
@@ -335,17 +335,17 @@
Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
- SDOperand StackPtr;
- std::vector<SDOperand> Stores;
- std::vector<SDOperand> Converts;
- std::vector<SDOperand> RegValuesToPass;
+ SDValue StackPtr;
+ std::vector<SDValue> Stores;
+ std::vector<SDValue> Converts;
+ std::vector<SDValue> RegValuesToPass;
unsigned ArgOffset = 16;
for (unsigned i = 0, e = Args.size(); i != e; ++i)
{
- SDOperand Val = Args[i].Node;
+ SDValue Val = Args[i].Node;
MVT ObjectVT = Val.getValueType();
- SDOperand ValToStore(0, 0), ValToConvert(0, 0);
+ SDValue ValToStore(0, 0), ValToConvert(0, 0);
unsigned ObjSize=8;
switch (ObjectVT.getSimpleVT()) {
default: assert(0 && "unexpected argument type!");
@@ -391,7 +391,7 @@
if(!StackPtr.Val) {
StackPtr = DAG.getRegister(IA64::r12, MVT::i64);
}
- SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
+ SDValue PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
PtrOff = DAG.getNode(ISD::ADD, MVT::i64, StackPtr, PtrOff);
Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0));
ArgOffset += ObjSize;
@@ -416,16 +416,16 @@
IA64::F12, IA64::F13, IA64::F14, IA64::F15
};
- SDOperand InFlag;
+ SDValue InFlag;
// save the current GP, SP and RP : FIXME: do we need to do all 3 always?
- SDOperand GPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r1, MVT::i64, InFlag);
+ SDValue GPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r1, MVT::i64, InFlag);
Chain = GPBeforeCall.getValue(1);
InFlag = Chain.getValue(2);
- SDOperand SPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r12, MVT::i64, InFlag);
+ SDValue SPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r12, MVT::i64, InFlag);
Chain = SPBeforeCall.getValue(1);
InFlag = Chain.getValue(2);
- SDOperand RPBeforeCall = DAG.getCopyFromReg(Chain, IA64::rp, MVT::i64, InFlag);
+ SDValue RPBeforeCall = DAG.getCopyFromReg(Chain, IA64::rp, MVT::i64, InFlag);
Chain = RPBeforeCall.getValue(1);
InFlag = Chain.getValue(2);
@@ -464,7 +464,7 @@
*/
std::vector<MVT> NodeTys;
- std::vector<SDOperand> CallOperands;
+ std::vector<SDValue> CallOperands;
NodeTys.push_back(MVT::Other); // Returns a chain
NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
CallOperands.push_back(Chain);
@@ -494,17 +494,17 @@
RetVals.push_back(MVT::Flag);
MVT RetTyVT = getValueType(RetTy);
- SDOperand RetVal;
+ SDValue RetVal;
if (RetTyVT != MVT::isVoid) {
switch (RetTyVT.getSimpleVT()) {
default: assert(0 && "Unknown value type to return!");
case MVT::i1: { // bools are just like other integers (returned in r8)
// we *could* fall through to the truncate below, but this saves a
// few redundant predicate ops
- SDOperand boolInR8 = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64,InFlag);
+ SDValue boolInR8 = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64,InFlag);
InFlag = boolInR8.getValue(2);
Chain = boolInR8.getValue(1);
- SDOperand zeroReg = DAG.getCopyFromReg(Chain, IA64::r0, MVT::i64, InFlag);
+ SDValue zeroReg = DAG.getCopyFromReg(Chain, IA64::r0, MVT::i64, InFlag);
InFlag = zeroReg.getValue(2);
Chain = zeroReg.getValue(1);
@@ -546,18 +546,18 @@
Chain = DAG.getCALLSEQ_END(Chain,
DAG.getConstant(NumBytes, getPointerTy()),
DAG.getConstant(0, getPointerTy()),
- SDOperand());
+ SDValue());
return std::make_pair(RetVal, Chain);
}
-SDOperand IA64TargetLowering::
-LowerOperation(SDOperand Op, SelectionDAG &DAG) {
+SDValue IA64TargetLowering::
+LowerOperation(SDValue Op, SelectionDAG &DAG) {
switch (Op.getOpcode()) {
default: assert(0 && "Should not custom lower this!");
case ISD::GlobalTLSAddress:
assert(0 && "TLS not implemented for IA64.");
case ISD::RET: {
- SDOperand AR_PFSVal, Copy;
+ SDValue AR_PFSVal, Copy;
switch(Op.getNumOperands()) {
default:
@@ -575,22 +575,22 @@
AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), VirtGPR, MVT::i64);
Copy = DAG.getCopyToReg(AR_PFSVal.getValue(1), ArgReg, Op.getOperand(1),
- SDOperand());
+ SDValue());
AR_PFSVal = DAG.getCopyToReg(Copy.getValue(0), IA64::AR_PFS, AR_PFSVal,
Copy.getValue(1));
return DAG.getNode(IA64ISD::RET_FLAG, MVT::Other,
AR_PFSVal, AR_PFSVal.getValue(1));
}
}
- return SDOperand();
+ return SDValue();
}
case ISD::VAARG: {
MVT VT = getPointerTy();
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
- SDOperand VAList = DAG.getLoad(VT, Op.getOperand(0), Op.getOperand(1),
+ SDValue VAList = DAG.getLoad(VT, Op.getOperand(0), Op.getOperand(1),
SV, 0);
// Increment the pointer, VAList, to the next vaarg
- SDOperand VAIncr = DAG.getNode(ISD::ADD, VT, VAList,
+ SDValue VAIncr = DAG.getNode(ISD::ADD, VT, VAList,
DAG.getConstant(VT.getSizeInBits()/8,
VT));
// Store the incremented VAList to the legalized pointer
@@ -602,7 +602,7 @@
case ISD::VASTART: {
// vastart just stores the address of the VarArgsFrameIndex slot into the
// memory location argument.
- SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64);
+ SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64);
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0);
}
@@ -610,5 +610,5 @@
case ISD::RETURNADDR: break;
case ISD::FRAMEADDR: break;
}
- return SDOperand();
+ return SDValue();
}
Modified: llvm/trunk/lib/Target/IA64/IA64ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64ISelLowering.h?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/Target/IA64/IA64ISelLowering.h (original)
+++ llvm/trunk/lib/Target/IA64/IA64ISelLowering.h Sun Jul 27 16:46:04 2008
@@ -49,24 +49,24 @@
const char *getTargetNodeName(unsigned Opcode) const;
/// getSetCCResultType: return ISD::SETCC's result type.
- virtual MVT getSetCCResultType(const SDOperand &) const;
+ virtual MVT getSetCCResultType(const SDValue &) const;
/// LowerArguments - This hook must be implemented to indicate how we should
/// lower the arguments for the specified function, into the specified DAG.
virtual void LowerArguments(Function &F, SelectionDAG &DAG,
- SmallVectorImpl<SDOperand> &ArgValues);
+ SmallVectorImpl<SDValue> &ArgValues);
/// LowerCallTo - This hook lowers an abstract call to a function into an
/// actual call.
- virtual std::pair<SDOperand, SDOperand>
- LowerCallTo(SDOperand Chain, const Type *RetTy,
+ virtual std::pair<SDValue, SDValue>
+ LowerCallTo(SDValue Chain, const Type *RetTy,
bool RetSExt, bool RetZExt, bool isVarArg,
unsigned CC, bool isTailCall,
- SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
+ SDValue Callee, ArgListTy &Args, SelectionDAG &DAG);
/// LowerOperation - for custom lowering specific ops
/// (currently, only "ret void")
- virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
+ virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
};
}
Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Sun Jul 27 16:46:04 2008
@@ -78,17 +78,17 @@
// Include the pieces autogenerated from the target description.
#include "MipsGenDAGISel.inc"
- SDOperand getGlobalBaseReg();
- SDNode *Select(SDOperand N);
+ SDValue getGlobalBaseReg();
+ SDNode *Select(SDValue N);
// Complex Pattern.
- bool SelectAddr(SDOperand Op, SDOperand N,
- SDOperand &Base, SDOperand &Offset);
+ bool SelectAddr(SDValue Op, SDValue N,
+ SDValue &Base, SDValue &Offset);
// getI32Imm - Return a target constant with the specified
// value, of type i32.
- inline SDOperand getI32Imm(unsigned Imm) {
+ inline SDValue getI32Imm(unsigned Imm) {
return CurDAG->getTargetConstant(Imm, MVT::i32);
}
@@ -124,7 +124,7 @@
/// getGlobalBaseReg - Output the instructions required to put the
/// GOT address into a register.
-SDOperand MipsDAGToDAGISel::getGlobalBaseReg() {
+SDValue MipsDAGToDAGISel::getGlobalBaseReg() {
MachineFunction* MF = BB->getParent();
unsigned GP = 0;
for(MachineRegisterInfo::livein_iterator ii = MF->getRegInfo().livein_begin(),
@@ -141,7 +141,7 @@
/// ComplexPattern used on MipsInstrInfo
/// Used on Mips Load/Store instructions
bool MipsDAGToDAGISel::
-SelectAddr(SDOperand Op, SDOperand Addr, SDOperand &Offset, SDOperand &Base)
+SelectAddr(SDValue Op, SDValue Addr, SDValue &Offset, SDValue &Base)
{
// if Address is FI, get the TargetFrameIndex.
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
@@ -191,7 +191,7 @@
/// Select instructions not customized! Used for
/// expanded, promoted and normal instructions
SDNode* MipsDAGToDAGISel::
-Select(SDOperand N)
+Select(SDValue N)
{
SDNode *Node = N.Val;
unsigned Opcode = Node->getOpcode();
@@ -225,7 +225,7 @@
case ISD::SUBE:
case ISD::ADDE: {
- SDOperand InFlag = Node->getOperand(2), CmpLHS;
+ SDValue InFlag = Node->getOperand(2), CmpLHS;
unsigned Opc = InFlag.getOpcode(), MOp;
assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
@@ -240,20 +240,20 @@
MOp = Mips::SUBu;
}
- SDOperand Ops[] = { CmpLHS, InFlag.getOperand(1) };
+ SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
- SDOperand LHS = Node->getOperand(0);
- SDOperand RHS = Node->getOperand(1);
+ SDValue LHS = Node->getOperand(0);
+ SDValue RHS = Node->getOperand(1);
AddToISelQueue(LHS);
AddToISelQueue(RHS);
MVT VT = LHS.getValueType();
SDNode *Carry = CurDAG->getTargetNode(Mips::SLTu, VT, Ops, 2);
SDNode *AddCarry = CurDAG->getTargetNode(Mips::ADDu, VT,
- SDOperand(Carry,0), RHS);
+ SDValue(Carry,0), RHS);
return CurDAG->SelectNodeTo(N.Val, MOp, VT, MVT::Flag,
- LHS, SDOperand(AddCarry,0));
+ LHS, SDValue(AddCarry,0));
}
/// Mul/Div with two results
@@ -261,8 +261,8 @@
case ISD::UDIVREM:
case ISD::SMUL_LOHI:
case ISD::UMUL_LOHI: {
- SDOperand Op1 = Node->getOperand(0);
- SDOperand Op2 = Node->getOperand(1);
+ SDValue Op1 = Node->getOperand(0);
+ SDValue Op2 = Node->getOperand(1);
AddToISelQueue(Op1);
AddToISelQueue(Op2);
@@ -274,17 +274,17 @@
SDNode *Node = CurDAG->getTargetNode(Op, MVT::Flag, Op1, Op2);
- SDOperand InFlag = SDOperand(Node, 0);
+ SDValue InFlag = SDValue(Node, 0);
SDNode *Lo = CurDAG->getTargetNode(Mips::MFLO, MVT::i32,
MVT::Flag, InFlag);
- InFlag = SDOperand(Lo,1);
+ InFlag = SDValue(Lo,1);
SDNode *Hi = CurDAG->getTargetNode(Mips::MFHI, MVT::i32, InFlag);
if (!N.getValue(0).use_empty())
- ReplaceUses(N.getValue(0), SDOperand(Lo,0));
+ ReplaceUses(N.getValue(0), SDValue(Lo,0));
if (!N.getValue(1).use_empty())
- ReplaceUses(N.getValue(1), SDOperand(Hi,0));
+ ReplaceUses(N.getValue(1), SDValue(Hi,0));
return NULL;
}
@@ -293,15 +293,15 @@
case ISD::MUL:
case ISD::MULHS:
case ISD::MULHU: {
- SDOperand MulOp1 = Node->getOperand(0);
- SDOperand MulOp2 = Node->getOperand(1);
+ SDValue MulOp1 = Node->getOperand(0);
+ SDValue MulOp2 = Node->getOperand(1);
AddToISelQueue(MulOp1);
AddToISelQueue(MulOp2);
unsigned MulOp = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
SDNode *MulNode = CurDAG->getTargetNode(MulOp, MVT::Flag, MulOp1, MulOp2);
- SDOperand InFlag = SDOperand(MulNode, 0);
+ SDValue InFlag = SDValue(MulNode, 0);
if (MulOp == ISD::MUL)
return CurDAG->getTargetNode(Mips::MFLO, MVT::i32, InFlag);
@@ -314,8 +314,8 @@
case ISD::UREM:
case ISD::SDIV:
case ISD::UDIV: {
- SDOperand Op1 = Node->getOperand(0);
- SDOperand Op2 = Node->getOperand(1);
+ SDValue Op1 = Node->getOperand(0);
+ SDValue Op2 = Node->getOperand(1);
AddToISelQueue(Op1);
AddToISelQueue(Op2);
@@ -329,13 +329,13 @@
}
SDNode *Node = CurDAG->getTargetNode(Op, MVT::Flag, Op1, Op2);
- SDOperand InFlag = SDOperand(Node, 0);
+ SDValue InFlag = SDValue(Node, 0);
return CurDAG->getTargetNode(MOp, MVT::i32, InFlag);
}
// Get target GOT address.
case ISD::GLOBAL_OFFSET_TABLE: {
- SDOperand Result = getGlobalBaseReg();
+ SDValue Result = getGlobalBaseReg();
ReplaceUses(N, Result);
return NULL;
}
@@ -347,21 +347,21 @@
case MipsISD::JmpLink: {
if (TM.getRelocationModel() == Reloc::PIC_) {
//bool isCodeLarge = (TM.getCodeModel() == CodeModel::Large);
- SDOperand Chain = Node->getOperand(0);
- SDOperand Callee = Node->getOperand(1);
+ SDValue Chain = Node->getOperand(0);
+ SDValue Callee = Node->getOperand(1);
AddToISelQueue(Chain);
- SDOperand T9Reg = CurDAG->getRegister(Mips::T9, MVT::i32);
- SDOperand InFlag(0, 0);
+ SDValue T9Reg = CurDAG->getRegister(Mips::T9, MVT::i32);
+ SDValue InFlag(0, 0);
if ( (isa<GlobalAddressSDNode>(Callee)) ||
(isa<ExternalSymbolSDNode>(Callee)) )
{
/// Direct call for global addresses and external symbols
- SDOperand GPReg = CurDAG->getRegister(Mips::GP, MVT::i32);
+ SDValue GPReg = CurDAG->getRegister(Mips::GP, MVT::i32);
// Use load to get GOT target
- SDOperand Ops[] = { Callee, GPReg, Chain };
- SDOperand Load = SDOperand(CurDAG->getTargetNode(Mips::LW, MVT::i32,
+ SDValue Ops[] = { Callee, GPReg, Chain };
+ SDValue Load = SDValue(CurDAG->getTargetNode(Mips::LW, MVT::i32,
MVT::Other, Ops, 3), 0);
Chain = Load.getValue(1);
AddToISelQueue(Chain);
@@ -377,10 +377,10 @@
// Emit Jump and Link Register
SDNode *ResNode = CurDAG->getTargetNode(Mips::JALR, MVT::Other,
MVT::Flag, T9Reg, Chain);
- Chain = SDOperand(ResNode, 0);
- InFlag = SDOperand(ResNode, 1);
- ReplaceUses(SDOperand(Node, 0), Chain);
- ReplaceUses(SDOperand(Node, 1), InFlag);
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ ReplaceUses(SDValue(Node, 0), Chain);
+ ReplaceUses(SDValue(Node, 1), InFlag);
return ResNode;
}
}
Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Sun Jul 27 16:46:04 2008
@@ -132,13 +132,13 @@
}
-MVT MipsTargetLowering::getSetCCResultType(const SDOperand &) const {
+MVT MipsTargetLowering::getSetCCResultType(const SDValue &) const {
return MVT::i32;
}
-SDOperand MipsTargetLowering::
-LowerOperation(SDOperand Op, SelectionDAG &DAG)
+SDValue MipsTargetLowering::
+LowerOperation(SDValue Op, SelectionDAG &DAG)
{
switch (Op.getOpcode())
{
@@ -151,7 +151,7 @@
case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
}
- return SDOperand();
+ return SDValue();
}
MachineBasicBlock *
@@ -268,105 +268,105 @@
//===----------------------------------------------------------------------===//
// Misc Lower Operation implementation
//===----------------------------------------------------------------------===//
-SDOperand MipsTargetLowering::
-LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG)
+SDValue MipsTargetLowering::
+LowerGlobalAddress(SDValue Op, SelectionDAG &DAG)
{
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
- SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
+ SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
if (!Subtarget->hasABICall()) {
if (isa<Function>(GV)) return GA;
const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
- SDOperand Ops[] = { GA };
+ SDValue Ops[] = { GA };
if (IsGlobalInSmallSection(GV)) { // %gp_rel relocation
- SDOperand GPRelNode = DAG.getNode(MipsISD::GPRel, VTs, 1, Ops, 1);
- SDOperand GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32);
+ SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, VTs, 1, Ops, 1);
+ SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32);
return DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
}
// %hi/%lo relocation
- SDOperand HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
- SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
+ SDValue HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
+ SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
return DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
} else { // Abicall relocations, TODO: make this cleaner.
- SDOperand ResNode = DAG.getLoad(MVT::i32, DAG.getEntryNode(), GA, NULL, 0);
+ SDValue ResNode = DAG.getLoad(MVT::i32, DAG.getEntryNode(), GA, NULL, 0);
// On functions and global targets not internal linked only
// a load from got/GP is necessary for PIC to work.
if (!GV->hasInternalLinkage() || isa<Function>(GV))
return ResNode;
- SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
+ SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
return DAG.getNode(ISD::ADD, MVT::i32, ResNode, Lo);
}
assert(0 && "Dont know how to handle GlobalAddress");
- return SDOperand(0,0);
+ return SDValue(0,0);
}
-SDOperand MipsTargetLowering::
-LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG)
+SDValue MipsTargetLowering::
+LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG)
{
assert(0 && "TLS not implemented for MIPS.");
- return SDOperand(); // Not reached
+ return SDValue(); // Not reached
}
-SDOperand MipsTargetLowering::
-LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG)
+SDValue MipsTargetLowering::
+LowerSELECT_CC(SDValue Op, SelectionDAG &DAG)
{
- SDOperand LHS = Op.getOperand(0);
- SDOperand RHS = Op.getOperand(1);
- SDOperand True = Op.getOperand(2);
- SDOperand False = Op.getOperand(3);
- SDOperand CC = Op.getOperand(4);
+ SDValue LHS = Op.getOperand(0);
+ SDValue RHS = Op.getOperand(1);
+ SDValue True = Op.getOperand(2);
+ SDValue False = Op.getOperand(3);
+ SDValue CC = Op.getOperand(4);
const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
- SDOperand Ops[] = { LHS, RHS, CC };
- SDOperand SetCCRes = DAG.getNode(ISD::SETCC, VTs, 1, Ops, 3);
+ SDValue Ops[] = { LHS, RHS, CC };
+ SDValue SetCCRes = DAG.getNode(ISD::SETCC, VTs, 1, Ops, 3);
return DAG.getNode(MipsISD::SelectCC, True.getValueType(),
SetCCRes, True, False);
}
-SDOperand MipsTargetLowering::
-LowerJumpTable(SDOperand Op, SelectionDAG &DAG)
+SDValue MipsTargetLowering::
+LowerJumpTable(SDValue Op, SelectionDAG &DAG)
{
- SDOperand ResNode;
- SDOperand HiPart;
+ SDValue ResNode;
+ SDValue HiPart;
MVT PtrVT = Op.getValueType();
JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
- SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
+ SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
- SDOperand Ops[] = { JTI };
+ SDValue Ops[] = { JTI };
HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
} else // Emit Load from Global Pointer
HiPart = DAG.getLoad(MVT::i32, DAG.getEntryNode(), JTI, NULL, 0);
- SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, JTI);
+ SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, JTI);
ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
return ResNode;
}
-SDOperand MipsTargetLowering::
-LowerConstantPool(SDOperand Op, SelectionDAG &DAG)
+SDValue MipsTargetLowering::
+LowerConstantPool(SDValue Op, SelectionDAG &DAG)
{
- SDOperand ResNode;
+ SDValue ResNode;
ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
Constant *C = N->getConstVal();
- SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
+ SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
// gp_rel relocation
if (!Subtarget->hasABICall() &&
IsInSmallSection(getTargetData()->getABITypeSize(C->getType()))) {
- SDOperand GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
- SDOperand GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32);
+ SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
+ SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32);
ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
} else { // %hi/%lo relocation
- SDOperand HiPart = DAG.getNode(MipsISD::Hi, MVT::i32, CP);
- SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, CP);
+ SDValue HiPart = DAG.getNode(MipsISD::Hi, MVT::i32, CP);
+ SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, CP);
ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
}
@@ -391,8 +391,8 @@
//===----------------------------------------------------------------------===//
/// Mips custom CALL implementation
-SDOperand MipsTargetLowering::
-LowerCALL(SDOperand Op, SelectionDAG &DAG)
+SDValue MipsTargetLowering::
+LowerCALL(SDValue Op, SelectionDAG &DAG)
{
unsigned CallingConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
@@ -410,13 +410,13 @@
/// regs to (physical regs)/(stack frame), CALLSEQ_START and
/// CALLSEQ_END are emitted.
/// TODO: isVarArg, isTailCall.
-SDOperand MipsTargetLowering::
-LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC)
+SDValue MipsTargetLowering::
+LowerCCCCallTo(SDValue Op, SelectionDAG &DAG, unsigned CC)
{
MachineFunction &MF = DAG.getMachineFunction();
- SDOperand Chain = Op.getOperand(0);
- SDOperand Callee = Op.getOperand(4);
+ SDValue Chain = Op.getOperand(0);
+ SDValue Callee = Op.getOperand(4);
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
MachineFrameInfo *MFI = MF.getFrameInfo();
@@ -440,8 +440,8 @@
getPointerTy()));
// With EABI is it possible to have 16 args on registers.
- SmallVector<std::pair<unsigned, SDOperand>, 16> RegsToPass;
- SmallVector<SDOperand, 8> MemOpChains;
+ SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
+ SmallVector<SDValue, 8> MemOpChains;
// First/LastArgStackLoc contains the first/last
// "at stack" argument location.
@@ -453,7 +453,7 @@
CCValAssign &VA = ArgLocs[i];
// Arguments start after the 5 first operands of ISD::CALL
- SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
+ SDValue Arg = Op.getOperand(5+2*VA.getValNo());
// Promote the value if needed.
switch (VA.getLocInfo()) {
@@ -488,7 +488,7 @@
int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
LastArgStackLoc);
- SDOperand PtrOff = DAG.getFrameIndex(FI,getPointerTy());
+ SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
// emit ISD::STORE whichs stores the
// parameter value to a stack Location
@@ -505,7 +505,7 @@
// chain and flag operands which copy the outgoing args into registers.
// The InFlag in necessary since all emited instructions must be
// stuck together.
- SDOperand InFlag;
+ SDValue InFlag;
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first,
RegsToPass[i].second, InFlag);
@@ -526,7 +526,7 @@
//
// Returns a chain & a flag for retval copy to use.
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
- SmallVector<SDOperand, 8> Ops;
+ SmallVector<SDValue, 8> Ops;
Ops.push_back(Chain);
Ops.push_back(Callee);
@@ -570,17 +570,17 @@
// Reload GP value.
FI = MipsFI->getGPFI();
- SDOperand FIN = DAG.getFrameIndex(FI,getPointerTy());
- SDOperand GPLoad = DAG.getLoad(MVT::i32, Chain, FIN, NULL, 0);
+ SDValue FIN = DAG.getFrameIndex(FI,getPointerTy());
+ SDValue GPLoad = DAG.getLoad(MVT::i32, Chain, FIN, NULL, 0);
Chain = GPLoad.getValue(1);
Chain = DAG.getCopyToReg(Chain, DAG.getRegister(Mips::GP, MVT::i32),
- GPLoad, SDOperand(0,0));
+ GPLoad, SDValue(0,0));
InFlag = Chain.getValue(1);
}
// Handle result values, copying them out of physregs into vregs that we
// return.
- return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
+ return SDValue(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
}
/// LowerCallResult - Lower the result values of an ISD::CALL into the
@@ -589,7 +589,7 @@
/// being lowered. Returns a SDNode with the same number of values as the
/// ISD::CALL.
SDNode *MipsTargetLowering::
-LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
+LowerCallResult(SDValue Chain, SDValue InFlag, SDNode *TheCall,
unsigned CallingConv, SelectionDAG &DAG) {
bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
@@ -599,7 +599,7 @@
CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips);
- SmallVector<SDOperand, 8> ResultVals;
+ SmallVector<SDValue, 8> ResultVals;
// Copy all of the result registers out of their specified physreg.
for (unsigned i = 0; i != RVLocs.size(); ++i) {
@@ -621,8 +621,8 @@
//===----------------------------------------------------------------------===//
/// Mips custom FORMAL_ARGUMENTS implementation
-SDOperand MipsTargetLowering::
-LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG)
+SDValue MipsTargetLowering::
+LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG)
{
unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
switch(CC)
@@ -638,10 +638,10 @@
/// virtual registers and generate load operations for
/// arguments places on the stack.
/// TODO: isVarArg
-SDOperand MipsTargetLowering::
-LowerCCCArguments(SDOperand Op, SelectionDAG &DAG)
+SDValue MipsTargetLowering::
+LowerCCCArguments(SDValue Op, SelectionDAG &DAG)
{
- SDOperand Root = Op.getOperand(0);
+ SDValue Root = Op.getOperand(0);
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo();
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
@@ -659,8 +659,8 @@
CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
CCInfo.AnalyzeFormalArguments(Op.Val, CC_Mips);
- SmallVector<SDOperand, 16> ArgValues;
- SDOperand StackPtr;
+ SmallVector<SDValue, 16> ArgValues;
+ SDValue StackPtr;
unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
@@ -689,7 +689,7 @@
// Transform the arguments stored on
// physical registers into virtual ones
unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
- SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
+ SDValue ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
// If this is an 8 or 16-bit value, it is really passed promoted
// to 32 bits. Insert an assert[sz]ext to capture this, then
@@ -722,7 +722,7 @@
// Arguments are always 32-bit.
int FI = MFI->CreateFixedObject(4, 0);
MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4)));
- SDOperand PtrOff = DAG.getFrameIndex(FI, getPointerTy());
+ SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
// emit ISD::STORE whichs stores the
// parameter value to a stack Location
@@ -748,7 +748,7 @@
(FirstStackArgLoc + VA.getLocMemOffset())));
// Create load nodes to retrieve arguments from the stack
- SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
+ SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
}
}
@@ -762,7 +762,7 @@
Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
MipsFI->setSRetReturnReg(Reg);
}
- SDOperand Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]);
+ SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]);
Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root);
}
@@ -777,8 +777,8 @@
// Return Value Calling Convention Implementation
//===----------------------------------------------------------------------===//
-SDOperand MipsTargetLowering::
-LowerRET(SDOperand Op, SelectionDAG &DAG)
+SDValue MipsTargetLowering::
+LowerRET(SDValue Op, SelectionDAG &DAG)
{
// CCValAssign - represent the assignment of
// the return value to a location
@@ -801,8 +801,8 @@
}
// The chain is always operand #0
- SDOperand Chain = Op.getOperand(0);
- SDOperand Flag;
+ SDValue Chain = Op.getOperand(0);
+ SDValue Flag;
// Copy the result values into the output registers.
for (unsigned i = 0; i != RVLocs.size(); ++i) {
@@ -829,7 +829,7 @@
if (!Reg)
assert(0 && "sret virtual register not created in the entry block");
- SDOperand Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy());
+ SDValue Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy());
Chain = DAG.getCopyToReg(Chain, Mips::V0, Val, Flag);
Flag = Chain.getValue(1);
Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.h?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.h Sun Jul 27 16:46:04 2008
@@ -66,36 +66,36 @@
explicit MipsTargetLowering(MipsTargetMachine &TM);
/// LowerOperation - Provide custom lowering hooks for some operations.
- virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
+ virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
/// getTargetNodeName - This method returns the name of a target specific
// DAG node.
virtual const char *getTargetNodeName(unsigned Opcode) const;
/// getSetCCResultType - get the ISD::SETCC result ValueType
- MVT getSetCCResultType(const SDOperand &) const;
+ MVT getSetCCResultType(const SDValue &) const;
private:
// Subtarget Info
const MipsSubtarget *Subtarget;
// Lower Operand helpers
- SDOperand LowerCCCArguments(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC);
- SDNode *LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode*TheCall,
+ SDValue LowerCCCArguments(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerCCCCallTo(SDValue Op, SelectionDAG &DAG, unsigned CC);
+ SDNode *LowerCallResult(SDValue Chain, SDValue InFlag, SDNode*TheCall,
unsigned CallingConv, SelectionDAG &DAG);
bool IsGlobalInSmallSection(GlobalValue *GV);
bool IsInSmallSection(unsigned Size);
// Lower Operand specifics
- SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG);
+ SDValue LowerRET(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerCALL(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *MBB);
Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp Sun Jul 27 16:46:04 2008
@@ -71,20 +71,20 @@
// Include the pieces autogenerated from the target description.
#include "PIC16GenDAGISel.inc"
- SDNode *Select(SDOperand N);
+ SDNode *Select(SDValue N);
// Select addressing mode. currently assume base + offset addr mode.
- bool SelectAM(SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Offset);
- bool SelectDirectAM(SDOperand Op, SDOperand N, SDOperand &Base,
- SDOperand &Offset);
- bool StoreInDirectAM(SDOperand Op, SDOperand N, SDOperand &fsr);
- bool LoadFSR(SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Offset);
- bool LoadNothing(SDOperand Op, SDOperand N, SDOperand &Base,
- SDOperand &Offset);
+ bool SelectAM(SDValue Op, SDValue N, SDValue &Base, SDValue &Offset);
+ bool SelectDirectAM(SDValue Op, SDValue N, SDValue &Base,
+ SDValue &Offset);
+ bool StoreInDirectAM(SDValue Op, SDValue N, SDValue &fsr);
+ bool LoadFSR(SDValue Op, SDValue N, SDValue &Base, SDValue &Offset);
+ bool LoadNothing(SDValue Op, SDValue N, SDValue &Base,
+ SDValue &Offset);
// getI8Imm - Return a target constant with the specified
// value, of type i8.
- inline SDOperand getI8Imm(unsigned Imm) {
+ inline SDValue getI8Imm(unsigned Imm) {
return CurDAG->getTargetConstant(Imm, MVT::i8);
}
@@ -118,7 +118,7 @@
bool PIC16DAGToDAGISel::
-SelectDirectAM (SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Offset)
+SelectDirectAM (SDValue Op, SDValue N, SDValue &Base, SDValue &Offset)
{
GlobalAddressSDNode *GA;
ConstantSDNode *GC;
@@ -160,7 +160,7 @@
// FIXME: must also account for preinc/predec/postinc/postdec.
bool PIC16DAGToDAGISel::
-StoreInDirectAM (SDOperand Op, SDOperand N, SDOperand &fsr)
+StoreInDirectAM (SDValue Op, SDValue N, SDValue &fsr)
{
RegisterSDNode *Reg;
if (N.getOpcode() == ISD::LOAD) {
@@ -186,7 +186,7 @@
}
bool PIC16DAGToDAGISel::
-LoadFSR (SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Offset)
+LoadFSR (SDValue Op, SDValue N, SDValue &Base, SDValue &Offset)
{
GlobalAddressSDNode *GA;
@@ -207,7 +207,7 @@
// LoadNothing - Don't thake this seriously, it will change.
bool PIC16DAGToDAGISel::
-LoadNothing (SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Offset)
+LoadNothing (SDValue Op, SDValue N, SDValue &Base, SDValue &Offset)
{
GlobalAddressSDNode *GA;
if (N.getOpcode() == ISD::GlobalAddress) {
@@ -225,7 +225,7 @@
/// Select - Select instructions not customized! Used for
/// expanded, promoted and normal instructions.
-SDNode* PIC16DAGToDAGISel::Select(SDOperand N)
+SDNode* PIC16DAGToDAGISel::Select(SDValue N)
{
SDNode *Node = N.Val;
unsigned Opcode = Node->getOpcode();
Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Sun Jul 27 16:46:04 2008
@@ -159,7 +159,7 @@
}
-SDOperand PIC16TargetLowering:: LowerOperation(SDOperand Op, SelectionDAG &DAG)
+SDValue PIC16TargetLowering:: LowerOperation(SDValue Op, SelectionDAG &DAG)
{
SDVTList VTList16 = DAG.getVTList(MVT::i16, MVT::i16, MVT::Other);
switch (Op.getOpcode()) {
@@ -195,7 +195,7 @@
DOUT << "==== lowering BR_CC\n";
return LowerBR_CC(Op, DAG);
} // end switch.
- return SDOperand();
+ return SDValue();
}
@@ -203,21 +203,21 @@
// Lower helper functions
//===----------------------------------------------------------------------===//
-SDOperand PIC16TargetLowering::LowerBR_CC(SDOperand Op, SelectionDAG &DAG)
+SDValue PIC16TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG)
{
MVT VT = Op.getValueType();
- SDOperand Chain = Op.getOperand(0);
+ SDValue Chain = Op.getOperand(0);
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
- SDOperand LHS = Op.getOperand(2);
- SDOperand RHS = Op.getOperand(3);
- SDOperand JumpVal = Op.getOperand(4);
- SDOperand Result;
+ SDValue LHS = Op.getOperand(2);
+ SDValue RHS = Op.getOperand(3);
+ SDValue JumpVal = Op.getOperand(4);
+ SDValue Result;
unsigned cmpOpcode;
unsigned branchOpcode;
- SDOperand branchOperand;
+ SDValue branchOperand;
- SDOperand StatusReg = DAG.getRegister(PIC16::STATUSREG, MVT::i8);
- SDOperand CPUReg = DAG.getRegister(PIC16::WREG, MVT::i8);
+ SDValue StatusReg = DAG.getRegister(PIC16::STATUSREG, MVT::i8);
+ SDValue CPUReg = DAG.getRegister(PIC16::WREG, MVT::i8);
switch(CC) {
default:
assert(0 && "This condition code is not handled yet!!");
@@ -263,7 +263,7 @@
} // End of Switch
SDVTList VTList = DAG.getVTList(MVT::i8, MVT::Flag);
- SDOperand CmpValue = DAG.getNode(cmpOpcode, VTList, LHS, RHS).getValue(1);
+ SDValue CmpValue = DAG.getNode(cmpOpcode, VTList, LHS, RHS).getValue(1);
Result = DAG.getNode(branchOpcode, VT, Chain, JumpVal, branchOperand,
StatusReg, CmpValue);
return Result;
@@ -276,23 +276,23 @@
// LowerGlobalAddress - Create a constant pool entry for global value
// and wrap it in a wrapper node.
-SDOperand
-PIC16TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG)
+SDValue
+PIC16TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG)
{
MVT PtrVT = getPointerTy();
GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
GlobalValue *GV = GSDN->getGlobal();
// FIXME: for now only do the ram.
- SDOperand CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
- SDOperand CPBank = DAG.getNode(PIC16ISD::SetBank, MVT::i8, CPAddr);
+ SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
+ SDValue CPBank = DAG.getNode(PIC16ISD::SetBank, MVT::i8, CPAddr);
CPAddr = DAG.getNode(PIC16ISD::Wrapper, MVT::i8, CPAddr,CPBank);
return CPAddr;
}
-SDOperand
-PIC16TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG)
+SDValue
+PIC16TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG)
{
switch(Op.getNumOperands()) {
default:
@@ -300,12 +300,12 @@
abort();
case 1:
- return SDOperand(); // ret void is legal
+ return SDValue(); // ret void is legal
}
}
-SDOperand
-PIC16TargetLowering::LowerFrameIndex(SDOperand N, SelectionDAG &DAG)
+SDValue
+PIC16TargetLowering::LowerFrameIndex(SDValue N, SelectionDAG &DAG)
{
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N)) {
return DAG.getTargetFrameIndex(FIN->getIndex(), MVT::i32);
@@ -314,17 +314,17 @@
return N;
}
-SDOperand
+SDValue
PIC16TargetLowering::LowerLOAD(SDNode *N,
SelectionDAG &DAG,
DAGCombinerInfo &DCI) const
{
- SDOperand Outs[2];
- SDOperand TF; //TokenFactor
- SDOperand OutChains[2];
- SDOperand Chain = N->getOperand(0);
- SDOperand Src = N->getOperand(1);
- SDOperand retVal;
+ SDValue Outs[2];
+ SDValue TF; //TokenFactor
+ SDValue OutChains[2];
+ SDValue Chain = N->getOperand(0);
+ SDValue Src = N->getOperand(1);
+ SDValue retVal;
SDVTList VTList;
// If this load is directly stored, replace the load value with the stored
@@ -332,7 +332,7 @@
// FIXME: Handle store large -> read small portion.
// FIXME: Handle TRUNCSTORE/LOADEXT
LoadSDNode *LD = cast<LoadSDNode>(N);
- SDOperand Ptr = LD->getBasePtr();
+ SDValue Ptr = LD->getBasePtr();
if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
if (ISD::isNON_TRUNCStore(Chain.Val)) {
StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
@@ -343,9 +343,9 @@
}
if (N->getValueType(0) != MVT::i16)
- return SDOperand();
+ return SDValue();
- SDOperand toWorklist;
+ SDValue toWorklist;
Outs[0] = DAG.getLoad(MVT::i8, Chain, Src, NULL, 0);
toWorklist = DAG.getNode(ISD::ADD, MVT::i16, Src,
DAG.getConstant(1, MVT::i16));
@@ -367,17 +367,17 @@
return retVal;
}
-SDOperand
+SDValue
PIC16TargetLowering::LowerADDSUB(SDNode *N, SelectionDAG &DAG,
DAGCombinerInfo &DCI) const
{
bool changed = false;
int i;
- SDOperand LoOps[3], HiOps[3];
- SDOperand OutOps[3]; // [0]:left, [1]:right, [2]:carry
- SDOperand InOp[2];
- SDOperand retVal;
- SDOperand as1,as2;
+ SDValue LoOps[3], HiOps[3];
+ SDValue OutOps[3]; // [0]:left, [1]:right, [2]:carry
+ SDValue InOp[2];
+ SDValue retVal;
+ SDValue as1,as2;
SDVTList VTList;
unsigned AS = 0, ASE = 0, ASC=0;
@@ -427,7 +427,7 @@
for (i = 0; i < 2; i++) {
if (InOp[i].getOpcode() == ISD::GlobalAddress) {
// We don't want to lower subs/adds with global address yet.
- return SDOperand();
+ return SDValue();
}
else if (InOp[i].getOpcode() == ISD::Constant) {
changed = true;
@@ -443,7 +443,7 @@
changed = true;
// LowerLOAD returns a Package node or it may combine and return
// anything else.
- SDOperand lowered = LowerLOAD(InOp[i].Val, DAG, DCI);
+ SDValue lowered = LowerLOAD(InOp[i].Val, DAG, DCI);
// So If LowerLOAD returns something other than Package,
// then just call ADD again.
@@ -462,7 +462,7 @@
changed = true;
// Must call LowerADDSUB recursively here,
// LowerADDSUB returns a Package node.
- SDOperand lowered = LowerADDSUB(InOp[i].Val, DAG, DCI);
+ SDValue lowered = LowerADDSUB(InOp[i].Val, DAG, DCI);
LoOps[i] = lowered.getOperand(0);
HiOps[i] = lowered.getOperand(1);
@@ -533,11 +533,11 @@
//===----------------------------------------------------------------------===//
// FORMAL_ARGUMENTS Calling Convention Implementation
//===----------------------------------------------------------------------===//
-SDOperand PIC16TargetLowering::
-LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG)
+SDValue PIC16TargetLowering::
+LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG)
{
- SmallVector<SDOperand, 8> ArgValues;
- SDOperand Root = Op.getOperand(0);
+ SmallVector<SDValue, 8> ArgValues;
+ SDValue Root = Op.getOperand(0);
// Return the new list of results.
// FIXME: Just copy right now.
@@ -560,7 +560,7 @@
// Target Optimization Hooks
//===----------------------------------------------------------------------===//
-SDOperand PIC16TargetLowering::PerformDAGCombine(SDNode *N,
+SDValue PIC16TargetLowering::PerformDAGCombine(SDNode *N,
DAGCombinerInfo &DCI) const
{
int i;
@@ -573,14 +573,14 @@
case PIC16ISD::Package:
DOUT << "==== combining PIC16ISD::Package\n";
- return SDOperand();
+ return SDValue();
case ISD::ADD:
case ISD::SUB:
if ((N->getOperand(0).getOpcode() == ISD::GlobalAddress) ||
(N->getOperand(0).getOpcode() == ISD::FrameIndex)) {
// Do not touch pointer adds.
- return SDOperand ();
+ return SDValue ();
}
break;
@@ -589,11 +589,11 @@
case ISD::SUBE :
case ISD::SUBC :
if (N->getValueType(0) == MVT::i16) {
- SDOperand retVal = LowerADDSUB(N, DAG,DCI);
+ SDValue retVal = LowerADDSUB(N, DAG,DCI);
// LowerADDSUB has already combined the result,
// so we just return nothing to avoid assertion failure from llvm
// if N has been deleted already.
- return SDOperand();
+ return SDValue();
}
else if (N->getValueType(0) == MVT::i8) {
// Sanity check ....
@@ -609,12 +609,12 @@
// FIXME: split this large chunk of code.
case ISD::STORE :
{
- SDOperand Chain = N->getOperand(0);
- SDOperand Src = N->getOperand(1);
- SDOperand Dest = N->getOperand(2);
+ SDValue Chain = N->getOperand(0);
+ SDValue Src = N->getOperand(1);
+ SDValue Dest = N->getOperand(2);
unsigned int DstOff = 0;
int NUM_STORES = 0;
- SDOperand Stores[6];
+ SDValue Stores[6];
// if source operand is expected to be extended to
// some higher type then - remove this extension
@@ -652,10 +652,10 @@
//create direct addressing a = b
Chain = Src.getOperand(0);
for (i=0; i<NUM_STORES; i++) {
- SDOperand ADN = DAG.getNode(ISD::ADD, MVT::i16, Src.getOperand(1),
+ SDValue ADN = DAG.getNode(ISD::ADD, MVT::i16, Src.getOperand(1),
DAG.getConstant(DstOff, MVT::i16));
- SDOperand LDN = DAG.getLoad(MVT::i8, Chain, ADN, NULL, 0);
- SDOperand DSTADDR = DAG.getNode(ISD::ADD, MVT::i16, Dest,
+ SDValue LDN = DAG.getLoad(MVT::i8, Chain, ADN, NULL, 0);
+ SDValue DSTADDR = DAG.getNode(ISD::ADD, MVT::i16, Dest,
DAG.getConstant(DstOff, MVT::i16));
Stores[i] = DAG.getStore(Chain, LDN, DSTADDR, NULL, 0);
Chain = Stores[i];
@@ -670,8 +670,8 @@
//create direct addressing a = CONST
CST = dyn_cast<ConstantSDNode>(Src);
for (i = 0; i < NUM_STORES; i++) {
- SDOperand CNST = DAG.getConstant(CST->getValue() >> i*8, MVT::i8);
- SDOperand ADN = DAG.getNode(ISD::ADD, MVT::i16, Dest,
+ SDValue CNST = DAG.getConstant(CST->getValue() >> i*8, MVT::i8);
+ SDValue ADN = DAG.getNode(ISD::ADD, MVT::i16, Dest,
DAG.getConstant(DstOff, MVT::i16));
Stores[i] = DAG.getStore(Chain, CNST, ADN, NULL, 0);
Chain = Stores[i];
@@ -686,11 +686,11 @@
// Create indirect addressing.
CST = dyn_cast<ConstantSDNode>(Src);
Chain = Dest.getOperand(0);
- SDOperand Load;
+ SDValue Load;
Load = DAG.getLoad(MVT::i16, Chain,Dest.getOperand(1), NULL, 0);
Chain = Load.getValue(1);
for (i=0; i<NUM_STORES; i++) {
- SDOperand CNST = DAG.getConstant(CST->getValue() >> i*8, MVT::i8);
+ SDValue CNST = DAG.getConstant(CST->getValue() >> i*8, MVT::i8);
Stores[i] = DAG.getStore(Chain, CNST, Load, NULL, 0);
Chain = Stores[i];
DstOff += 1;
@@ -701,11 +701,11 @@
}
else if (isa<LoadSDNode>(Dest) && isa<GlobalAddressSDNode>(Src)) {
// GlobalAddressSDNode *GAD = dyn_cast<GlobalAddressSDNode>(Src);
- return SDOperand();
+ return SDValue();
}
else if (Src.getOpcode() == PIC16ISD::Package) {
StoreSDNode *st = dyn_cast<StoreSDNode>(N);
- SDOperand toWorkList, retVal;
+ SDValue toWorkList, retVal;
Chain = N->getOperand(0);
if (st->isTruncatingStore()) {
@@ -739,7 +739,7 @@
case ISD::LOAD :
{
- SDOperand Ptr = N->getOperand(1);
+ SDValue Ptr = N->getOperand(1);
if (Ptr.getOpcode() == PIC16ISD::Package) {
assert (0 && "not implemented yet");
}
@@ -747,20 +747,20 @@
break;
} // end switch.
- return SDOperand();
+ return SDValue();
}
//===----------------------------------------------------------------------===//
// Utility functions
//===----------------------------------------------------------------------===//
-const SDOperand *PIC16TargetLowering::
-findLoadi8(const SDOperand &Src, SelectionDAG &DAG) const
+const SDValue *PIC16TargetLowering::
+findLoadi8(const SDValue &Src, SelectionDAG &DAG) const
{
unsigned int i;
if ((Src.getOpcode() == ISD::LOAD) && (Src.getValueType() == MVT::i8))
return &Src;
for (i=0; i<Src.getNumOperands(); i++) {
- const SDOperand *retVal = findLoadi8(Src.getOperand(i),DAG);
+ const SDValue *retVal = findLoadi8(Src.getOperand(i),DAG);
if (retVal) return retVal;
}
Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h Sun Jul 27 16:46:04 2008
@@ -64,28 +64,28 @@
explicit PIC16TargetLowering(PIC16TargetMachine &TM);
/// LowerOperation - Provide custom lowering hooks for some operations.
- virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
+ virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
- SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerFrameIndex(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG);
+ SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerRET(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG);
- SDOperand RemoveHiLo(SDNode *, SelectionDAG &DAG,
+ SDValue RemoveHiLo(SDNode *, SelectionDAG &DAG,
DAGCombinerInfo &DCI) const;
- SDOperand LowerADDSUB(SDNode *, SelectionDAG &DAG,
+ SDValue LowerADDSUB(SDNode *, SelectionDAG &DAG,
DAGCombinerInfo &DCI) const;
- SDOperand LowerLOAD(SDNode *, SelectionDAG &DAG,
+ SDValue LowerLOAD(SDNode *, SelectionDAG &DAG,
DAGCombinerInfo &DCI) const;
/// getTargetNodeName - This method returns the name of a target specific
// DAG node.
virtual const char *getTargetNodeName(unsigned Opcode) const;
- virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
+ virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
// utility function.
- const SDOperand *findLoadi8(const SDOperand &Src, SelectionDAG &DAG) const;
+ const SDValue *findLoadi8(const SDValue &Src, SelectionDAG &DAG) const;
};
} // namespace llvm
Modified: llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.cpp?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.cpp Sun Jul 27 16:46:04 2008
@@ -86,7 +86,7 @@
/// isLoadOfStoredAddress - If we have a load from the previously stored pointer
/// as indicated by StorePtr1/StorePtr2/StoreSize, return true.
bool PPCHazardRecognizer970::
-isLoadOfStoredAddress(unsigned LoadSize, SDOperand Ptr1, SDOperand Ptr2) const {
+isLoadOfStoredAddress(unsigned LoadSize, SDValue Ptr1, SDValue Ptr2) const {
for (unsigned i = 0, e = NumStores; i != e; ++i) {
// Handle exact and commuted addresses.
if (Ptr1 == StorePtr1[i] && Ptr2 == StorePtr2[i])
Modified: llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.h?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.h Sun Jul 27 16:46:04 2008
@@ -41,7 +41,7 @@
//
// This is null if we haven't seen a store yet. We keep track of both
// operands of the store here, since we support [r+r] and [r+i] addressing.
- SDOperand StorePtr1[4], StorePtr2[4];
+ SDValue StorePtr1[4], StorePtr2[4];
unsigned StoreSize[4];
unsigned NumStores;
@@ -64,7 +64,7 @@
bool &isLoad, bool &isStore);
bool isLoadOfStoredAddress(unsigned LoadSize,
- SDOperand Ptr1, SDOperand Ptr2) const;
+ SDValue Ptr1, SDValue Ptr2) const;
};
} // end namespace llvm
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Sun Jul 27 16:46:04 2008
@@ -61,18 +61,18 @@
/// getI32Imm - Return a target constant with the specified value, of type
/// i32.
- inline SDOperand getI32Imm(unsigned Imm) {
+ inline SDValue getI32Imm(unsigned Imm) {
return CurDAG->getTargetConstant(Imm, MVT::i32);
}
/// getI64Imm - Return a target constant with the specified value, of type
/// i64.
- inline SDOperand getI64Imm(uint64_t Imm) {
+ inline SDValue getI64Imm(uint64_t Imm) {
return CurDAG->getTargetConstant(Imm, MVT::i64);
}
/// getSmallIPtrImm - Return a target constant of pointer type.
- inline SDOperand getSmallIPtrImm(unsigned Imm) {
+ inline SDValue getSmallIPtrImm(unsigned Imm) {
return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy());
}
@@ -94,25 +94,25 @@
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
- SDNode *Select(SDOperand Op);
+ SDNode *Select(SDValue Op);
SDNode *SelectBitfieldInsert(SDNode *N);
/// SelectCC - Select a comparison of the specified values with the
/// specified condition code, returning the CR# of the expression.
- SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
+ SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC);
/// SelectAddrImm - Returns true if the address N can be represented by
/// a base register plus a signed 16-bit displacement [r+imm].
- bool SelectAddrImm(SDOperand Op, SDOperand N, SDOperand &Disp,
- SDOperand &Base) {
+ bool SelectAddrImm(SDValue Op, SDValue N, SDValue &Disp,
+ SDValue &Base) {
return PPCLowering.SelectAddressRegImm(N, Disp, Base, *CurDAG);
}
/// SelectAddrImmOffs - Return true if the operand is valid for a preinc
/// immediate field. Because preinc imms have already been validated, just
/// accept it.
- bool SelectAddrImmOffs(SDOperand Op, SDOperand N, SDOperand &Out) const {
+ bool SelectAddrImmOffs(SDValue Op, SDValue N, SDValue &Out) const {
Out = N;
return true;
}
@@ -120,33 +120,33 @@
/// SelectAddrIdx - Given the specified addressed, check to see if it can be
/// represented as an indexed [r+r] operation. Returns false if it can
/// be represented by [r+imm], which are preferred.
- bool SelectAddrIdx(SDOperand Op, SDOperand N, SDOperand &Base,
- SDOperand &Index) {
+ bool SelectAddrIdx(SDValue Op, SDValue N, SDValue &Base,
+ SDValue &Index) {
return PPCLowering.SelectAddressRegReg(N, Base, Index, *CurDAG);
}
/// SelectAddrIdxOnly - Given the specified addressed, force it to be
/// represented as an indexed [r+r] operation.
- bool SelectAddrIdxOnly(SDOperand Op, SDOperand N, SDOperand &Base,
- SDOperand &Index) {
+ bool SelectAddrIdxOnly(SDValue Op, SDValue N, SDValue &Base,
+ SDValue &Index) {
return PPCLowering.SelectAddressRegRegOnly(N, Base, Index, *CurDAG);
}
/// SelectAddrImmShift - Returns true if the address N can be represented by
/// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable
/// for use by STD and friends.
- bool SelectAddrImmShift(SDOperand Op, SDOperand N, SDOperand &Disp,
- SDOperand &Base) {
+ bool SelectAddrImmShift(SDValue Op, SDValue N, SDValue &Disp,
+ SDValue &Base) {
return PPCLowering.SelectAddressRegImmShift(N, Disp, Base, *CurDAG);
}
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
- virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
+ virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
char ConstraintCode,
- std::vector<SDOperand> &OutOps,
+ std::vector<SDValue> &OutOps,
SelectionDAG &DAG) {
- SDOperand Op0, Op1;
+ SDValue Op0, Op1;
switch (ConstraintCode) {
default: return true;
case 'm': // memory
@@ -170,8 +170,8 @@
return false;
}
- SDOperand BuildSDIVSequence(SDNode *N);
- SDOperand BuildUDIVSequence(SDNode *N);
+ SDValue BuildSDIVSequence(SDNode *N);
+ SDValue BuildUDIVSequence(SDNode *N);
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
@@ -197,7 +197,7 @@
#include "PPCGenDAGISel.inc"
private:
- SDNode *SelectSETCC(SDOperand Op);
+ SDNode *SelectSETCC(SDValue Op);
};
}
@@ -313,7 +313,7 @@
return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue();
}
-static bool isIntS16Immediate(SDOperand Op, short &Imm) {
+static bool isIntS16Immediate(SDValue Op, short &Imm) {
return isIntS16Immediate(Op.Val, Imm);
}
@@ -340,7 +340,7 @@
// isInt32Immediate - This method tests to see if a constant operand.
// If so Imm will receive the 32 bit value.
-static bool isInt32Immediate(SDOperand N, unsigned &Imm) {
+static bool isInt32Immediate(SDValue N, unsigned &Imm) {
return isInt32Immediate(N.Val, Imm);
}
@@ -418,8 +418,8 @@
/// SelectBitfieldInsert - turn an or of two masked values into
/// the rotate left word immediate then mask insert (rlwimi) instruction.
SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
- SDOperand Op0 = N->getOperand(0);
- SDOperand Op1 = N->getOperand(1);
+ SDValue Op0 = N->getOperand(0);
+ SDValue Op1 = N->getOperand(1);
APInt LKZ, LKO, RKZ, RKO;
CurDAG->ComputeMaskedBits(Op0, APInt::getAllOnesValue(32), LKZ, LKO);
@@ -458,7 +458,7 @@
unsigned MB, ME;
if (InsertMask && isRunOfOnes(InsertMask, MB, ME)) {
- SDOperand Tmp1, Tmp2, Tmp3;
+ SDValue Tmp1, Tmp2, Tmp3;
bool DisjointMask = (TargetMask ^ InsertMask) == 0xFFFFFFFF;
if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
@@ -481,7 +481,7 @@
AddToISelQueue(Tmp3);
AddToISelQueue(Op1);
SH &= 31;
- SDOperand Ops[] = { Tmp3, Op1, getI32Imm(SH), getI32Imm(MB),
+ SDValue Ops[] = { Tmp3, Op1, getI32Imm(SH), getI32Imm(MB),
getI32Imm(ME) };
return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Ops, 5);
}
@@ -491,7 +491,7 @@
/// SelectCC - Select a comparison of the specified values with the specified
/// condition code, returning the CR# of the expression.
-SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS,
+SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS,
ISD::CondCode CC) {
// Always select the LHS.
AddToISelQueue(LHS);
@@ -503,11 +503,11 @@
if (isInt32Immediate(RHS, Imm)) {
// SETEQ/SETNE comparison with 16-bit immediate, fold it.
if (isUInt16(Imm))
- return SDOperand(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, LHS,
+ return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, LHS,
getI32Imm(Imm & 0xFFFF)), 0);
// If this is a 16-bit signed immediate, fold it.
if (isInt16((int)Imm))
- return SDOperand(CurDAG->getTargetNode(PPC::CMPWI, MVT::i32, LHS,
+ return SDValue(CurDAG->getTargetNode(PPC::CMPWI, MVT::i32, LHS,
getI32Imm(Imm & 0xFFFF)), 0);
// For non-equality comparisons, the default code would materialize the
@@ -519,21 +519,21 @@
// xoris r0,r3,0x1234
// cmplwi cr0,r0,0x5678
// beq cr0,L6
- SDOperand Xor(CurDAG->getTargetNode(PPC::XORIS, MVT::i32, LHS,
+ SDValue Xor(CurDAG->getTargetNode(PPC::XORIS, MVT::i32, LHS,
getI32Imm(Imm >> 16)), 0);
- return SDOperand(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, Xor,
+ return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, Xor,
getI32Imm(Imm & 0xFFFF)), 0);
}
Opc = PPC::CMPLW;
} else if (ISD::isUnsignedIntSetCC(CC)) {
if (isInt32Immediate(RHS, Imm) && isUInt16(Imm))
- return SDOperand(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, LHS,
+ return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, LHS,
getI32Imm(Imm & 0xFFFF)), 0);
Opc = PPC::CMPLW;
} else {
short SImm;
if (isIntS16Immediate(RHS, SImm))
- return SDOperand(CurDAG->getTargetNode(PPC::CMPWI, MVT::i32, LHS,
+ return SDValue(CurDAG->getTargetNode(PPC::CMPWI, MVT::i32, LHS,
getI32Imm((int)SImm & 0xFFFF)),
0);
Opc = PPC::CMPW;
@@ -544,11 +544,11 @@
if (isInt64Immediate(RHS.Val, Imm)) {
// SETEQ/SETNE comparison with 16-bit immediate, fold it.
if (isUInt16(Imm))
- return SDOperand(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS,
+ return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS,
getI32Imm(Imm & 0xFFFF)), 0);
// If this is a 16-bit signed immediate, fold it.
if (isInt16(Imm))
- return SDOperand(CurDAG->getTargetNode(PPC::CMPDI, MVT::i64, LHS,
+ return SDValue(CurDAG->getTargetNode(PPC::CMPDI, MVT::i64, LHS,
getI32Imm(Imm & 0xFFFF)), 0);
// For non-equality comparisons, the default code would materialize the
@@ -561,22 +561,22 @@
// cmpldi cr0,r0,0x5678
// beq cr0,L6
if (isUInt32(Imm)) {
- SDOperand Xor(CurDAG->getTargetNode(PPC::XORIS8, MVT::i64, LHS,
+ SDValue Xor(CurDAG->getTargetNode(PPC::XORIS8, MVT::i64, LHS,
getI64Imm(Imm >> 16)), 0);
- return SDOperand(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, Xor,
+ return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, Xor,
getI64Imm(Imm & 0xFFFF)), 0);
}
}
Opc = PPC::CMPLD;
} else if (ISD::isUnsignedIntSetCC(CC)) {
if (isInt64Immediate(RHS.Val, Imm) && isUInt16(Imm))
- return SDOperand(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS,
+ return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS,
getI64Imm(Imm & 0xFFFF)), 0);
Opc = PPC::CMPLD;
} else {
short SImm;
if (isIntS16Immediate(RHS, SImm))
- return SDOperand(CurDAG->getTargetNode(PPC::CMPDI, MVT::i64, LHS,
+ return SDValue(CurDAG->getTargetNode(PPC::CMPDI, MVT::i64, LHS,
getI64Imm(SImm & 0xFFFF)),
0);
Opc = PPC::CMPD;
@@ -588,7 +588,7 @@
Opc = PPC::FCMPUD;
}
AddToISelQueue(RHS);
- return SDOperand(CurDAG->getTargetNode(Opc, MVT::i32, LHS, RHS), 0);
+ return SDValue(CurDAG->getTargetNode(Opc, MVT::i32, LHS, RHS), 0);
}
static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
@@ -653,7 +653,7 @@
return 0;
}
-SDNode *PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
+SDNode *PPCDAGToDAGISel::SelectSETCC(SDValue Op) {
SDNode *N = Op.Val;
unsigned Imm;
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
@@ -662,64 +662,64 @@
// Check for those cases here.
// setcc op, 0
if (Imm == 0) {
- SDOperand Op = N->getOperand(0);
+ SDValue Op = N->getOperand(0);
AddToISelQueue(Op);
switch (CC) {
default: break;
case ISD::SETEQ: {
- Op = SDOperand(CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op), 0);
- SDOperand Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
+ Op = SDValue(CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op), 0);
+ SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
case ISD::SETNE: {
- SDOperand AD =
- SDOperand(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
+ SDValue AD =
+ SDValue(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
Op, getI32Imm(~0U)), 0);
return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
AD.getValue(1));
}
case ISD::SETLT: {
- SDOperand Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
+ SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
case ISD::SETGT: {
- SDOperand T =
- SDOperand(CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op), 0);
- T = SDOperand(CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op), 0);
- SDOperand Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
+ SDValue T =
+ SDValue(CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op), 0);
+ T = SDValue(CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op), 0);
+ SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
}
} else if (Imm == ~0U) { // setcc op, -1
- SDOperand Op = N->getOperand(0);
+ SDValue Op = N->getOperand(0);
AddToISelQueue(Op);
switch (CC) {
default: break;
case ISD::SETEQ:
- Op = SDOperand(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
+ Op = SDValue(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
Op, getI32Imm(1)), 0);
return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
- SDOperand(CurDAG->getTargetNode(PPC::LI, MVT::i32,
+ SDValue(CurDAG->getTargetNode(PPC::LI, MVT::i32,
getI32Imm(0)), 0),
Op.getValue(1));
case ISD::SETNE: {
- Op = SDOperand(CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op), 0);
+ Op = SDValue(CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op), 0);
SDNode *AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
Op, getI32Imm(~0U));
- return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDOperand(AD, 0),
- Op, SDOperand(AD, 1));
+ return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0),
+ Op, SDValue(AD, 1));
}
case ISD::SETLT: {
- SDOperand AD = SDOperand(CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op,
+ SDValue AD = SDValue(CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op,
getI32Imm(1)), 0);
- SDOperand AN = SDOperand(CurDAG->getTargetNode(PPC::AND, MVT::i32, AD,
+ SDValue AN = SDValue(CurDAG->getTargetNode(PPC::AND, MVT::i32, AD,
Op), 0);
- SDOperand Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
+ SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
case ISD::SETGT: {
- SDOperand Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
- Op = SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
+ SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
+ Op = SDValue(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op,
getI32Imm(1));
}
@@ -730,30 +730,30 @@
bool Inv;
int OtherCondIdx;
unsigned Idx = getCRIdxForSetCC(CC, Inv, OtherCondIdx);
- SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
- SDOperand IntCR;
+ SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
+ SDValue IntCR;
// Force the ccreg into CR7.
- SDOperand CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
+ SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
- SDOperand InFlag(0, 0); // Null incoming flag value.
+ SDValue InFlag(0, 0); // Null incoming flag value.
CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), CR7Reg, CCReg,
InFlag).getValue(1);
if (PPCSubTarget.isGigaProcessor() && OtherCondIdx == -1)
- IntCR = SDOperand(CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg,
+ IntCR = SDValue(CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg,
CCReg), 0);
else
- IntCR = SDOperand(CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg), 0);
+ IntCR = SDValue(CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg), 0);
- SDOperand Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
+ SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
getI32Imm(31), getI32Imm(31) };
if (OtherCondIdx == -1 && !Inv)
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
// Get the specified bit.
- SDOperand Tmp =
- SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
+ SDValue Tmp =
+ SDValue(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
if (Inv) {
assert(OtherCondIdx == -1 && "Can't have split plus negation");
return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
@@ -764,8 +764,8 @@
// Get the other bit of the comparison.
Ops[1] = getI32Imm((32-(3-OtherCondIdx)) & 31);
- SDOperand OtherCond =
- SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
+ SDValue OtherCond =
+ SDValue(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
return CurDAG->SelectNodeTo(N, PPC::OR, MVT::i32, Tmp, OtherCond);
}
@@ -773,7 +773,7 @@
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
-SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
+SDNode *PPCDAGToDAGISel::Select(SDValue Op) {
SDNode *N = Op.Val;
if (N->isMachineOpcode())
return NULL; // Already selected.
@@ -824,7 +824,7 @@
Result = CurDAG->getTargetNode(OpC, MVT::i64, getI32Imm(Hi));
// And Lo bits.
Result = CurDAG->getTargetNode(PPC::ORI8, MVT::i64,
- SDOperand(Result, 0), getI32Imm(Lo));
+ SDValue(Result, 0), getI32Imm(Lo));
} else {
// Just the Hi bits.
Result = CurDAG->getTargetNode(PPC::LIS8, MVT::i64, getI32Imm(Hi));
@@ -836,18 +836,18 @@
// Shift for next step if the upper 32-bits were not zero.
if (Imm) {
Result = CurDAG->getTargetNode(PPC::RLDICR, MVT::i64,
- SDOperand(Result, 0),
+ SDValue(Result, 0),
getI32Imm(Shift), getI32Imm(63 - Shift));
}
// Add in the last bits as required.
if ((Hi = (Remainder >> 16) & 0xFFFF)) {
Result = CurDAG->getTargetNode(PPC::ORIS8, MVT::i64,
- SDOperand(Result, 0), getI32Imm(Hi));
+ SDValue(Result, 0), getI32Imm(Hi));
}
if ((Lo = Remainder & 0xFFFF)) {
Result = CurDAG->getTargetNode(PPC::ORI8, MVT::i64,
- SDOperand(Result, 0), getI32Imm(Lo));
+ SDValue(Result, 0), getI32Imm(Lo));
}
return Result;
@@ -862,7 +862,7 @@
case ISD::FrameIndex: {
int FI = cast<FrameIndexSDNode>(N)->getIndex();
- SDOperand TFI = CurDAG->getTargetFrameIndex(FI, Op.getValueType());
+ SDValue TFI = CurDAG->getTargetFrameIndex(FI, Op.getValueType());
unsigned Opc = Op.getValueType() == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
if (N->hasOneUse())
return CurDAG->SelectNodeTo(N, Opc, Op.getValueType(), TFI,
@@ -872,7 +872,7 @@
}
case PPCISD::MFCR: {
- SDOperand InFlag = N->getOperand(1);
+ SDValue InFlag = N->getOperand(1);
AddToISelQueue(InFlag);
// Use MFOCRF if supported.
if (PPCSubTarget.isGigaProcessor())
@@ -890,21 +890,21 @@
// sra/addze rather than having to handle sdiv ourselves. oh well.
unsigned Imm;
if (isInt32Immediate(N->getOperand(1), Imm)) {
- SDOperand N0 = N->getOperand(0);
+ SDValue N0 = N->getOperand(0);
AddToISelQueue(N0);
if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
SDNode *Op =
CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
N0, getI32Imm(Log2_32(Imm)));
return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
- SDOperand(Op, 0), SDOperand(Op, 1));
+ SDValue(Op, 0), SDValue(Op, 1));
} else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
SDNode *Op =
CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
N0, getI32Imm(Log2_32(-Imm)));
- SDOperand PT =
- SDOperand(CurDAG->getTargetNode(PPC::ADDZE, MVT::i32,
- SDOperand(Op, 0), SDOperand(Op, 1)),
+ SDValue PT =
+ SDValue(CurDAG->getTargetNode(PPC::ADDZE, MVT::i32,
+ SDValue(Op, 0), SDValue(Op, 1)),
0);
return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
}
@@ -923,7 +923,7 @@
if (LD->getAddressingMode() != ISD::PRE_INC)
break;
- SDOperand Offset = LD->getOffset();
+ SDValue Offset = LD->getOffset();
if (isa<ConstantSDNode>(Offset) ||
Offset.getOpcode() == ISD::TargetGlobalAddress) {
@@ -954,12 +954,12 @@
}
}
- SDOperand Chain = LD->getChain();
- SDOperand Base = LD->getBasePtr();
+ SDValue Chain = LD->getChain();
+ SDValue Base = LD->getBasePtr();
AddToISelQueue(Chain);
AddToISelQueue(Base);
AddToISelQueue(Offset);
- SDOperand Ops[] = { Offset, Base, Chain };
+ SDValue Ops[] = { Offset, Base, Chain };
// FIXME: PPC64
return CurDAG->getTargetNode(Opcode, LD->getValueType(0),
PPCLowering.getPointerTy(),
@@ -976,9 +976,9 @@
// with a mask, emit rlwinm
if (isInt32Immediate(N->getOperand(1), Imm) &&
isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) {
- SDOperand Val = N->getOperand(0).getOperand(0);
+ SDValue Val = N->getOperand(0).getOperand(0);
AddToISelQueue(Val);
- SDOperand Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
+ SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
// If this is just a masked value where the input is not handled above, and
@@ -986,15 +986,15 @@
if (isInt32Immediate(N->getOperand(1), Imm) &&
isRunOfOnes(Imm, MB, ME) &&
N->getOperand(0).getOpcode() != ISD::ROTL) {
- SDOperand Val = N->getOperand(0);
+ SDValue Val = N->getOperand(0);
AddToISelQueue(Val);
- SDOperand Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) };
+ SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) };
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
// AND X, 0 -> 0, not "rlwinm 32".
if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) {
AddToISelQueue(N->getOperand(1));
- ReplaceUses(SDOperand(N, 0), N->getOperand(1));
+ ReplaceUses(SDValue(N, 0), N->getOperand(1));
return NULL;
}
// ISD::OR doesn't get all the bitfield insertion fun.
@@ -1007,7 +1007,7 @@
if (isRunOfOnes(Imm, MB, ME)) {
AddToISelQueue(N->getOperand(0).getOperand(0));
AddToISelQueue(N->getOperand(0).getOperand(1));
- SDOperand Ops[] = { N->getOperand(0).getOperand(0),
+ SDValue Ops[] = { N->getOperand(0).getOperand(0),
N->getOperand(0).getOperand(1),
getI32Imm(0), getI32Imm(MB),getI32Imm(ME) };
return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Ops, 5);
@@ -1029,7 +1029,7 @@
if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
isRotateAndMask(N, Imm, true, SH, MB, ME)) {
AddToISelQueue(N->getOperand(0).getOperand(0));
- SDOperand Ops[] = { N->getOperand(0).getOperand(0),
+ SDValue Ops[] = { N->getOperand(0).getOperand(0),
getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
@@ -1042,7 +1042,7 @@
if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
isRotateAndMask(N, Imm, true, SH, MB, ME)) {
AddToISelQueue(N->getOperand(0).getOperand(0));
- SDOperand Ops[] = { N->getOperand(0).getOperand(0),
+ SDValue Ops[] = { N->getOperand(0).getOperand(0),
getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
@@ -1066,11 +1066,11 @@
CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
N->getOperand(0), getI32Imm(~0U));
return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
- SDOperand(Tmp, 0), N->getOperand(0),
- SDOperand(Tmp, 1));
+ SDValue(Tmp, 0), N->getOperand(0),
+ SDValue(Tmp, 1));
}
- SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
+ SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
unsigned BROpc = getPredicateForSetCC(CC);
unsigned SelectCCOp;
@@ -1087,7 +1087,7 @@
AddToISelQueue(N->getOperand(2));
AddToISelQueue(N->getOperand(3));
- SDOperand Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
+ SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
getI32Imm(BROpc) };
return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops, 4);
}
@@ -1098,28 +1098,28 @@
// Op #3 is the Dest MBB
AddToISelQueue(N->getOperand(4)); // Op #4 is the Flag.
// Prevent PPC::PRED_* from being selected into LI.
- SDOperand Pred =
+ SDValue Pred =
getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getValue());
- SDOperand Ops[] = { Pred, N->getOperand(2), N->getOperand(3),
+ SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3),
N->getOperand(0), N->getOperand(4) };
return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 5);
}
case ISD::BR_CC: {
AddToISelQueue(N->getOperand(0));
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
- SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
- SDOperand Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode,
+ SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
+ SDValue Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode,
N->getOperand(4), N->getOperand(0) };
return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4);
}
case ISD::BRIND: {
// FIXME: Should custom lower this.
- SDOperand Chain = N->getOperand(0);
- SDOperand Target = N->getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ SDValue Target = N->getOperand(1);
AddToISelQueue(Chain);
AddToISelQueue(Target);
unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
- Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, Target,
+ Chain = SDValue(CurDAG->getTargetNode(Opc, MVT::Other, Target,
Chain), 0);
return CurDAG->SelectNodeTo(N, PPC::BCTR, MVT::Other, Chain);
}
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