[llvm-commits] [llvm] r54128 [2/2] - in /llvm/trunk: docs/ include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/CellSPU/ lib/Target/IA64/ lib/Target/Mips/ lib/Target/PIC16/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/X86/ lib/Transforms/Scalar/ utils/TableGen/
Dan Gohman
gohman at apple.com
Sun Jul 27 14:46:05 PDT 2008
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Sun Jul 27 16:46:04 2008
@@ -422,7 +422,7 @@
}
-MVT PPCTargetLowering::getSetCCResultType(const SDOperand &) const {
+MVT PPCTargetLowering::getSetCCResultType(const SDValue &) const {
return MVT::i32;
}
@@ -432,7 +432,7 @@
//===----------------------------------------------------------------------===//
/// isFloatingPointZero - Return true if this is 0.0 or -0.0.
-static bool isFloatingPointZero(SDOperand Op) {
+static bool isFloatingPointZero(SDValue Op) {
if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
return CFP->getValueAPF().isZero();
else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
@@ -446,7 +446,7 @@
/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
/// true if Op is undef or if it matches the specified value.
-static bool isConstantOrUndef(SDOperand Op, unsigned Val) {
+static bool isConstantOrUndef(SDValue Op, unsigned Val) {
return Op.getOpcode() == ISD::UNDEF ||
cast<ConstantSDNode>(Op)->getValue() == Val;
}
@@ -567,7 +567,7 @@
// This is a splat operation if each element of the permute is the same, and
// if the value doesn't reference the second vector.
unsigned ElementBase = 0;
- SDOperand Elt = N->getOperand(0);
+ SDValue Elt = N->getOperand(0);
if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt))
ElementBase = EltV->getValue();
else
@@ -617,8 +617,8 @@
/// by using a vspltis[bhw] instruction of the specified element size, return
/// the constant being splatted. The ByteSize field indicates the number of
/// bytes of each element [124] -> [bhw].
-SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
- SDOperand OpVal(0, 0);
+SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
+ SDValue OpVal(0, 0);
// If ByteSize of the splat is bigger than the element size of the
// build_vector, then we have a case where we are checking for a splat where
@@ -627,20 +627,20 @@
unsigned EltSize = 16/N->getNumOperands();
if (EltSize < ByteSize) {
unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
- SDOperand UniquedVals[4];
+ SDValue UniquedVals[4];
assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
// See if all of the elements in the buildvector agree across.
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
// If the element isn't a constant, bail fully out.
- if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand();
+ if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
if (UniquedVals[i&(Multiple-1)].Val == 0)
UniquedVals[i&(Multiple-1)] = N->getOperand(i);
else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
- return SDOperand(); // no match.
+ return SDValue(); // no match.
}
// Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
@@ -673,7 +673,7 @@
return DAG.getTargetConstant(Val, MVT::i32);
}
- return SDOperand();
+ return SDValue();
}
// Check to see if this buildvec has a single non-undef value in its elements.
@@ -682,10 +682,10 @@
if (OpVal.Val == 0)
OpVal = N->getOperand(i);
else if (OpVal != N->getOperand(i))
- return SDOperand();
+ return SDValue();
}
- if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def.
+ if (OpVal.Val == 0) return SDValue(); // All UNDEF: use implicit def.
unsigned ValSizeInBytes = 0;
uint64_t Value = 0;
@@ -701,7 +701,7 @@
// If the splat value is larger than the element value, then we can never do
// this splat. The only case that we could fit the replicated bits into our
// immediate field for would be zero, and we prefer to use vxor for it.
- if (ValSizeInBytes < ByteSize) return SDOperand();
+ if (ValSizeInBytes < ByteSize) return SDValue();
// If the element value is larger than the splat value, cut it in half and
// check to see if the two halves are equal. Continue doing this until we
@@ -712,7 +712,7 @@
// If the top half equals the bottom half, we're still ok.
if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
(Value & ((1 << (8*ValSizeInBytes))-1)))
- return SDOperand();
+ return SDValue();
}
// Properly sign extend the value.
@@ -720,12 +720,12 @@
int MaskVal = ((int)Value << ShAmt) >> ShAmt;
// If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
- if (MaskVal == 0) return SDOperand();
+ if (MaskVal == 0) return SDValue();
// Finally, if this value fits in a 5 bit sext field, return it
if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
return DAG.getTargetConstant(MaskVal, MVT::i32);
- return SDOperand();
+ return SDValue();
}
//===----------------------------------------------------------------------===//
@@ -746,7 +746,7 @@
else
return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue();
}
-static bool isIntS16Immediate(SDOperand Op, short &Imm) {
+static bool isIntS16Immediate(SDValue Op, short &Imm) {
return isIntS16Immediate(Op.Val, Imm);
}
@@ -754,8 +754,8 @@
/// SelectAddressRegReg - Given the specified addressed, check to see if it
/// can be represented as an indexed [r+r] operation. Returns false if it
/// can be more efficiently represented with [r+imm].
-bool PPCTargetLowering::SelectAddressRegReg(SDOperand N, SDOperand &Base,
- SDOperand &Index,
+bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
+ SDValue &Index,
SelectionDAG &DAG) {
short imm = 0;
if (N.getOpcode() == ISD::ADD) {
@@ -802,8 +802,8 @@
/// Returns true if the address N can be represented by a base register plus
/// a signed 16-bit displacement [r+imm], and if it is not better
/// represented as reg+reg.
-bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp,
- SDOperand &Base, SelectionDAG &DAG){
+bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
+ SDValue &Base, SelectionDAG &DAG){
// If this can be more profitably realized as r+r, fail.
if (SelectAddressRegReg(N, Disp, Base, DAG))
return false;
@@ -871,7 +871,7 @@
Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
- Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
+ Base = SDValue(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
return true;
}
}
@@ -886,8 +886,8 @@
/// SelectAddressRegRegOnly - Given the specified addressed, force it to be
/// represented as an indexed [r+r] operation.
-bool PPCTargetLowering::SelectAddressRegRegOnly(SDOperand N, SDOperand &Base,
- SDOperand &Index,
+bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
+ SDValue &Index,
SelectionDAG &DAG) {
// Check to see if we can easily represent this as an [r+r] address. This
// will fail if it thinks that the address is more profitably represented as
@@ -913,8 +913,8 @@
/// SelectAddressRegImmShift - Returns true if the address N can be
/// represented by a base register plus a signed 14-bit displacement
/// [r+imm*4]. Suitable for use by STD and friends.
-bool PPCTargetLowering::SelectAddressRegImmShift(SDOperand N, SDOperand &Disp,
- SDOperand &Base,
+bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp,
+ SDValue &Base,
SelectionDAG &DAG) {
// If this can be more profitably realized as r+r, fail.
if (SelectAddressRegReg(N, Disp, Base, DAG))
@@ -982,7 +982,7 @@
Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
- Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
+ Base = SDValue(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
return true;
}
}
@@ -1000,14 +1000,14 @@
/// getPreIndexedAddressParts - returns true by value, base pointer and
/// offset pointer and addressing mode by reference if the node's address
/// can be legally represented as pre-indexed load / store address.
-bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
- SDOperand &Offset,
+bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
+ SDValue &Offset,
ISD::MemIndexedMode &AM,
SelectionDAG &DAG) {
// Disabled by default for now.
if (!EnablePPCPreinc) return false;
- SDOperand Ptr;
+ SDValue Ptr;
MVT VT;
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
Ptr = LD->getBasePtr();
@@ -1054,18 +1054,18 @@
// LowerOperation implementation
//===----------------------------------------------------------------------===//
-SDOperand PPCTargetLowering::LowerConstantPool(SDOperand Op,
+SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
SelectionDAG &DAG) {
MVT PtrVT = Op.getValueType();
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
Constant *C = CP->getConstVal();
- SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
- SDOperand Zero = DAG.getConstant(0, PtrVT);
+ SDValue CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
+ SDValue Zero = DAG.getConstant(0, PtrVT);
const TargetMachine &TM = DAG.getTarget();
- SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero);
- SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero);
+ SDValue Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero);
+ SDValue Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero);
// If this is a non-darwin platform, we don't support non-static relo models
// yet.
@@ -1086,16 +1086,16 @@
return Lo;
}
-SDOperand PPCTargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
+SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
MVT PtrVT = Op.getValueType();
JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
- SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
- SDOperand Zero = DAG.getConstant(0, PtrVT);
+ SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
+ SDValue Zero = DAG.getConstant(0, PtrVT);
const TargetMachine &TM = DAG.getTarget();
- SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero);
- SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero);
+ SDValue Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero);
+ SDValue Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero);
// If this is a non-darwin platform, we don't support non-static relo models
// yet.
@@ -1116,27 +1116,27 @@
return Lo;
}
-SDOperand PPCTargetLowering::LowerGlobalTLSAddress(SDOperand Op,
+SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
SelectionDAG &DAG) {
assert(0 && "TLS not implemented for PPC.");
- return SDOperand(); // Not reached
+ return SDValue(); // Not reached
}
-SDOperand PPCTargetLowering::LowerGlobalAddress(SDOperand Op,
+SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
SelectionDAG &DAG) {
MVT PtrVT = Op.getValueType();
GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
GlobalValue *GV = GSDN->getGlobal();
- SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
+ SDValue GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
// If it's a debug information descriptor, don't mess with it.
if (DAG.isVerifiedDebugInfoDesc(Op))
return GA;
- SDOperand Zero = DAG.getConstant(0, PtrVT);
+ SDValue Zero = DAG.getConstant(0, PtrVT);
const TargetMachine &TM = DAG.getTarget();
- SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero);
- SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero);
+ SDValue Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero);
+ SDValue Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero);
// If this is a non-darwin platform, we don't support non-static relo models
// yet.
@@ -1163,7 +1163,7 @@
return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0);
}
-SDOperand PPCTargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
+SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
// If we're comparing for equality to zero, expose the fact that this is
@@ -1172,14 +1172,14 @@
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
if (C->isNullValue() && CC == ISD::SETEQ) {
MVT VT = Op.getOperand(0).getValueType();
- SDOperand Zext = Op.getOperand(0);
+ SDValue Zext = Op.getOperand(0);
if (VT.bitsLT(MVT::i32)) {
VT = MVT::i32;
Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
}
unsigned Log2b = Log2_32(VT.getSizeInBits());
- SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext);
- SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz,
+ SDValue Clz = DAG.getNode(ISD::CTLZ, VT, Zext);
+ SDValue Scc = DAG.getNode(ISD::SRL, VT, Clz,
DAG.getConstant(Log2b, MVT::i32));
return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc);
}
@@ -1187,7 +1187,7 @@
// optimized. FIXME: revisit this when we can custom lower all setcc
// optimizations.
if (C->isAllOnesValue() || C->isNullValue())
- return SDOperand();
+ return SDValue();
}
// If we have an integer seteq/setne, turn it into a compare against zero
@@ -1198,14 +1198,14 @@
MVT LHSVT = Op.getOperand(0).getValueType();
if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
MVT VT = Op.getValueType();
- SDOperand Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0),
+ SDValue Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0),
Op.getOperand(1));
return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC);
}
- return SDOperand();
+ return SDValue();
}
-SDOperand PPCTargetLowering::LowerVAARG(SDOperand Op, SelectionDAG &DAG,
+SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
int VarArgsFrameIndex,
int VarArgsStackOffset,
unsigned VarArgsNumGPR,
@@ -1213,10 +1213,10 @@
const PPCSubtarget &Subtarget) {
assert(0 && "VAARG in ELF32 ABI not implemented yet!");
- return SDOperand(); // Not reached
+ return SDValue(); // Not reached
}
-SDOperand PPCTargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG,
+SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
int VarArgsFrameIndex,
int VarArgsStackOffset,
unsigned VarArgsNumGPR,
@@ -1227,7 +1227,7 @@
// vastart just stores the address of the VarArgsFrameIndex slot into the
// memory location argument.
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
- SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
+ SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0);
}
@@ -1257,41 +1257,41 @@
// } va_list[1];
- SDOperand ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i8);
- SDOperand ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8);
+ SDValue ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i8);
+ SDValue ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8);
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
- SDOperand StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT);
- SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
+ SDValue StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT);
+ SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
- SDOperand ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
+ SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
- SDOperand ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
+ SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
uint64_t FPROffset = 1;
- SDOperand ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
+ SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
// Store first byte : number of int regs
- SDOperand firstStore = DAG.getStore(Op.getOperand(0), ArgGPR,
+ SDValue firstStore = DAG.getStore(Op.getOperand(0), ArgGPR,
Op.getOperand(1), SV, 0);
uint64_t nextOffset = FPROffset;
- SDOperand nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1),
+ SDValue nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1),
ConstFPROffset);
// Store second byte : number of float regs
- SDOperand secondStore =
+ SDValue secondStore =
DAG.getStore(firstStore, ArgFPR, nextPtr, SV, nextOffset);
nextOffset += StackOffset;
nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstStackOffset);
// Store second word : arguments given on stack
- SDOperand thirdStore =
+ SDValue thirdStore =
DAG.getStore(secondStore, StackOffsetFI, nextPtr, SV, nextOffset);
nextOffset += FrameOffset;
nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstFrameOffset);
@@ -1324,7 +1324,7 @@
/// CalculateStackSlotSize - Calculates the size reserved for this argument on
/// the stack.
-static unsigned CalculateStackSlotSize(SDOperand Arg, SDOperand Flag,
+static unsigned CalculateStackSlotSize(SDValue Arg, SDValue Flag,
bool isVarArg, unsigned PtrByteSize) {
MVT ArgVT = Arg.getValueType();
ISD::ArgFlagsTy Flags = cast<ARG_FLAGSSDNode>(Flag)->getArgFlags();
@@ -1336,8 +1336,8 @@
return ArgSize;
}
-SDOperand
-PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op,
+SDValue
+PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
SelectionDAG &DAG,
int &VarArgsFrameIndex,
int &VarArgsStackOffset,
@@ -1349,8 +1349,8 @@
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo();
MachineRegisterInfo &RegInfo = MF.getRegInfo();
- SmallVector<SDOperand, 8> ArgValues;
- SDOperand Root = Op.getOperand(0);
+ SmallVector<SDValue, 8> ArgValues;
+ SDValue Root = Op.getOperand(0);
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
@@ -1449,10 +1449,10 @@
// represented with two words (long long or double) must be copied to an
// even GPR_idx value or to an even ArgOffset value.
- SmallVector<SDOperand, 8> MemOps;
+ SmallVector<SDValue, 8> MemOps;
unsigned nAltivecParamsAtEnd = 0;
for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
- SDOperand ArgVal;
+ SDValue ArgVal;
bool needsLoad = false;
MVT ObjectVT = Op.getValue(ArgNo).getValueType();
unsigned ObjSize = ObjectVT.getSizeInBits()/8;
@@ -1497,14 +1497,14 @@
}
// The value of the object is its address.
int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset);
- SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
+ SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
ArgValues.push_back(FIN);
if (ObjSize==1 || ObjSize==2) {
if (GPR_idx != Num_GPR_Regs) {
unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
RegInfo.addLiveIn(GPR[GPR_idx], VReg);
- SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
- SDOperand Store = DAG.getTruncStore(Val.getValue(1), Val, FIN,
+ SDValue Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
+ SDValue Store = DAG.getTruncStore(Val.getValue(1), Val, FIN,
NULL, 0, ObjSize==1 ? MVT::i8 : MVT::i16 );
MemOps.push_back(Store);
++GPR_idx;
@@ -1522,9 +1522,9 @@
unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
RegInfo.addLiveIn(GPR[GPR_idx], VReg);
int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset);
- SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
- SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
- SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
+ SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
+ SDValue Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
+ SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
MemOps.push_back(Store);
++GPR_idx;
if (isMachoABI) ArgOffset += PtrByteSize;
@@ -1658,7 +1658,7 @@
int FI = MFI->CreateFixedObject(ObjSize,
CurArgOffset + (ArgSize - ObjSize),
isImmutable);
- SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
+ SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
}
@@ -1708,17 +1708,17 @@
VarArgsFrameIndex = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
depth);
- SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
+ SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
// In ELF 32 ABI, the fixed integer arguments of a variadic function are
// stored to the VarArgsFrameIndex on the stack.
if (isELF32_ABI) {
for (GPR_idx = 0; GPR_idx != VarArgsNumGPR; ++GPR_idx) {
- SDOperand Val = DAG.getRegister(GPR[GPR_idx], PtrVT);
- SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0);
+ SDValue Val = DAG.getRegister(GPR[GPR_idx], PtrVT);
+ SDValue Store = DAG.getStore(Root, Val, FIN, NULL, 0);
MemOps.push_back(Store);
// Increment the address by four for the next argument to store
- SDOperand PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
+ SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
}
}
@@ -1734,11 +1734,11 @@
VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
RegInfo.addLiveIn(GPR[GPR_idx], VReg);
- SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
- SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
+ SDValue Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
+ SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
MemOps.push_back(Store);
// Increment the address by four for the next argument to store
- SDOperand PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
+ SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
}
@@ -1746,11 +1746,11 @@
// on the stack.
if (isELF32_ABI) {
for (FPR_idx = 0; FPR_idx != VarArgsNumFPR; ++FPR_idx) {
- SDOperand Val = DAG.getRegister(FPR[FPR_idx], MVT::f64);
- SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0);
+ SDValue Val = DAG.getRegister(FPR[FPR_idx], MVT::f64);
+ SDValue Store = DAG.getStore(Root, Val, FIN, NULL, 0);
MemOps.push_back(Store);
// Increment the address by eight for the next argument to store
- SDOperand PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
+ SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
PtrVT);
FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
}
@@ -1760,11 +1760,11 @@
VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
RegInfo.addLiveIn(FPR[FPR_idx], VReg);
- SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::f64);
- SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
+ SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::f64);
+ SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
MemOps.push_back(Store);
// Increment the address by eight for the next argument to store
- SDOperand PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
+ SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
PtrVT);
FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
}
@@ -1789,7 +1789,7 @@
bool isMachoABI,
bool isVarArg,
unsigned CC,
- SDOperand Call,
+ SDValue Call,
unsigned &nAltivecParamsAtEnd) {
// Count how many bytes are to be pushed on the stack, including the linkage
// area, and parameter passing area. We start with 24/48 bytes, which is
@@ -1806,8 +1806,8 @@
// 16-byte aligned.
nAltivecParamsAtEnd = 0;
for (unsigned i = 0; i != NumOps; ++i) {
- SDOperand Arg = Call.getOperand(5+2*i);
- SDOperand Flag = Call.getOperand(5+2*i+1);
+ SDValue Arg = Call.getOperand(5+2*i);
+ SDValue Flag = Call.getOperand(5+2*i+1);
MVT ArgVT = Arg.getValueType();
// Varargs Altivec parameters are padded to a 16 byte boundary.
if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
@@ -1871,8 +1871,8 @@
/// calling conventions match, currently only fastcc supports tail calls, and
/// the function CALL is immediatly followed by a RET.
bool
-PPCTargetLowering::IsEligibleForTailCallOptimization(SDOperand Call,
- SDOperand Ret,
+PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Call,
+ SDValue Ret,
SelectionDAG& DAG) const {
// Variable argument functions are not supported.
if (!PerformTailCallOpt ||
@@ -1890,7 +1890,7 @@
if (Flags.isByVal()) return false;
}
- SDOperand Callee = Call.getOperand(4);
+ SDValue Callee = Call.getOperand(4);
// Non PIC/GOT tail calls are supported.
if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
return true;
@@ -1908,7 +1908,7 @@
/// isCallCompatibleAddress - Return the immediate to use if the specified
/// 32-bit value is representable in the immediate field of a BxA instruction.
-static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) {
+static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
if (!C) return 0;
@@ -1924,8 +1924,8 @@
namespace {
struct TailCallArgumentInfo {
- SDOperand Arg;
- SDOperand FrameIdxOp;
+ SDValue Arg;
+ SDValue FrameIdxOp;
int FrameIdx;
TailCallArgumentInfo() : FrameIdx(0) {}
@@ -1936,12 +1936,12 @@
/// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
static void
StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
- SDOperand Chain,
+ SDValue Chain,
const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
- SmallVector<SDOperand, 8> &MemOpChains) {
+ SmallVector<SDValue, 8> &MemOpChains) {
for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
- SDOperand Arg = TailCallArgs[i].Arg;
- SDOperand FIN = TailCallArgs[i].FrameIdxOp;
+ SDValue Arg = TailCallArgs[i].Arg;
+ SDValue FIN = TailCallArgs[i].FrameIdxOp;
int FI = TailCallArgs[i].FrameIdx;
// Store relative to framepointer.
MemOpChains.push_back(DAG.getStore(Chain, Arg, FIN,
@@ -1952,11 +1952,11 @@
/// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
/// the appropriate stack slot for the tail call optimized function call.
-static SDOperand EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
+static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
MachineFunction &MF,
- SDOperand Chain,
- SDOperand OldRetAddr,
- SDOperand OldFP,
+ SDValue Chain,
+ SDValue OldRetAddr,
+ SDValue OldFP,
int SPDiff,
bool isPPC64,
bool isMachoABI) {
@@ -1972,10 +1972,10 @@
int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc);
MVT VT = isPPC64 ? MVT::i64 : MVT::i32;
- SDOperand NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
+ SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
Chain = DAG.getStore(Chain, OldRetAddr, NewRetAddrFrIdx,
PseudoSourceValue::getFixedStack(NewRetAddr), 0);
- SDOperand NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
+ SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
Chain = DAG.getStore(Chain, OldFP, NewFramePtrIdx,
PseudoSourceValue::getFixedStack(NewFPIdx), 0);
}
@@ -1986,13 +1986,13 @@
/// the position of the argument.
static void
CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
- SDOperand Arg, int SPDiff, unsigned ArgOffset,
+ SDValue Arg, int SPDiff, unsigned ArgOffset,
SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
int Offset = ArgOffset + SPDiff;
uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
MVT VT = isPPC64 ? MVT::i64 : MVT::i32;
- SDOperand FIN = DAG.getFrameIndex(FI, VT);
+ SDValue FIN = DAG.getFrameIndex(FI, VT);
TailCallArgumentInfo Info;
Info.Arg = Arg;
Info.FrameIdxOp = FIN;
@@ -2003,20 +2003,20 @@
/// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
/// stack slot. Returns the chain as result and the loaded frame pointers in
/// LROpOut/FPOpout. Used when tail calling.
-SDOperand PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
+SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
int SPDiff,
- SDOperand Chain,
- SDOperand &LROpOut,
- SDOperand &FPOpOut) {
+ SDValue Chain,
+ SDValue &LROpOut,
+ SDValue &FPOpOut) {
if (SPDiff) {
// Load the LR and FP stack slot for later adjusting.
MVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
LROpOut = getReturnAddrFrameIndex(DAG);
LROpOut = DAG.getLoad(VT, Chain, LROpOut, NULL, 0);
- Chain = SDOperand(LROpOut.Val, 1);
+ Chain = SDValue(LROpOut.Val, 1);
FPOpOut = getFramePointerFrameIndex(DAG);
FPOpOut = DAG.getLoad(VT, Chain, FPOpOut, NULL, 0);
- Chain = SDOperand(FPOpOut.Val, 1);
+ Chain = SDValue(FPOpOut.Val, 1);
}
return Chain;
}
@@ -2027,11 +2027,11 @@
/// a byval function parameter.
/// Sometimes what we are copying is the end of a larger object, the part that
/// does not fit in registers.
-static SDOperand
-CreateCopyOfByValArgument(SDOperand Src, SDOperand Dst, SDOperand Chain,
+static SDValue
+CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
unsigned Size) {
- SDOperand SizeNode = DAG.getConstant(Size, MVT::i32);
+ SDValue SizeNode = DAG.getConstant(Size, MVT::i32);
return DAG.getMemcpy(Chain, Dst, Src, SizeNode, Flags.getByValAlign(), false,
NULL, 0, NULL, 0);
}
@@ -2039,15 +2039,15 @@
/// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
/// tail calls.
static void
-LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDOperand Chain,
- SDOperand Arg, SDOperand PtrOff, int SPDiff,
+LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
+ SDValue Arg, SDValue PtrOff, int SPDiff,
unsigned ArgOffset, bool isPPC64, bool isTailCall,
- bool isVector, SmallVector<SDOperand, 8> &MemOpChains,
+ bool isVector, SmallVector<SDValue, 8> &MemOpChains,
SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
if (!isTailCall) {
if (isVector) {
- SDOperand StackPtr;
+ SDValue StackPtr;
if (isPPC64)
StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
else
@@ -2061,15 +2061,15 @@
TailCallArguments);
}
-SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG,
+SDValue PPCTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG,
const PPCSubtarget &Subtarget,
TargetMachine &TM) {
- SDOperand Chain = Op.getOperand(0);
+ SDValue Chain = Op.getOperand(0);
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0 &&
CC == CallingConv::Fast && PerformTailCallOpt;
- SDOperand Callee = Op.getOperand(4);
+ SDValue Callee = Op.getOperand(4);
unsigned NumOps = (Op.getNumOperands() - 5) / 2;
bool isMachoABI = Subtarget.isMachoABI();
@@ -2083,7 +2083,7 @@
// args_to_use will accumulate outgoing args for the PPCISD::CALL case in
// SelectExpr to use to put the arguments in the appropriate registers.
- std::vector<SDOperand> args_to_use;
+ std::vector<SDValue> args_to_use;
// Mark this function as potentially containing a function that contains a
// tail call. As a consequence the frame pointer will be used for dynamicalloc
@@ -2110,17 +2110,17 @@
// These operations are automatically eliminated by the prolog/epilog pass
Chain = DAG.getCALLSEQ_START(Chain,
DAG.getConstant(NumBytes, PtrVT));
- SDOperand CallSeqStart = Chain;
+ SDValue CallSeqStart = Chain;
// Load the return address and frame pointer so it can be move somewhere else
// later.
- SDOperand LROp, FPOp;
+ SDValue LROp, FPOp;
Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp);
// Set up a copy of the stack pointer for use loading and storing any
// arguments that may not fit in the registers available for argument
// passing.
- SDOperand StackPtr;
+ SDValue StackPtr;
if (isPPC64)
StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
else
@@ -2153,13 +2153,13 @@
const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
- std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
+ std::vector<std::pair<unsigned, SDValue> > RegsToPass;
SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
- SmallVector<SDOperand, 8> MemOpChains;
+ SmallVector<SDValue, 8> MemOpChains;
for (unsigned i = 0; i != NumOps; ++i) {
bool inMem = false;
- SDOperand Arg = Op.getOperand(5+2*i);
+ SDValue Arg = Op.getOperand(5+2*i);
ISD::ArgFlagsTy Flags =
cast<ARG_FLAGSSDNode>(Op.getOperand(5+2*i+1))->getArgFlags();
// See if next argument requires stack alignment in ELF
@@ -2167,7 +2167,7 @@
// PtrOff will be used to store the current argument to the stack if a
// register cannot be found for it.
- SDOperand PtrOff;
+ SDValue PtrOff;
// Stack align in ELF 32
if (isELF32_ABI && Align)
@@ -2195,20 +2195,20 @@
// Everything else is passed left-justified.
MVT VT = (Size==1) ? MVT::i8 : MVT::i16;
if (GPR_idx != NumGPRs) {
- SDOperand Load = DAG.getExtLoad(ISD::EXTLOAD, PtrVT, Chain, Arg,
+ SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, PtrVT, Chain, Arg,
NULL, 0, VT);
MemOpChains.push_back(Load.getValue(1));
RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
if (isMachoABI)
ArgOffset += PtrByteSize;
} else {
- SDOperand Const = DAG.getConstant(4 - Size, PtrOff.getValueType());
- SDOperand AddPtr = DAG.getNode(ISD::ADD, PtrVT, PtrOff, Const);
- SDOperand MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr,
+ SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType());
+ SDValue AddPtr = DAG.getNode(ISD::ADD, PtrVT, PtrOff, Const);
+ SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr,
CallSeqStart.Val->getOperand(0),
Flags, DAG, Size);
// This must go outside the CALLSEQ_START..END.
- SDOperand NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
+ SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
CallSeqStart.Val->getOperand(1));
DAG.ReplaceAllUsesWith(CallSeqStart.Val, NewCallSeqStart.Val);
Chain = CallSeqStart = NewCallSeqStart;
@@ -2219,20 +2219,20 @@
// Copy entire object into memory. There are cases where gcc-generated
// code assumes it is there, even if it could be put entirely into
// registers. (This is not what the doc says.)
- SDOperand MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
+ SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
CallSeqStart.Val->getOperand(0),
Flags, DAG, Size);
// This must go outside the CALLSEQ_START..END.
- SDOperand NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
+ SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
CallSeqStart.Val->getOperand(1));
DAG.ReplaceAllUsesWith(CallSeqStart.Val, NewCallSeqStart.Val);
Chain = CallSeqStart = NewCallSeqStart;
// And copy the pieces of it that fit into registers.
for (unsigned j=0; j<Size; j+=PtrByteSize) {
- SDOperand Const = DAG.getConstant(j, PtrOff.getValueType());
- SDOperand AddArg = DAG.getNode(ISD::ADD, PtrVT, Arg, Const);
+ SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
+ SDValue AddArg = DAG.getNode(ISD::ADD, PtrVT, Arg, Const);
if (GPR_idx != NumGPRs) {
- SDOperand Load = DAG.getLoad(PtrVT, Chain, AddArg, NULL, 0);
+ SDValue Load = DAG.getLoad(PtrVT, Chain, AddArg, NULL, 0);
MemOpChains.push_back(Load.getValue(1));
RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
if (isMachoABI)
@@ -2273,20 +2273,20 @@
RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
if (isVarArg) {
- SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
+ SDValue Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
MemOpChains.push_back(Store);
// Float varargs are always shadowed in available integer registers
if (GPR_idx != NumGPRs) {
- SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
+ SDValue Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
MemOpChains.push_back(Load.getValue(1));
if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
Load));
}
if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
- SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType());
+ SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour);
- SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
+ SDValue Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
MemOpChains.push_back(Load.getValue(1));
if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
Load));
@@ -2338,10 +2338,10 @@
// entirely in R registers. Maybe later.
PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr,
DAG.getConstant(ArgOffset, PtrVT));
- SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
+ SDValue Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
MemOpChains.push_back(Store);
if (VR_idx != NumVRs) {
- SDOperand Load = DAG.getLoad(MVT::v4f32, Store, PtrOff, NULL, 0);
+ SDValue Load = DAG.getLoad(MVT::v4f32, Store, PtrOff, NULL, 0);
MemOpChains.push_back(Load.getValue(1));
RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
}
@@ -2349,9 +2349,9 @@
for (unsigned i=0; i<16; i+=PtrByteSize) {
if (GPR_idx == NumGPRs)
break;
- SDOperand Ix = DAG.getNode(ISD::ADD, PtrVT, PtrOff,
+ SDValue Ix = DAG.getNode(ISD::ADD, PtrVT, PtrOff,
DAG.getConstant(i, PtrVT));
- SDOperand Load = DAG.getLoad(PtrVT, Store, Ix, NULL, 0);
+ SDValue Load = DAG.getLoad(PtrVT, Store, Ix, NULL, 0);
MemOpChains.push_back(Load.getValue(1));
RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
}
@@ -2384,12 +2384,12 @@
ArgOffset = ((ArgOffset+15)/16)*16;
ArgOffset += 12*16;
for (unsigned i = 0; i != NumOps; ++i) {
- SDOperand Arg = Op.getOperand(5+2*i);
+ SDValue Arg = Op.getOperand(5+2*i);
MVT ArgType = Arg.getValueType();
if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
if (++j > NumVRs) {
- SDOperand PtrOff;
+ SDValue PtrOff;
// We are emitting Altivec params in order.
LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
isPPC64, isTailCall, true, MemOpChains,
@@ -2406,7 +2406,7 @@
// Build a sequence of copy-to-reg nodes chained together with token chain
// and flag operands which copy the outgoing args into the appropriate regs.
- SDOperand InFlag;
+ SDValue InFlag;
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
InFlag);
@@ -2415,7 +2415,7 @@
// With the ELF 32 ABI, set CR6 to true if this is a vararg call.
if (isVarArg && isELF32_ABI) {
- SDOperand SetCR(DAG.getTargetNode(PPC::CRSET, MVT::i32), 0);
+ SDValue SetCR(DAG.getTargetNode(PPC::CRSET, MVT::i32), 0);
Chain = DAG.getCopyToReg(Chain, PPC::CR1EQ, SetCR, InFlag);
InFlag = Chain.getValue(1);
}
@@ -2423,9 +2423,9 @@
// Emit a sequence of copyto/copyfrom virtual registers for arguments that
// might overwrite each other in case of tail call optimization.
if (isTailCall) {
- SmallVector<SDOperand, 8> MemOpChains2;
+ SmallVector<SDValue, 8> MemOpChains2;
// Do not flag preceeding copytoreg stuff together with the following stuff.
- InFlag = SDOperand();
+ InFlag = SDValue();
StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
MemOpChains2);
if (!MemOpChains2.empty())
@@ -2439,7 +2439,7 @@
// Emit callseq_end just before tailcall node.
if (isTailCall) {
- SmallVector<SDOperand, 8> CallSeqOps;
+ SmallVector<SDValue, 8> CallSeqOps;
SDVTList CallSeqNodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
CallSeqOps.push_back(Chain);
CallSeqOps.push_back(DAG.getIntPtrConstant(NumBytes));
@@ -2455,7 +2455,7 @@
NodeTys.push_back(MVT::Other); // Returns a chain
NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
- SmallVector<SDOperand, 8> Ops;
+ SmallVector<SDValue, 8> Ops;
unsigned CallOpc = isMachoABI? PPCISD::CALL_Macho : PPCISD::CALL_ELF;
// If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
@@ -2467,11 +2467,11 @@
Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
// If this is an absolute destination address, use the munged value.
- Callee = SDOperand(Dest, 0);
+ Callee = SDValue(Dest, 0);
else {
// Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
// to do the call, we can't use PPCISD::CALL.
- SDOperand MTCTROps[] = {Chain, Callee, InFlag};
+ SDValue MTCTROps[] = {Chain, Callee, InFlag};
Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0));
InFlag = Chain.getValue(1);
@@ -2523,7 +2523,7 @@
"Flag must be set. Depend on flag being set in LowerRET");
Chain = DAG.getNode(PPCISD::TAILCALL,
Op.Val->getVTList(), &Ops[0], Ops.size());
- return SDOperand(Chain.Val, Op.ResNo);
+ return SDValue(Chain.Val, Op.ResNo);
}
Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
@@ -2536,7 +2536,7 @@
if (Op.Val->getValueType(0) != MVT::Other)
InFlag = Chain.getValue(1);
- SmallVector<SDOperand, 16> ResultVals;
+ SmallVector<SDValue, 16> ResultVals;
SmallVector<CCValAssign, 16> RVLocs;
unsigned CallerCC = DAG.getMachineFunction().getFunction()->getCallingConv();
CCState CCInfo(CallerCC, isVarArg, TM, RVLocs);
@@ -2558,12 +2558,12 @@
// Otherwise, merge everything together with a MERGE_VALUES node.
ResultVals.push_back(Chain);
- SDOperand Res = DAG.getMergeValues(Op.Val->getVTList(), &ResultVals[0],
+ SDValue Res = DAG.getMergeValues(Op.Val->getVTList(), &ResultVals[0],
ResultVals.size());
return Res.getValue(Op.ResNo);
}
-SDOperand PPCTargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG,
+SDValue PPCTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG,
TargetMachine &TM) {
SmallVector<CCValAssign, 16> RVLocs;
unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
@@ -2578,13 +2578,13 @@
DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
}
- SDOperand Chain = Op.getOperand(0);
+ SDValue Chain = Op.getOperand(0);
Chain = GetPossiblePreceedingTailCall(Chain, PPCISD::TAILCALL);
if (Chain.getOpcode() == PPCISD::TAILCALL) {
- SDOperand TailCall = Chain;
- SDOperand TargetAddress = TailCall.getOperand(1);
- SDOperand StackAdjustment = TailCall.getOperand(2);
+ SDValue TailCall = Chain;
+ SDValue TargetAddress = TailCall.getOperand(1);
+ SDValue StackAdjustment = TailCall.getOperand(2);
assert(((TargetAddress.getOpcode() == ISD::Register &&
cast<RegisterSDNode>(TargetAddress)->getReg() == PPC::CTR) ||
@@ -2596,7 +2596,7 @@
assert(StackAdjustment.getOpcode() == ISD::Constant &&
"Expecting a const value");
- SmallVector<SDOperand,8> Operands;
+ SmallVector<SDValue,8> Operands;
Operands.push_back(Chain.getOperand(0));
Operands.push_back(TargetAddress);
Operands.push_back(StackAdjustment);
@@ -2609,7 +2609,7 @@
Operands.size());
}
- SDOperand Flag;
+ SDValue Flag;
// Copy the result values into the output registers.
for (unsigned i = 0; i != RVLocs.size(); ++i) {
@@ -2625,7 +2625,7 @@
return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain);
}
-SDOperand PPCTargetLowering::LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG,
+SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
const PPCSubtarget &Subtarget) {
// When we pop the dynamic allocation we need to restore the SP link.
@@ -2635,14 +2635,14 @@
// Construct the stack pointer operand.
bool IsPPC64 = Subtarget.isPPC64();
unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1;
- SDOperand StackPtr = DAG.getRegister(SP, PtrVT);
+ SDValue StackPtr = DAG.getRegister(SP, PtrVT);
// Get the operands for the STACKRESTORE.
- SDOperand Chain = Op.getOperand(0);
- SDOperand SaveSP = Op.getOperand(1);
+ SDValue Chain = Op.getOperand(0);
+ SDValue SaveSP = Op.getOperand(1);
// Load the old link SP.
- SDOperand LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0);
+ SDValue LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0);
// Restore the stack pointer.
Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), SP, SaveSP);
@@ -2653,7 +2653,7 @@
-SDOperand
+SDValue
PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
MachineFunction &MF = DAG.getMachineFunction();
bool IsPPC64 = PPCSubTarget.isPPC64();
@@ -2677,7 +2677,7 @@
return DAG.getFrameIndex(RASI, PtrVT);
}
-SDOperand
+SDValue
PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
MachineFunction &MF = DAG.getMachineFunction();
bool IsPPC64 = PPCSubTarget.isPPC64();
@@ -2702,34 +2702,34 @@
return DAG.getFrameIndex(FPSI, PtrVT);
}
-SDOperand PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op,
+SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
SelectionDAG &DAG,
const PPCSubtarget &Subtarget) {
// Get the inputs.
- SDOperand Chain = Op.getOperand(0);
- SDOperand Size = Op.getOperand(1);
+ SDValue Chain = Op.getOperand(0);
+ SDValue Size = Op.getOperand(1);
// Get the corect type for pointers.
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
// Negate the size.
- SDOperand NegSize = DAG.getNode(ISD::SUB, PtrVT,
+ SDValue NegSize = DAG.getNode(ISD::SUB, PtrVT,
DAG.getConstant(0, PtrVT), Size);
// Construct a node for the frame pointer save index.
- SDOperand FPSIdx = getFramePointerFrameIndex(DAG);
+ SDValue FPSIdx = getFramePointerFrameIndex(DAG);
// Build a DYNALLOC node.
- SDOperand Ops[3] = { Chain, NegSize, FPSIdx };
+ SDValue Ops[3] = { Chain, NegSize, FPSIdx };
SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3);
}
-SDOperand PPCTargetLowering::LowerAtomicLOAD_ADD(SDOperand Op, SelectionDAG &DAG) {
+SDValue PPCTargetLowering::LowerAtomicLOAD_ADD(SDValue Op, SelectionDAG &DAG) {
MVT VT = Op.Val->getValueType(0);
- SDOperand Chain = Op.getOperand(0);
- SDOperand Ptr = Op.getOperand(1);
- SDOperand Incr = Op.getOperand(2);
+ SDValue Chain = Op.getOperand(0);
+ SDValue Ptr = Op.getOperand(1);
+ SDValue Incr = Op.getOperand(2);
SDVTList VTs = DAG.getVTList(VT, MVT::Other);
- SDOperand Ops[] = {
+ SDValue Ops[] = {
Chain,
Ptr,
Incr,
@@ -2737,15 +2737,15 @@
return DAG.getNode(PPCISD::ATOMIC_LOAD_ADD, VTs, Ops, 3);
}
-SDOperand PPCTargetLowering::LowerAtomicCMP_SWAP(SDOperand Op, SelectionDAG &DAG) {
+SDValue PPCTargetLowering::LowerAtomicCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
MVT VT = Op.Val->getValueType(0);
- SDOperand Chain = Op.getOperand(0);
- SDOperand Ptr = Op.getOperand(1);
- SDOperand NewVal = Op.getOperand(2);
- SDOperand OldVal = Op.getOperand(3);
+ SDValue Chain = Op.getOperand(0);
+ SDValue Ptr = Op.getOperand(1);
+ SDValue NewVal = Op.getOperand(2);
+ SDValue OldVal = Op.getOperand(3);
SDVTList VTs = DAG.getVTList(VT, MVT::Other);
- SDOperand Ops[] = {
+ SDValue Ops[] = {
Chain,
Ptr,
OldVal,
@@ -2754,14 +2754,14 @@
return DAG.getNode(PPCISD::ATOMIC_CMP_SWAP, VTs, Ops, 4);
}
-SDOperand PPCTargetLowering::LowerAtomicSWAP(SDOperand Op, SelectionDAG &DAG) {
+SDValue PPCTargetLowering::LowerAtomicSWAP(SDValue Op, SelectionDAG &DAG) {
MVT VT = Op.Val->getValueType(0);
- SDOperand Chain = Op.getOperand(0);
- SDOperand Ptr = Op.getOperand(1);
- SDOperand NewVal = Op.getOperand(2);
+ SDValue Chain = Op.getOperand(0);
+ SDValue Ptr = Op.getOperand(1);
+ SDValue NewVal = Op.getOperand(2);
SDVTList VTs = DAG.getVTList(VT, MVT::Other);
- SDOperand Ops[] = {
+ SDValue Ops[] = {
Chain,
Ptr,
NewVal,
@@ -2771,21 +2771,21 @@
/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
/// possible.
-SDOperand PPCTargetLowering::LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
+SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
// Not FP? Not a fsel.
if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
!Op.getOperand(2).getValueType().isFloatingPoint())
- return SDOperand();
+ return SDValue();
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
// Cannot handle SETEQ/SETNE.
- if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand();
+ if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDValue();
MVT ResVT = Op.getValueType();
MVT CmpVT = Op.getOperand(0).getValueType();
- SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
- SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
+ SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
+ SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
// If the RHS of the comparison is a 0.0, we don't need to do the
// subtraction at all.
@@ -2815,7 +2815,7 @@
DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
}
- SDOperand Cmp;
+ SDValue Cmp;
switch (CC) {
default: break; // SETUO etc aren't handled by fsel.
case ISD::SETULT:
@@ -2847,17 +2847,17 @@
Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
}
- return SDOperand();
+ return SDValue();
}
// FIXME: Split this code up when LegalizeDAGTypes lands.
-SDOperand PPCTargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
+SDValue PPCTargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
assert(Op.getOperand(0).getValueType().isFloatingPoint());
- SDOperand Src = Op.getOperand(0);
+ SDValue Src = Op.getOperand(0);
if (Src.getValueType() == MVT::f32)
Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
- SDOperand Tmp;
+ SDValue Tmp;
switch (Op.getValueType().getSimpleVT()) {
default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
case MVT::i32:
@@ -2869,10 +2869,10 @@
}
// Convert the FP value to an int value through memory.
- SDOperand FIPtr = DAG.CreateStackTemporary(MVT::f64);
+ SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64);
// Emit a store to the stack slot.
- SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Tmp, FIPtr, NULL, 0);
+ SDValue Chain = DAG.getStore(DAG.getEntryNode(), Tmp, FIPtr, NULL, 0);
// Result is a load from the stack slot. If loading 4 bytes, make sure to
// add in a bias.
@@ -2882,20 +2882,20 @@
return DAG.getLoad(Op.getValueType(), Chain, FIPtr, NULL, 0);
}
-SDOperand PPCTargetLowering::LowerFP_ROUND_INREG(SDOperand Op,
+SDValue PPCTargetLowering::LowerFP_ROUND_INREG(SDValue Op,
SelectionDAG &DAG) {
assert(Op.getValueType() == MVT::ppcf128);
SDNode *Node = Op.Val;
assert(Node->getOperand(0).getValueType() == MVT::ppcf128);
assert(Node->getOperand(0).Val->getOpcode() == ISD::BUILD_PAIR);
- SDOperand Lo = Node->getOperand(0).Val->getOperand(0);
- SDOperand Hi = Node->getOperand(0).Val->getOperand(1);
+ SDValue Lo = Node->getOperand(0).Val->getOperand(0);
+ SDValue Hi = Node->getOperand(0).Val->getOperand(1);
// This sequence changes FPSCR to do round-to-zero, adds the two halves
// of the long double, and puts FPSCR back the way it was. We do not
// actually model FPSCR.
std::vector<MVT> NodeTys;
- SDOperand Ops[4], Result, MFFSreg, InFlag, FPreg;
+ SDValue Ops[4], Result, MFFSreg, InFlag, FPreg;
NodeTys.push_back(MVT::f64); // Return register
NodeTys.push_back(MVT::Flag); // Returns a flag for later insns
@@ -2941,14 +2941,14 @@
return DAG.getNode(ISD::BUILD_PAIR, Lo.getValueType(), FPreg, FPreg);
}
-SDOperand PPCTargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
+SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
// Don't handle ppc_fp128 here; let it be lowered to a libcall.
if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
- return SDOperand();
+ return SDValue();
if (Op.getOperand(0).getValueType() == MVT::i64) {
- SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
- SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
+ SDValue Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
+ SDValue FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
if (Op.getValueType() == MVT::f32)
FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0));
return FP;
@@ -2963,28 +2963,28 @@
MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
int FrameIdx = FrameInfo->CreateStackObject(8, 8);
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
- SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
+ SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
- SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32,
+ SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32,
Op.getOperand(0));
// STD the extended value into the stack slot.
MachineMemOperand MO(PseudoSourceValue::getFixedStack(FrameIdx),
MachineMemOperand::MOStore, 0, 8, 8);
- SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other,
+ SDValue Store = DAG.getNode(PPCISD::STD_32, MVT::Other,
DAG.getEntryNode(), Ext64, FIdx,
DAG.getMemOperand(MO));
// Load the value as a double.
- SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0);
+ SDValue Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0);
// FCFID it and return it.
- SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
+ SDValue FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
if (Op.getValueType() == MVT::f32)
FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0));
return FP;
}
-SDOperand PPCTargetLowering::LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG) {
+SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
/*
The rounding mode is in bits 30:31 of FPSR, and has the following
settings:
@@ -3008,29 +3008,29 @@
MVT VT = Op.getValueType();
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
std::vector<MVT> NodeTys;
- SDOperand MFFSreg, InFlag;
+ SDValue MFFSreg, InFlag;
// Save FP Control Word to register
NodeTys.push_back(MVT::f64); // return register
NodeTys.push_back(MVT::Flag); // unused in this context
- SDOperand Chain = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0);
+ SDValue Chain = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0);
// Save FP register to stack slot
int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
- SDOperand StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
- SDOperand Store = DAG.getStore(DAG.getEntryNode(), Chain,
+ SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
+ SDValue Store = DAG.getStore(DAG.getEntryNode(), Chain,
StackSlot, NULL, 0);
// Load FP Control Word from low 32 bits of stack slot.
- SDOperand Four = DAG.getConstant(4, PtrVT);
- SDOperand Addr = DAG.getNode(ISD::ADD, PtrVT, StackSlot, Four);
- SDOperand CWD = DAG.getLoad(MVT::i32, Store, Addr, NULL, 0);
+ SDValue Four = DAG.getConstant(4, PtrVT);
+ SDValue Addr = DAG.getNode(ISD::ADD, PtrVT, StackSlot, Four);
+ SDValue CWD = DAG.getLoad(MVT::i32, Store, Addr, NULL, 0);
// Transform as necessary
- SDOperand CWD1 =
+ SDValue CWD1 =
DAG.getNode(ISD::AND, MVT::i32,
CWD, DAG.getConstant(3, MVT::i32));
- SDOperand CWD2 =
+ SDValue CWD2 =
DAG.getNode(ISD::SRL, MVT::i32,
DAG.getNode(ISD::AND, MVT::i32,
DAG.getNode(ISD::XOR, MVT::i32,
@@ -3038,14 +3038,14 @@
DAG.getConstant(3, MVT::i32)),
DAG.getConstant(1, MVT::i8));
- SDOperand RetVal =
+ SDValue RetVal =
DAG.getNode(ISD::XOR, MVT::i32, CWD1, CWD2);
return DAG.getNode((VT.getSizeInBits() < 16 ?
ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
}
-SDOperand PPCTargetLowering::LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) {
+SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) {
MVT VT = Op.getValueType();
unsigned BitWidth = VT.getSizeInBits();
assert(Op.getNumOperands() == 3 &&
@@ -3054,26 +3054,26 @@
// Expand into a bunch of logical ops. Note that these ops
// depend on the PPC behavior for oversized shift amounts.
- SDOperand Lo = Op.getOperand(0);
- SDOperand Hi = Op.getOperand(1);
- SDOperand Amt = Op.getOperand(2);
+ SDValue Lo = Op.getOperand(0);
+ SDValue Hi = Op.getOperand(1);
+ SDValue Amt = Op.getOperand(2);
MVT AmtVT = Amt.getValueType();
- SDOperand Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
+ SDValue Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
DAG.getConstant(BitWidth, AmtVT), Amt);
- SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, VT, Hi, Amt);
- SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, VT, Lo, Tmp1);
- SDOperand Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3);
- SDOperand Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt,
+ SDValue Tmp2 = DAG.getNode(PPCISD::SHL, VT, Hi, Amt);
+ SDValue Tmp3 = DAG.getNode(PPCISD::SRL, VT, Lo, Tmp1);
+ SDValue Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3);
+ SDValue Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt,
DAG.getConstant(-BitWidth, AmtVT));
- SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, VT, Lo, Tmp5);
- SDOperand OutHi = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6);
- SDOperand OutLo = DAG.getNode(PPCISD::SHL, VT, Lo, Amt);
- SDOperand OutOps[] = { OutLo, OutHi };
+ SDValue Tmp6 = DAG.getNode(PPCISD::SHL, VT, Lo, Tmp5);
+ SDValue OutHi = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6);
+ SDValue OutLo = DAG.getNode(PPCISD::SHL, VT, Lo, Amt);
+ SDValue OutOps[] = { OutLo, OutHi };
return DAG.getMergeValues(OutOps, 2);
}
-SDOperand PPCTargetLowering::LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) {
+SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) {
MVT VT = Op.getValueType();
unsigned BitWidth = VT.getSizeInBits();
assert(Op.getNumOperands() == 3 &&
@@ -3082,26 +3082,26 @@
// Expand into a bunch of logical ops. Note that these ops
// depend on the PPC behavior for oversized shift amounts.
- SDOperand Lo = Op.getOperand(0);
- SDOperand Hi = Op.getOperand(1);
- SDOperand Amt = Op.getOperand(2);
+ SDValue Lo = Op.getOperand(0);
+ SDValue Hi = Op.getOperand(1);
+ SDValue Amt = Op.getOperand(2);
MVT AmtVT = Amt.getValueType();
- SDOperand Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
+ SDValue Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
DAG.getConstant(BitWidth, AmtVT), Amt);
- SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt);
- SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1);
- SDOperand Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3);
- SDOperand Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt,
+ SDValue Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt);
+ SDValue Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1);
+ SDValue Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3);
+ SDValue Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt,
DAG.getConstant(-BitWidth, AmtVT));
- SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, VT, Hi, Tmp5);
- SDOperand OutLo = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6);
- SDOperand OutHi = DAG.getNode(PPCISD::SRL, VT, Hi, Amt);
- SDOperand OutOps[] = { OutLo, OutHi };
+ SDValue Tmp6 = DAG.getNode(PPCISD::SRL, VT, Hi, Tmp5);
+ SDValue OutLo = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6);
+ SDValue OutHi = DAG.getNode(PPCISD::SRL, VT, Hi, Amt);
+ SDValue OutOps[] = { OutLo, OutHi };
return DAG.getMergeValues(OutOps, 2);
}
-SDOperand PPCTargetLowering::LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) {
+SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) {
MVT VT = Op.getValueType();
unsigned BitWidth = VT.getSizeInBits();
assert(Op.getNumOperands() == 3 &&
@@ -3109,23 +3109,23 @@
"Unexpected SRA!");
// Expand into a bunch of logical ops, followed by a select_cc.
- SDOperand Lo = Op.getOperand(0);
- SDOperand Hi = Op.getOperand(1);
- SDOperand Amt = Op.getOperand(2);
+ SDValue Lo = Op.getOperand(0);
+ SDValue Hi = Op.getOperand(1);
+ SDValue Amt = Op.getOperand(2);
MVT AmtVT = Amt.getValueType();
- SDOperand Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
+ SDValue Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
DAG.getConstant(BitWidth, AmtVT), Amt);
- SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt);
- SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1);
- SDOperand Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3);
- SDOperand Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt,
+ SDValue Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt);
+ SDValue Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1);
+ SDValue Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3);
+ SDValue Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt,
DAG.getConstant(-BitWidth, AmtVT));
- SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, VT, Hi, Tmp5);
- SDOperand OutHi = DAG.getNode(PPCISD::SRA, VT, Hi, Amt);
- SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, AmtVT),
+ SDValue Tmp6 = DAG.getNode(PPCISD::SRA, VT, Hi, Tmp5);
+ SDValue OutHi = DAG.getNode(PPCISD::SRA, VT, Hi, Amt);
+ SDValue OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, AmtVT),
Tmp4, Tmp6, ISD::SETLE);
- SDOperand OutOps[] = { OutLo, OutHi };
+ SDValue OutOps[] = { OutLo, OutHi };
return DAG.getMergeValues(OutOps, 2);
}
@@ -3145,7 +3145,7 @@
unsigned EltBitSize = BV->getOperand(0).getValueType().getSizeInBits();
for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
- SDOperand OpVal = BV->getOperand(i);
+ SDValue OpVal = BV->getOperand(i);
unsigned PartNo = i >= e/2; // In the upper 128 bits?
unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t.
@@ -3229,7 +3229,7 @@
/// BuildSplatI - Build a canonical splati of Val with an element size of
/// SplatSize. Cast the result to VT.
-static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT VT,
+static SDValue BuildSplatI(int Val, unsigned SplatSize, MVT VT,
SelectionDAG &DAG) {
assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
@@ -3246,17 +3246,17 @@
MVT CanonicalVT = VTys[SplatSize-1];
// Build a canonical splat for this value.
- SDOperand Elt = DAG.getConstant(Val, CanonicalVT.getVectorElementType());
- SmallVector<SDOperand, 8> Ops;
+ SDValue Elt = DAG.getConstant(Val, CanonicalVT.getVectorElementType());
+ SmallVector<SDValue, 8> Ops;
Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
- SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT,
+ SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT,
&Ops[0], Ops.size());
return DAG.getNode(ISD::BIT_CONVERT, ReqVT, Res);
}
/// BuildIntrinsicOp - Return a binary operator intrinsic node with the
/// specified intrinsic ID.
-static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS,
+static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
SelectionDAG &DAG,
MVT DestVT = MVT::Other) {
if (DestVT == MVT::Other) DestVT = LHS.getValueType();
@@ -3266,8 +3266,8 @@
/// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
/// specified intrinsic ID.
-static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1,
- SDOperand Op2, SelectionDAG &DAG,
+static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
+ SDValue Op2, SelectionDAG &DAG,
MVT DestVT = MVT::Other) {
if (DestVT == MVT::Other) DestVT = Op0.getValueType();
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
@@ -3277,16 +3277,16 @@
/// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
/// amount. The result has the specified value type.
-static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt,
+static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
MVT VT, SelectionDAG &DAG) {
// Force LHS/RHS to be the right type.
LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS);
RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS);
- SDOperand Ops[16];
+ SDValue Ops[16];
for (unsigned i = 0; i != 16; ++i)
Ops[i] = DAG.getConstant(i+Amt, MVT::i8);
- SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS,
+ SDValue T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS,
DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16));
return DAG.getNode(ISD::BIT_CONVERT, VT, T);
}
@@ -3296,7 +3296,7 @@
// selects to a single instruction, return Op. Otherwise, if we can codegen
// this case more efficiently than a constant pool load, lower it to the
// sequence of ops that should be used.
-SDOperand PPCTargetLowering::LowerBUILD_VECTOR(SDOperand Op,
+SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
SelectionDAG &DAG) {
// If this is a vector of constants or undefs, get the bits. A bit in
// UndefBits is set if the corresponding element of the vector is an
@@ -3305,7 +3305,7 @@
uint64_t VectorBits[2];
uint64_t UndefBits[2];
if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits))
- return SDOperand(); // Not a constant vector.
+ return SDValue(); // Not a constant vector.
// If this is a splat (repetition) of a value across the whole vector, return
// the smallest size that splats it. For example, "0x01010101010101..." is a
@@ -3321,7 +3321,7 @@
if (SplatBits == 0) {
// Canonicalize all zero vectors to be v4i32.
if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
- SDOperand Z = DAG.getConstant(0, MVT::i32);
+ SDValue Z = DAG.getConstant(0, MVT::i32);
Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z);
Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z);
}
@@ -3339,7 +3339,7 @@
// If this value is in the range [-32,30] and is even, use:
// tmp = VSPLTI[bhw], result = add tmp, tmp
if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
- SDOperand Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG);
+ SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG);
Res = DAG.getNode(ISD::ADD, Res.getValueType(), Res, Res);
return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
}
@@ -3349,10 +3349,10 @@
// for fneg/fabs.
if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
// Make -1 and vspltisw -1:
- SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG);
+ SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG);
// Make the VSLW intrinsic, computing 0x8000_0000.
- SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
+ SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
OnesV, DAG);
// xor by OnesV to invert it.
@@ -3378,7 +3378,7 @@
// vsplti + shl self.
if (SextVal == (i << (int)TypeShiftAmt)) {
- SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
+ SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
static const unsigned IIDs[] = { // Intrinsic to use for each size.
Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
Intrinsic::ppc_altivec_vslw
@@ -3389,7 +3389,7 @@
// vsplti + srl self.
if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
- SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
+ SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
static const unsigned IIDs[] = { // Intrinsic to use for each size.
Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
Intrinsic::ppc_altivec_vsrw
@@ -3400,7 +3400,7 @@
// vsplti + sra self.
if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
- SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
+ SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
static const unsigned IIDs[] = { // Intrinsic to use for each size.
Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
Intrinsic::ppc_altivec_vsraw
@@ -3412,7 +3412,7 @@
// vsplti + rol self.
if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
- SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
+ SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
static const unsigned IIDs[] = { // Intrinsic to use for each size.
Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
Intrinsic::ppc_altivec_vrlw
@@ -3423,17 +3423,17 @@
// t = vsplti c, result = vsldoi t, t, 1
if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
- SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
+ SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG);
}
// t = vsplti c, result = vsldoi t, t, 2
if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
- SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
+ SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG);
}
// t = vsplti c, result = vsldoi t, t, 3
if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
- SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
+ SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG);
}
}
@@ -3442,27 +3442,27 @@
// Odd, in range [17,31]: (vsplti C)-(vsplti -16).
if (SextVal >= 0 && SextVal <= 31) {
- SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG);
- SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
+ SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG);
+ SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
LHS = DAG.getNode(ISD::SUB, LHS.getValueType(), LHS, RHS);
return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
}
// Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
if (SextVal >= -31 && SextVal <= 0) {
- SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG);
- SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
+ SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG);
+ SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
LHS = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS);
return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
}
}
- return SDOperand();
+ return SDValue();
}
/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
/// the specified operations to build the shuffle.
-static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS,
- SDOperand RHS, SelectionDAG &DAG) {
+static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
+ SDValue RHS, SelectionDAG &DAG) {
unsigned OpNum = (PFEntry >> 26) & 0x0F;
unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
@@ -3486,7 +3486,7 @@
return RHS;
}
- SDOperand OpLHS, OpRHS;
+ SDValue OpLHS, OpRHS;
OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG);
OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG);
@@ -3528,7 +3528,7 @@
case OP_VSLDOI12:
return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG);
}
- SDOperand Ops[16];
+ SDValue Ops[16];
for (unsigned i = 0; i != 16; ++i)
Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i8);
@@ -3540,11 +3540,11 @@
/// is a shuffle we can handle in a single instruction, return it. Otherwise,
/// return the code it can be lowered into. Worst case, it can always be
/// lowered into a vperm.
-SDOperand PPCTargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op,
+SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
SelectionDAG &DAG) {
- SDOperand V1 = Op.getOperand(0);
- SDOperand V2 = Op.getOperand(1);
- SDOperand PermMask = Op.getOperand(2);
+ SDValue V1 = Op.getOperand(0);
+ SDValue V2 = Op.getOperand(1);
+ SDValue PermMask = Op.getOperand(2);
// Cases that are handled by instructions that take permute immediates
// (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
@@ -3642,7 +3642,7 @@
MVT EltVT = V1.getValueType().getVectorElementType();
unsigned BytesPerElement = EltVT.getSizeInBits()/8;
- SmallVector<SDOperand, 16> ResultMask;
+ SmallVector<SDValue, 16> ResultMask;
for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
unsigned SrcElt;
if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
@@ -3655,7 +3655,7 @@
MVT::i8));
}
- SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8,
+ SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8,
&ResultMask[0], ResultMask.size());
return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
}
@@ -3663,7 +3663,7 @@
/// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
/// altivec comparison. If it is, return true and fill in Opc/isDot with
/// information about the intrinsic.
-static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc,
+static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
bool &isDot) {
unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue();
CompareOpc = -1;
@@ -3705,25 +3705,25 @@
/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
/// lower, do it, otherwise return null.
-SDOperand PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op,
+SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
SelectionDAG &DAG) {
// If this is a lowered altivec predicate compare, CompareOpc is set to the
// opcode number of the comparison.
int CompareOpc;
bool isDot;
if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
- return SDOperand(); // Don't custom lower most intrinsics.
+ return SDValue(); // Don't custom lower most intrinsics.
// If this is a non-dot comparison, make the VCMP node and we are done.
if (!isDot) {
- SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
+ SDValue Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
Op.getOperand(1), Op.getOperand(2),
DAG.getConstant(CompareOpc, MVT::i32));
return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp);
}
// Create the PPCISD altivec 'dot' comparison node.
- SDOperand Ops[] = {
+ SDValue Ops[] = {
Op.getOperand(2), // LHS
Op.getOperand(3), // RHS
DAG.getConstant(CompareOpc, MVT::i32)
@@ -3731,11 +3731,11 @@
std::vector<MVT> VTs;
VTs.push_back(Op.getOperand(2).getValueType());
VTs.push_back(MVT::Flag);
- SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
+ SDValue CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
// Now that we have the comparison, emit a copy from the CR to a GPR.
// This is flagged to the above dot comparison.
- SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32,
+ SDValue Flags = DAG.getNode(PPCISD::MFCR, MVT::i32,
DAG.getRegister(PPC::CR6, MVT::i32),
CompNode.getValue(1));
@@ -3772,29 +3772,29 @@
return Flags;
}
-SDOperand PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op,
+SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
SelectionDAG &DAG) {
// Create a stack slot that is 16-byte aligned.
MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
int FrameIdx = FrameInfo->CreateStackObject(16, 16);
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
- SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
+ SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
// Store the input value into Value#0 of the stack slot.
- SDOperand Store = DAG.getStore(DAG.getEntryNode(),
+ SDValue Store = DAG.getStore(DAG.getEntryNode(),
Op.getOperand(0), FIdx, NULL, 0);
// Load it out.
return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0);
}
-SDOperand PPCTargetLowering::LowerMUL(SDOperand Op, SelectionDAG &DAG) {
+SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) {
if (Op.getValueType() == MVT::v4i32) {
- SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
+ SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
- SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG);
- SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt.
+ SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG);
+ SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt.
- SDOperand RHSSwap = // = vrlw RHS, 16
+ SDValue RHSSwap = // = vrlw RHS, 16
BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG);
// Shrinkify inputs to v8i16.
@@ -3804,36 +3804,36 @@
// Low parts multiplied together, generating 32-bit results (we ignore the
// top parts).
- SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
+ SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
LHS, RHS, DAG, MVT::v4i32);
- SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
+ SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
LHS, RHSSwap, Zero, DAG, MVT::v4i32);
// Shift the high parts up 16 bits.
HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG);
return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd);
} else if (Op.getValueType() == MVT::v8i16) {
- SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
+ SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
- SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG);
+ SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG);
return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
LHS, RHS, Zero, DAG);
} else if (Op.getValueType() == MVT::v16i8) {
- SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
+ SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
// Multiply the even 8-bit parts, producing 16-bit sums.
- SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
+ SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
LHS, RHS, DAG, MVT::v8i16);
EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts);
// Multiply the odd 8-bit parts, producing 16-bit sums.
- SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
+ SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
LHS, RHS, DAG, MVT::v8i16);
OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts);
// Merge the results together.
- SDOperand Ops[16];
+ SDValue Ops[16];
for (unsigned i = 0; i != 8; ++i) {
Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8);
Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8);
@@ -3848,7 +3848,7 @@
/// LowerOperation - Provide custom lowering hooks for some operations.
///
-SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
+SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
switch (Op.getOpcode()) {
default: assert(0 && "Wasn't expecting to be able to lower this!");
case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
@@ -3902,14 +3902,14 @@
case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
}
- return SDOperand();
+ return SDValue();
}
SDNode *PPCTargetLowering::ReplaceNodeResults(SDNode *N, SelectionDAG &DAG) {
switch (N->getOpcode()) {
default: assert(0 && "Wasn't expecting to be able to lower this!");
case ISD::FP_TO_SINT: {
- SDOperand Res = LowerFP_TO_SINT(SDOperand(N, 0), DAG);
+ SDValue Res = LowerFP_TO_SINT(SDValue(N, 0), DAG);
// Use MERGE_VALUES to drop the chain result value and get a node with one
// result. This requires turning off getMergeValues simplification, since
// otherwise it will give us Res back.
@@ -4127,7 +4127,7 @@
// Target Optimization Hooks
//===----------------------------------------------------------------------===//
-SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
+SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
DAGCombinerInfo &DCI) const {
TargetMachine &TM = getTargetMachine();
SelectionDAG &DAG = DCI.DAG;
@@ -4161,7 +4161,7 @@
// type must be i64.
if (N->getOperand(0).getValueType() == MVT::i64 &&
N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
- SDOperand Val = N->getOperand(0).getOperand(0);
+ SDValue Val = N->getOperand(0).getOperand(0);
if (Val.getValueType() == MVT::f32) {
Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
DCI.AddToWorklist(Val.Val);
@@ -4191,7 +4191,7 @@
N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
N->getOperand(1).getValueType() == MVT::i32 &&
N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
- SDOperand Val = N->getOperand(1).getOperand(0);
+ SDValue Val = N->getOperand(1).getOperand(0);
if (Val.getValueType() == MVT::f32) {
Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
DCI.AddToWorklist(Val.Val);
@@ -4210,7 +4210,7 @@
N->getOperand(1).Val->hasOneUse() &&
(N->getOperand(1).getValueType() == MVT::i32 ||
N->getOperand(1).getValueType() == MVT::i16)) {
- SDOperand BSwapOp = N->getOperand(1).getOperand(0);
+ SDValue BSwapOp = N->getOperand(1).getOperand(0);
// Do an any-extend to 32-bits if this is a half-word input.
if (BSwapOp.getValueType() == MVT::i16)
BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp);
@@ -4225,23 +4225,23 @@
if (ISD::isNON_EXTLoad(N->getOperand(0).Val) &&
N->getOperand(0).hasOneUse() &&
(N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
- SDOperand Load = N->getOperand(0);
+ SDValue Load = N->getOperand(0);
LoadSDNode *LD = cast<LoadSDNode>(Load);
// Create the byte-swapping load.
std::vector<MVT> VTs;
VTs.push_back(MVT::i32);
VTs.push_back(MVT::Other);
- SDOperand MO = DAG.getMemOperand(LD->getMemOperand());
- SDOperand Ops[] = {
+ SDValue MO = DAG.getMemOperand(LD->getMemOperand());
+ SDValue Ops[] = {
LD->getChain(), // Chain
LD->getBasePtr(), // Ptr
MO, // MemOperand
DAG.getValueType(N->getValueType(0)) // VT
};
- SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4);
+ SDValue BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4);
// If this is an i16 load, insert the truncate.
- SDOperand ResVal = BSLoad;
+ SDValue ResVal = BSLoad;
if (N->getValueType(0) == MVT::i16)
ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad);
@@ -4254,7 +4254,7 @@
DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1));
// Return N so it doesn't get rechecked!
- return SDOperand(N, 0);
+ return SDValue(N, 0);
}
break;
@@ -4295,7 +4295,7 @@
assert(UI != VCMPoNode->use_end() && "Didn't find user!");
SDNode *User = *UI;
for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
- if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) {
+ if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
FlagUser = User;
break;
}
@@ -4305,7 +4305,7 @@
// If the user is a MFCR instruction, we know this is safe. Otherwise we
// give up for right now.
if (FlagUser->getOpcode() == PPCISD::MFCR)
- return SDOperand(VCMPoNode, 0);
+ return SDValue(VCMPoNode, 0);
}
break;
}
@@ -4315,7 +4315,7 @@
// lowering is done pre-legalize, because the legalizer lowers the predicate
// compare down to code that is difficult to reassemble.
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
- SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3);
+ SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
int CompareOpc;
bool isDot;
@@ -4339,14 +4339,14 @@
// Create the PPCISD altivec 'dot' comparison node.
std::vector<MVT> VTs;
- SDOperand Ops[] = {
+ SDValue Ops[] = {
LHS.getOperand(2), // LHS of compare
LHS.getOperand(3), // RHS of compare
DAG.getConstant(CompareOpc, MVT::i32)
};
VTs.push_back(LHS.getOperand(2).getValueType());
VTs.push_back(MVT::Flag);
- SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
+ SDValue CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
// Unpack the result based on how the target uses it.
PPC::Predicate CompOpc;
@@ -4375,14 +4375,14 @@
}
}
- return SDOperand();
+ return SDValue();
}
//===----------------------------------------------------------------------===//
// Inline Assembly Support
//===----------------------------------------------------------------------===//
-void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
+void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
const APInt &Mask,
APInt &KnownZero,
APInt &KnownOne,
@@ -4469,10 +4469,10 @@
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
/// vector. If it is invalid, don't add anything to Ops.
-void PPCTargetLowering::LowerAsmOperandForConstraint(SDOperand Op, char Letter,
- std::vector<SDOperand>&Ops,
+void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, char Letter,
+ std::vector<SDValue>&Ops,
SelectionDAG &DAG) const {
- SDOperand Result(0,0);
+ SDValue Result(0,0);
switch (Letter) {
default: break;
case 'I':
@@ -4579,16 +4579,16 @@
return false;
}
-SDOperand PPCTargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) {
+SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
// Depths > 0 not supported yet!
if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
- return SDOperand();
+ return SDValue();
MachineFunction &MF = DAG.getMachineFunction();
PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
// Just load the return address off the stack.
- SDOperand RetAddrFI = getReturnAddrFrameIndex(DAG);
+ SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
// Make sure the function really does not optimize away the store of the RA
// to the stack.
@@ -4596,10 +4596,10 @@
return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
}
-SDOperand PPCTargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) {
+SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
// Depths > 0 not supported yet!
if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
- return SDOperand();
+ return SDValue();
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
bool isPPC64 = PtrVT == MVT::i64;
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h Sun Jul 27 16:46:04 2008
@@ -215,7 +215,7 @@
/// formed by using a vspltis[bhw] instruction of the specified element
/// size, return the constant being splatted. The ByteSize field indicates
/// the number of bytes of each element [124] -> [bhw].
- SDOperand get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
+ SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
}
class PPCTargetLowering : public TargetLowering {
@@ -236,49 +236,49 @@
virtual const char *getTargetNodeName(unsigned Opcode) const;
/// getSetCCResultType - Return the ISD::SETCC ValueType
- virtual MVT getSetCCResultType(const SDOperand &) const;
+ virtual MVT getSetCCResultType(const SDValue &) const;
/// getPreIndexedAddressParts - returns true by value, base pointer and
/// offset pointer and addressing mode by reference if the node's address
/// can be legally represented as pre-indexed load / store address.
- virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
- SDOperand &Offset,
+ virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
+ SDValue &Offset,
ISD::MemIndexedMode &AM,
SelectionDAG &DAG);
/// SelectAddressRegReg - Given the specified addressed, check to see if it
/// can be represented as an indexed [r+r] operation. Returns false if it
/// can be more efficiently represented with [r+imm].
- bool SelectAddressRegReg(SDOperand N, SDOperand &Base, SDOperand &Index,
+ bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
SelectionDAG &DAG);
/// SelectAddressRegImm - Returns true if the address N can be represented
/// by a base register plus a signed 16-bit displacement [r+imm], and if it
/// is not better represented as reg+reg.
- bool SelectAddressRegImm(SDOperand N, SDOperand &Disp, SDOperand &Base,
+ bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
SelectionDAG &DAG);
/// SelectAddressRegRegOnly - Given the specified addressed, force it to be
/// represented as an indexed [r+r] operation.
- bool SelectAddressRegRegOnly(SDOperand N, SDOperand &Base, SDOperand &Index,
+ bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
SelectionDAG &DAG);
/// SelectAddressRegImmShift - Returns true if the address N can be
/// represented by a base register plus a signed 14-bit displacement
/// [r+imm*4]. Suitable for use by STD and friends.
- bool SelectAddressRegImmShift(SDOperand N, SDOperand &Disp, SDOperand &Base,
+ bool SelectAddressRegImmShift(SDValue N, SDValue &Disp, SDValue &Base,
SelectionDAG &DAG);
/// LowerOperation - Provide custom lowering hooks for some operations.
///
- virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
+ virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
virtual SDNode *ReplaceNodeResults(SDNode *N, SelectionDAG &DAG);
- virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
+ virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
- virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
+ virtual void computeMaskedBitsForTargetNode(const SDValue Op,
const APInt &Mask,
APInt &KnownZero,
APInt &KnownOne,
@@ -300,9 +300,9 @@
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
/// vector. If it is invalid, don't add anything to Ops.
- virtual void LowerAsmOperandForConstraint(SDOperand Op,
+ virtual void LowerAsmOperandForConstraint(SDValue Op,
char ConstraintLetter,
- std::vector<SDOperand> &Ops,
+ std::vector<SDValue> &Ops,
SelectionDAG &DAG) const;
/// isLegalAddressingMode - Return true if the addressing mode represented
@@ -321,63 +321,63 @@
/// IsEligibleForTailCallOptimization - Check whether the call is eligible
/// for tail call optimization. Target which want to do tail call
/// optimization should implement this function.
- virtual bool IsEligibleForTailCallOptimization(SDOperand Call,
- SDOperand Ret,
+ virtual bool IsEligibleForTailCallOptimization(SDValue Call,
+ SDValue Ret,
SelectionDAG &DAG) const;
private:
- SDOperand getFramePointerFrameIndex(SelectionDAG & DAG) const;
- SDOperand getReturnAddrFrameIndex(SelectionDAG & DAG) const;
+ SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
+ SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
- SDOperand EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
+ SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
int SPDiff,
- SDOperand Chain,
- SDOperand &LROpOut,
- SDOperand &FPOpOut);
-
- SDOperand LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
+ SDValue Chain,
+ SDValue &LROpOut,
+ SDValue &FPOpOut);
+
+ SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
int VarArgsFrameIndex, int VarArgsStackOffset,
unsigned VarArgsNumGPR, unsigned VarArgsNumFPR,
const PPCSubtarget &Subtarget);
- SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG, int VarArgsFrameIndex,
+ SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG, int VarArgsFrameIndex,
int VarArgsStackOffset, unsigned VarArgsNumGPR,
unsigned VarArgsNumFPR, const PPCSubtarget &Subtarget);
- SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
+ SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG,
int &VarArgsFrameIndex,
int &VarArgsStackOffset,
unsigned &VarArgsNumGPR,
unsigned &VarArgsNumFPR,
const PPCSubtarget &Subtarget);
- SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG,
+ SDValue LowerCALL(SDValue Op, SelectionDAG &DAG,
const PPCSubtarget &Subtarget, TargetMachine &TM);
- SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG, TargetMachine &TM);
- SDOperand LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG,
+ SDValue LowerRET(SDValue Op, SelectionDAG &DAG, TargetMachine &TM);
+ SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
const PPCSubtarget &Subtarget);
- SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG,
+ SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
const PPCSubtarget &Subtarget);
- SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerAtomicLOAD_ADD(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerAtomicCMP_SWAP(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerAtomicSWAP(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerFP_ROUND_INREG(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG);
+ SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerAtomicLOAD_ADD(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerAtomicCMP_SWAP(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerAtomicSWAP(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerFP_ROUND_INREG(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerMUL(SDValue Op, SelectionDAG &DAG);
};
}
Modified: llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp Sun Jul 27 16:46:04 2008
@@ -40,12 +40,12 @@
Subtarget(TM.getSubtarget<SparcSubtarget>()) {
}
- SDNode *Select(SDOperand Op);
+ SDNode *Select(SDValue Op);
// Complex Pattern Selectors.
- bool SelectADDRrr(SDOperand Op, SDOperand N, SDOperand &R1, SDOperand &R2);
- bool SelectADDRri(SDOperand Op, SDOperand N, SDOperand &Base,
- SDOperand &Offset);
+ bool SelectADDRrr(SDValue Op, SDValue N, SDValue &R1, SDValue &R2);
+ bool SelectADDRri(SDValue Op, SDValue N, SDValue &Base,
+ SDValue &Offset);
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
@@ -70,8 +70,8 @@
DAG.RemoveDeadNodes();
}
-bool SparcDAGToDAGISel::SelectADDRri(SDOperand Op, SDOperand Addr,
- SDOperand &Base, SDOperand &Offset) {
+bool SparcDAGToDAGISel::SelectADDRri(SDValue Op, SDValue Addr,
+ SDValue &Base, SDValue &Offset) {
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
Offset = CurDAG->getTargetConstant(0, MVT::i32);
@@ -111,8 +111,8 @@
return true;
}
-bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Op, SDOperand Addr,
- SDOperand &R1, SDOperand &R2) {
+bool SparcDAGToDAGISel::SelectADDRrr(SDValue Op, SDValue Addr,
+ SDValue &R1, SDValue &R2) {
if (Addr.getOpcode() == ISD::FrameIndex) return false;
if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
Addr.getOpcode() == ISD::TargetGlobalAddress)
@@ -135,7 +135,7 @@
return true;
}
-SDNode *SparcDAGToDAGISel::Select(SDOperand Op) {
+SDNode *SparcDAGToDAGISel::Select(SDValue Op) {
SDNode *N = Op.Val;
if (N->isMachineOpcode())
return NULL; // Already selected.
@@ -145,20 +145,20 @@
case ISD::SDIV:
case ISD::UDIV: {
// FIXME: should use a custom expander to expose the SRA to the dag.
- SDOperand DivLHS = N->getOperand(0);
- SDOperand DivRHS = N->getOperand(1);
+ SDValue DivLHS = N->getOperand(0);
+ SDValue DivRHS = N->getOperand(1);
AddToISelQueue(DivLHS);
AddToISelQueue(DivRHS);
// Set the Y register to the high-part.
- SDOperand TopPart;
+ SDValue TopPart;
if (N->getOpcode() == ISD::SDIV) {
- TopPart = SDOperand(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS,
+ TopPart = SDValue(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS,
CurDAG->getTargetConstant(31, MVT::i32)), 0);
} else {
TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
}
- TopPart = SDOperand(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart,
+ TopPart = SDValue(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart,
CurDAG->getRegister(SP::G0, MVT::i32)), 0);
// FIXME: Handle div by immediate.
@@ -169,15 +169,15 @@
case ISD::MULHU:
case ISD::MULHS: {
// FIXME: Handle mul by immediate.
- SDOperand MulLHS = N->getOperand(0);
- SDOperand MulRHS = N->getOperand(1);
+ SDValue MulLHS = N->getOperand(0);
+ SDValue MulRHS = N->getOperand(1);
AddToISelQueue(MulLHS);
AddToISelQueue(MulRHS);
unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
MulLHS, MulRHS);
// The high part is in the Y register.
- return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1));
+ return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDValue(Mul, 1));
return NULL;
}
}
Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Sun Jul 27 16:46:04 2008
@@ -30,7 +30,7 @@
#include "SparcGenCallingConv.inc"
-static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
+static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) {
// CCValAssign - represent the assignment of the return value to locations.
SmallVector<CCValAssign, 16> RVLocs;
unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
@@ -50,8 +50,8 @@
DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
}
- SDOperand Chain = Op.getOperand(0);
- SDOperand Flag;
+ SDValue Chain = Op.getOperand(0);
+ SDValue Flag;
// Copy the result values into the output registers.
for (unsigned i = 0; i != RVLocs.size(); ++i) {
@@ -76,7 +76,7 @@
/// in FP registers for fastcc functions.
void
SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
- SmallVectorImpl<SDOperand> &ArgValues) {
+ SmallVectorImpl<SDValue> &ArgValues) {
MachineFunction &MF = DAG.getMachineFunction();
MachineRegisterInfo &RegInfo = MF.getRegInfo();
@@ -87,8 +87,8 @@
const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
unsigned ArgOffset = 68;
- SDOperand Root = DAG.getRoot();
- std::vector<SDOperand> OutChains;
+ SDValue Root = DAG.getRoot();
+ std::vector<SDValue> OutChains;
for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
MVT ObjectVT = getValueType(I->getType());
@@ -105,7 +105,7 @@
} else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
- SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
+ SDValue Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
if (ObjectVT != MVT::i32) {
unsigned AssertOp = ISD::AssertSext;
Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
@@ -115,8 +115,8 @@
ArgValues.push_back(Arg);
} else {
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
- SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
- SDOperand Load;
+ SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
+ SDValue Load;
if (ObjectVT == MVT::i32) {
Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
} else {
@@ -143,14 +143,14 @@
// FP value is passed in an integer register.
unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
- SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
+ SDValue Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg);
ArgValues.push_back(Arg);
} else {
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
- SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
- SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0);
+ SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
+ SDValue Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0);
ArgValues.push_back(Load);
}
ArgOffset += 4;
@@ -163,30 +163,30 @@
if (CurArgReg < ArgRegEnd) ++CurArgReg;
ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
} else {
- SDOperand HiVal;
+ SDValue HiVal;
if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
MF.getRegInfo().addLiveIn(*CurArgReg++, VRegHi);
HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
} else {
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
- SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
+ SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
}
- SDOperand LoVal;
+ SDValue LoVal;
if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
unsigned VRegLo = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
MF.getRegInfo().addLiveIn(*CurArgReg++, VRegLo);
LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
} else {
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
- SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
+ SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
}
// Compose the two halves together into an i64 unit.
- SDOperand WholeValue =
+ SDValue WholeValue =
DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
// If we want a double, do a bit convert.
@@ -208,10 +208,10 @@
for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
- SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
+ SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
- SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
+ SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
OutChains.push_back(DAG.getStore(DAG.getRoot(), Arg, FIPtr, NULL, 0));
ArgOffset += 4;
@@ -223,10 +223,10 @@
&OutChains[0], OutChains.size()));
}
-static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
+static SDValue LowerCALL(SDValue Op, SelectionDAG &DAG) {
unsigned CallingConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
- SDOperand Chain = Op.getOperand(0);
- SDOperand Callee = Op.getOperand(4);
+ SDValue Chain = Op.getOperand(0);
+ SDValue Callee = Op.getOperand(4);
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
#if 0
@@ -270,8 +270,8 @@
Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize));
- SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
- SmallVector<SDOperand, 8> MemOpChains;
+ SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
+ SmallVector<SDValue, 8> MemOpChains;
#if 0
// Walk the register/memloc assignments, inserting copies/loads.
@@ -279,7 +279,7 @@
CCValAssign &VA = ArgLocs[i];
// Arguments start after the 5 first operands of ISD::CALL
- SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
+ SDValue Arg = Op.getOperand(5+2*VA.getValNo());
// Promote the value if needed.
switch (VA.getLocInfo()) {
@@ -306,9 +306,9 @@
assert(VA.isMemLoc());
// Create a store off the stack pointer for this argument.
- SDOperand StackPtr = DAG.getRegister(SP::O6, MVT::i32);
+ SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
// FIXME: VERIFY THAT 68 IS RIGHT.
- SDOperand PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+68);
+ SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+68);
PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
}
@@ -320,9 +320,9 @@
unsigned ArgOffset = 68;
for (unsigned i = 5, e = Op.getNumOperands(); i != e; i += 2) {
- SDOperand Val = Op.getOperand(i);
+ SDValue Val = Op.getOperand(i);
MVT ObjectVT = Val.getValueType();
- SDOperand ValToStore(0, 0);
+ SDValue ValToStore(0, 0);
unsigned ObjSize;
switch (ObjectVT.getSimpleVT()) {
default: assert(0 && "Unhandled argument type!");
@@ -358,9 +358,9 @@
}
// Split the value into top and bottom part. Top part goes in a reg.
- SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
+ SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
DAG.getConstant(1, MVT::i32));
- SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
+ SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
DAG.getConstant(0, MVT::i32));
RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi));
@@ -375,8 +375,8 @@
}
if (ValToStore.Val) {
- SDOperand StackPtr = DAG.getRegister(SP::O6, MVT::i32);
- SDOperand PtrOff = DAG.getConstant(ArgOffset, MVT::i32);
+ SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
+ SDValue PtrOff = DAG.getConstant(ArgOffset, MVT::i32);
PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
MemOpChains.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0));
}
@@ -393,7 +393,7 @@
// chain and flag operands which copy the outgoing args into registers.
// The InFlag in necessary since all emited instructions must be
// stuck together.
- SDOperand InFlag;
+ SDValue InFlag;
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
unsigned Reg = RegsToPass[i].first;
// Remap I0->I7 -> O0->O7.
@@ -415,7 +415,7 @@
std::vector<MVT> NodeTys;
NodeTys.push_back(MVT::Other); // Returns a chain
NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
- SDOperand Ops[] = { Chain, Callee, InFlag };
+ SDValue Ops[] = { Chain, Callee, InFlag };
Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.Val ? 3 : 2);
InFlag = Chain.getValue(1);
@@ -429,7 +429,7 @@
CCState RVInfo(CallingConv, isVarArg, DAG.getTarget(), RVLocs);
RVInfo.AnalyzeCallResult(Op.Val, RetCC_Sparc32);
- SmallVector<SDOperand, 8> ResultVals;
+ SmallVector<SDValue, 8> ResultVals;
// Copy all of the result registers out of their specified physreg.
for (unsigned i = 0; i != RVLocs.size(); ++i) {
@@ -650,7 +650,7 @@
/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
/// be zero. Op is expected to be a target specific node. Used by DAG
/// combiner.
-void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
+void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
const APInt &Mask,
APInt &KnownZero,
APInt &KnownOne,
@@ -679,7 +679,7 @@
// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
-static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS,
+static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
ISD::CondCode CC, unsigned &SPCC) {
if (isa<ConstantSDNode>(RHS) && cast<ConstantSDNode>(RHS)->getValue() == 0 &&
CC == ISD::SETNE &&
@@ -691,50 +691,50 @@
isa<ConstantSDNode>(LHS.getOperand(1)) &&
cast<ConstantSDNode>(LHS.getOperand(0))->getValue() == 1 &&
cast<ConstantSDNode>(LHS.getOperand(1))->getValue() == 0) {
- SDOperand CMPCC = LHS.getOperand(3);
+ SDValue CMPCC = LHS.getOperand(3);
SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getValue();
LHS = CMPCC.getOperand(0);
RHS = CMPCC.getOperand(1);
}
}
-static SDOperand LowerGLOBALADDRESS(SDOperand Op, SelectionDAG &DAG) {
+static SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) {
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
- SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
- SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA);
- SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA);
+ SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
+ SDValue Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA);
+ SDValue Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA);
return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
}
-static SDOperand LowerCONSTANTPOOL(SDOperand Op, SelectionDAG &DAG) {
+static SDValue LowerCONSTANTPOOL(SDValue Op, SelectionDAG &DAG) {
ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
Constant *C = N->getConstVal();
- SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
- SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP);
- SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP);
+ SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
+ SDValue Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP);
+ SDValue Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP);
return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
}
-static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
+static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
// Convert the fp value to integer in an FP register.
assert(Op.getValueType() == MVT::i32);
Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
}
-static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
+static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
assert(Op.getOperand(0).getValueType() == MVT::i32);
- SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
+ SDValue Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
// Convert the int value to FP in an FP register.
return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp);
}
-static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG) {
- SDOperand Chain = Op.getOperand(0);
+static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
+ SDValue Chain = Op.getOperand(0);
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
- SDOperand LHS = Op.getOperand(2);
- SDOperand RHS = Op.getOperand(3);
- SDOperand Dest = Op.getOperand(4);
+ SDValue LHS = Op.getOperand(2);
+ SDValue RHS = Op.getOperand(3);
+ SDValue Dest = Op.getOperand(4);
unsigned Opc, SPCC = ~0U;
// If this is a br_cc of a "setcc", and if the setcc got lowered into
@@ -742,12 +742,12 @@
LookThroughSetCC(LHS, RHS, CC, SPCC);
// Get the condition flag.
- SDOperand CompareFlag;
+ SDValue CompareFlag;
if (LHS.getValueType() == MVT::i32) {
std::vector<MVT> VTs;
VTs.push_back(MVT::i32);
VTs.push_back(MVT::Flag);
- SDOperand Ops[2] = { LHS, RHS };
+ SDValue Ops[2] = { LHS, RHS };
CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
Opc = SPISD::BRICC;
@@ -760,24 +760,24 @@
DAG.getConstant(SPCC, MVT::i32), CompareFlag);
}
-static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
- SDOperand LHS = Op.getOperand(0);
- SDOperand RHS = Op.getOperand(1);
+static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
+ SDValue LHS = Op.getOperand(0);
+ SDValue RHS = Op.getOperand(1);
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
- SDOperand TrueVal = Op.getOperand(2);
- SDOperand FalseVal = Op.getOperand(3);
+ SDValue TrueVal = Op.getOperand(2);
+ SDValue FalseVal = Op.getOperand(3);
unsigned Opc, SPCC = ~0U;
// If this is a select_cc of a "setcc", and if the setcc got lowered into
// an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
LookThroughSetCC(LHS, RHS, CC, SPCC);
- SDOperand CompareFlag;
+ SDValue CompareFlag;
if (LHS.getValueType() == MVT::i32) {
std::vector<MVT> VTs;
VTs.push_back(LHS.getValueType()); // subcc returns a value
VTs.push_back(MVT::Flag);
- SDOperand Ops[2] = { LHS, RHS };
+ SDValue Ops[2] = { LHS, RHS };
CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
Opc = SPISD::SELECT_ICC;
if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
@@ -790,11 +790,11 @@
DAG.getConstant(SPCC, MVT::i32), CompareFlag);
}
-static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
+static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
SparcTargetLowering &TLI) {
// vastart just stores the address of the VarArgsFrameIndex slot into the
// memory location argument.
- SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
+ SDValue Offset = DAG.getNode(ISD::ADD, MVT::i32,
DAG.getRegister(SP::I6, MVT::i32),
DAG.getConstant(TLI.getVarArgsFrameOffset(),
MVT::i32));
@@ -802,15 +802,15 @@
return DAG.getStore(Op.getOperand(0), Offset, Op.getOperand(1), SV, 0);
}
-static SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG) {
+static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
SDNode *Node = Op.Val;
MVT VT = Node->getValueType(0);
- SDOperand InChain = Node->getOperand(0);
- SDOperand VAListPtr = Node->getOperand(1);
+ SDValue InChain = Node->getOperand(0);
+ SDValue VAListPtr = Node->getOperand(1);
const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
- SDOperand VAList = DAG.getLoad(MVT::i32, InChain, VAListPtr, SV, 0);
+ SDValue VAList = DAG.getLoad(MVT::i32, InChain, VAListPtr, SV, 0);
// Increment the pointer, VAList, to the next vaarg
- SDOperand NextPtr = DAG.getNode(ISD::ADD, MVT::i32, VAList,
+ SDValue NextPtr = DAG.getNode(ISD::ADD, MVT::i32, VAList,
DAG.getConstant(VT.getSizeInBits()/8,
MVT::i32));
// Store the incremented VAList to the legalized pointer
@@ -822,41 +822,41 @@
return DAG.getLoad(VT, InChain, VAList, NULL, 0);
// Otherwise, load it as i64, then do a bitconvert.
- SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0);
+ SDValue V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0);
// Bit-Convert the value to f64.
- SDOperand Ops[2] = {
+ SDValue Ops[2] = {
DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V),
V.getValue(1)
};
return DAG.getMergeValues(Ops, 2);
}
-static SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG) {
- SDOperand Chain = Op.getOperand(0); // Legalize the chain.
- SDOperand Size = Op.getOperand(1); // Legalize the size.
+static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
+ SDValue Chain = Op.getOperand(0); // Legalize the chain.
+ SDValue Size = Op.getOperand(1); // Legalize the size.
unsigned SPReg = SP::O6;
- SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32);
- SDOperand NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size); // Value
+ SDValue SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32);
+ SDValue NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size); // Value
Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP); // Output chain
// The resultant pointer is actually 16 words from the bottom of the stack,
// to provide a register spill area.
- SDOperand NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP,
+ SDValue NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP,
DAG.getConstant(96, MVT::i32));
- SDOperand Ops[2] = { NewVal, Chain };
+ SDValue Ops[2] = { NewVal, Chain };
return DAG.getMergeValues(Ops, 2);
}
-SDOperand SparcTargetLowering::
-LowerOperation(SDOperand Op, SelectionDAG &DAG) {
+SDValue SparcTargetLowering::
+LowerOperation(SDValue Op, SelectionDAG &DAG) {
switch (Op.getOpcode()) {
default: assert(0 && "Should not custom lower this!");
// Frame & Return address. Currently unimplemented
- case ISD::RETURNADDR: return SDOperand();
- case ISD::FRAMEADDR: return SDOperand();
+ case ISD::RETURNADDR: return SDValue();
+ case ISD::FRAMEADDR: return SDValue();
case ISD::GlobalTLSAddress:
assert(0 && "TLS not implemented for Sparc.");
case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG);
Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.h?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcISelLowering.h (original)
+++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.h Sun Jul 27 16:46:04 2008
@@ -43,14 +43,14 @@
int VarArgsFrameOffset; // Frame offset to start of varargs area.
public:
SparcTargetLowering(TargetMachine &TM);
- virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
+ virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
int getVarArgsFrameOffset() const { return VarArgsFrameOffset; }
/// computeMaskedBitsForTargetNode - Determine which of the bits specified
/// in Mask are known to be either zero or one and return them in the
/// KnownZero/KnownOne bitsets.
- virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
+ virtual void computeMaskedBitsForTargetNode(const SDValue Op,
const APInt &Mask,
APInt &KnownZero,
APInt &KnownOne,
@@ -58,7 +58,7 @@
unsigned Depth = 0) const;
virtual void LowerArguments(Function &F, SelectionDAG &DAG,
- SmallVectorImpl<SDOperand> &ArgValues);
+ SmallVectorImpl<SDValue> &ArgValues);
virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *MBB);
Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Sun Jul 27 16:46:04 2008
@@ -50,7 +50,7 @@
namespace {
/// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
- /// SDOperand's instead of register numbers for the leaves of the matched
+ /// SDValue's instead of register numbers for the leaves of the matched
/// tree.
struct X86ISelAddressMode {
enum {
@@ -59,13 +59,13 @@
} BaseType;
struct { // This is really a union, discriminated by BaseType!
- SDOperand Reg;
+ SDValue Reg;
int FrameIndex;
} Base;
bool isRIPRel; // RIP as base?
unsigned Scale;
- SDOperand IndexReg;
+ SDValue IndexReg;
unsigned Disp;
GlobalValue *GV;
Constant *CP;
@@ -143,38 +143,38 @@
#include "X86GenDAGISel.inc"
private:
- SDNode *Select(SDOperand N);
+ SDNode *Select(SDValue N);
- bool MatchAddress(SDOperand N, X86ISelAddressMode &AM,
+ bool MatchAddress(SDValue N, X86ISelAddressMode &AM,
bool isRoot = true, unsigned Depth = 0);
- bool MatchAddressBase(SDOperand N, X86ISelAddressMode &AM,
+ bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM,
bool isRoot, unsigned Depth);
- bool SelectAddr(SDOperand Op, SDOperand N, SDOperand &Base,
- SDOperand &Scale, SDOperand &Index, SDOperand &Disp);
- bool SelectLEAAddr(SDOperand Op, SDOperand N, SDOperand &Base,
- SDOperand &Scale, SDOperand &Index, SDOperand &Disp);
- bool SelectScalarSSELoad(SDOperand Op, SDOperand Pred,
- SDOperand N, SDOperand &Base, SDOperand &Scale,
- SDOperand &Index, SDOperand &Disp,
- SDOperand &InChain, SDOperand &OutChain);
- bool TryFoldLoad(SDOperand P, SDOperand N,
- SDOperand &Base, SDOperand &Scale,
- SDOperand &Index, SDOperand &Disp);
+ bool SelectAddr(SDValue Op, SDValue N, SDValue &Base,
+ SDValue &Scale, SDValue &Index, SDValue &Disp);
+ bool SelectLEAAddr(SDValue Op, SDValue N, SDValue &Base,
+ SDValue &Scale, SDValue &Index, SDValue &Disp);
+ bool SelectScalarSSELoad(SDValue Op, SDValue Pred,
+ SDValue N, SDValue &Base, SDValue &Scale,
+ SDValue &Index, SDValue &Disp,
+ SDValue &InChain, SDValue &OutChain);
+ bool TryFoldLoad(SDValue P, SDValue N,
+ SDValue &Base, SDValue &Scale,
+ SDValue &Index, SDValue &Disp);
void PreprocessForRMW(SelectionDAG &DAG);
void PreprocessForFPConvert(SelectionDAG &DAG);
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
- virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
+ virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
char ConstraintCode,
- std::vector<SDOperand> &OutOps,
+ std::vector<SDValue> &OutOps,
SelectionDAG &DAG);
void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI);
- inline void getAddressOperands(X86ISelAddressMode &AM, SDOperand &Base,
- SDOperand &Scale, SDOperand &Index,
- SDOperand &Disp) {
+ inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base,
+ SDValue &Scale, SDValue &Index,
+ SDValue &Disp) {
Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy()) :
AM.Base.Reg;
@@ -196,19 +196,19 @@
/// getI8Imm - Return a target constant with the specified value, of type
/// i8.
- inline SDOperand getI8Imm(unsigned Imm) {
+ inline SDValue getI8Imm(unsigned Imm) {
return CurDAG->getTargetConstant(Imm, MVT::i8);
}
/// getI16Imm - Return a target constant with the specified value, of type
/// i16.
- inline SDOperand getI16Imm(unsigned Imm) {
+ inline SDValue getI16Imm(unsigned Imm) {
return CurDAG->getTargetConstant(Imm, MVT::i16);
}
/// getI32Imm - Return a target constant with the specified value, of type
/// i32.
- inline SDOperand getI32Imm(unsigned Imm) {
+ inline SDValue getI32Imm(unsigned Imm) {
return CurDAG->getTargetConstant(Imm, MVT::i32);
}
@@ -218,7 +218,7 @@
/// getTruncate - return an SDNode that implements a subreg based truncate
/// of the specified operand to the the specified value type.
- SDNode *getTruncate(SDOperand N0, MVT VT);
+ SDNode *getTruncate(SDValue N0, MVT VT);
#ifndef NDEBUG
unsigned Indent;
@@ -233,7 +233,7 @@
for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
SDNode *User = *I;
for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
- SDOperand Op = User->getOperand(i);
+ SDValue Op = User->getOperand(i);
if (Op.Val == N && Op.ResNo == FlagResNo)
return User;
}
@@ -352,9 +352,9 @@
/// MoveBelowTokenFactor - Replace TokenFactor operand with load's chain operand
/// and move load below the TokenFactor. Replace store's chain operand with
/// load's chain result.
-static void MoveBelowTokenFactor(SelectionDAG &DAG, SDOperand Load,
- SDOperand Store, SDOperand TF) {
- std::vector<SDOperand> Ops;
+static void MoveBelowTokenFactor(SelectionDAG &DAG, SDValue Load,
+ SDValue Store, SDValue TF) {
+ std::vector<SDValue> Ops;
for (unsigned i = 0, e = TF.Val->getNumOperands(); i != e; ++i)
if (Load.Val == TF.Val->getOperand(i).Val)
Ops.push_back(Load.Val->getOperand(0));
@@ -368,8 +368,8 @@
/// isRMWLoad - Return true if N is a load that's part of RMW sub-DAG.
///
-static bool isRMWLoad(SDOperand N, SDOperand Chain, SDOperand Address,
- SDOperand &Load) {
+static bool isRMWLoad(SDValue N, SDValue Chain, SDValue Address,
+ SDValue &Load) {
if (N.getOpcode() == ISD::BIT_CONVERT)
N = N.getOperand(0);
@@ -437,19 +437,19 @@
E = DAG.allnodes_end(); I != E; ++I) {
if (!ISD::isNON_TRUNCStore(I))
continue;
- SDOperand Chain = I->getOperand(0);
+ SDValue Chain = I->getOperand(0);
if (Chain.Val->getOpcode() != ISD::TokenFactor)
continue;
- SDOperand N1 = I->getOperand(1);
- SDOperand N2 = I->getOperand(2);
+ SDValue N1 = I->getOperand(1);
+ SDValue N2 = I->getOperand(2);
if ((N1.getValueType().isFloatingPoint() &&
!N1.getValueType().isVector()) ||
!N1.hasOneUse())
continue;
bool RModW = false;
- SDOperand Load;
+ SDValue Load;
unsigned Opcode = N1.Val->getOpcode();
switch (Opcode) {
case ISD::ADD:
@@ -460,8 +460,8 @@
case ISD::ADDC:
case ISD::ADDE:
case ISD::VECTOR_SHUFFLE: {
- SDOperand N10 = N1.getOperand(0);
- SDOperand N11 = N1.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
RModW = isRMWLoad(N10, Chain, N2, Load);
if (!RModW)
RModW = isRMWLoad(N11, Chain, N2, Load);
@@ -477,14 +477,14 @@
case ISD::SUBE:
case X86ISD::SHLD:
case X86ISD::SHRD: {
- SDOperand N10 = N1.getOperand(0);
+ SDValue N10 = N1.getOperand(0);
RModW = isRMWLoad(N10, Chain, N2, Load);
break;
}
}
if (RModW) {
- MoveBelowTokenFactor(DAG, Load, SDOperand(I, 0), Chain);
+ MoveBelowTokenFactor(DAG, Load, SDValue(I, 0), Chain);
++NumLoadMoved;
}
}
@@ -533,12 +533,12 @@
else
MemVT = SrcIsSSE ? SrcVT : DstVT;
- SDOperand MemTmp = DAG.CreateStackTemporary(MemVT);
+ SDValue MemTmp = DAG.CreateStackTemporary(MemVT);
// FIXME: optimize the case where the src/dest is a load or store?
- SDOperand Store = DAG.getTruncStore(DAG.getEntryNode(), N->getOperand(0),
+ SDValue Store = DAG.getTruncStore(DAG.getEntryNode(), N->getOperand(0),
MemTmp, NULL, 0, MemVT);
- SDOperand Result = DAG.getExtLoad(ISD::EXTLOAD, DstVT, Store, MemTmp,
+ SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, DstVT, Store, MemTmp,
NULL, 0, MemVT);
// We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
@@ -546,7 +546,7 @@
// anything below the conversion could be folded into other existing nodes.
// To avoid invalidating 'I', back it up to the convert node.
--I;
- DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result);
+ DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
// Now that we did that, the node is dead. Increment the iterator to the
// next node to process, then delete N.
@@ -674,7 +674,7 @@
/// MatchAddress - Add the specified node to the specified addressing mode,
/// returning true if it cannot be done. This just pattern matches for the
/// addressing mode.
-bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
+bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM,
bool isRoot, unsigned Depth) {
// Limit recursion.
if (Depth > 5)
@@ -719,7 +719,7 @@
// been picked, we can't fit the result available in the register in the
// addressing mode. Duplicate GlobalAddress or ConstantPool as displacement.
if (!AlreadySelected || (AM.Base.Reg.Val && AM.IndexReg.Val)) {
- SDOperand N0 = N.getOperand(0);
+ SDValue N0 = N.getOperand(0);
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
GlobalValue *GV = G->getGlobal();
AM.GV = GV;
@@ -765,7 +765,7 @@
unsigned Val = CN->getValue();
if (Val == 1 || Val == 2 || Val == 3) {
AM.Scale = 1 << Val;
- SDOperand ShVal = N.Val->getOperand(0);
+ SDValue ShVal = N.Val->getOperand(0);
// Okay, we know that we have a scale by now. However, if the scaled
// value is an add of something and a constant, we can fold the
@@ -804,8 +804,8 @@
if (CN->getValue() == 3 || CN->getValue() == 5 || CN->getValue() == 9) {
AM.Scale = unsigned(CN->getValue())-1;
- SDOperand MulVal = N.Val->getOperand(0);
- SDOperand Reg;
+ SDValue MulVal = N.Val->getOperand(0);
+ SDValue Reg;
// Okay, we know that we have a scale by now. However, if the scaled
// value is an add of something and a constant, we can fold the
@@ -869,7 +869,7 @@
// Handle "(x << C1) & C2" as "(X & (C2>>C1)) << C1" if safe and if this
// allows us to fold the shift into this addressing mode.
if (AlreadySelected) break;
- SDOperand Shift = N.getOperand(0);
+ SDValue Shift = N.getOperand(0);
if (Shift.getOpcode() != ISD::SHL) break;
// Scale must not be used already.
@@ -894,9 +894,9 @@
break;
// Get the new AND mask, this folds to a constant.
- SDOperand NewANDMask = CurDAG->getNode(ISD::SRL, N.getValueType(),
- SDOperand(C2, 0), SDOperand(C1, 0));
- SDOperand NewAND = CurDAG->getNode(ISD::AND, N.getValueType(),
+ SDValue NewANDMask = CurDAG->getNode(ISD::SRL, N.getValueType(),
+ SDValue(C2, 0), SDValue(C1, 0));
+ SDValue NewAND = CurDAG->getNode(ISD::AND, N.getValueType(),
Shift.getOperand(0), NewANDMask);
NewANDMask.Val->setNodeId(Shift.Val->getNodeId());
NewAND.Val->setNodeId(N.Val->getNodeId());
@@ -912,7 +912,7 @@
/// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
/// specified addressing mode without any further recursion.
-bool X86DAGToDAGISel::MatchAddressBase(SDOperand N, X86ISelAddressMode &AM,
+bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM,
bool isRoot, unsigned Depth) {
// Is the base register already occupied?
if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base.Reg.Val) {
@@ -936,9 +936,9 @@
/// SelectAddr - returns true if it is able pattern match an addressing mode.
/// It returns the operands which make up the maximal addressing mode it can
/// match by reference.
-bool X86DAGToDAGISel::SelectAddr(SDOperand Op, SDOperand N, SDOperand &Base,
- SDOperand &Scale, SDOperand &Index,
- SDOperand &Disp) {
+bool X86DAGToDAGISel::SelectAddr(SDValue Op, SDValue N, SDValue &Base,
+ SDValue &Scale, SDValue &Index,
+ SDValue &Disp) {
X86ISelAddressMode AM;
if (MatchAddress(N, AM))
return false;
@@ -958,7 +958,7 @@
/// isZeroNode - Returns true if Elt is a constant zero or a floating point
/// constant +0.0.
-static inline bool isZeroNode(SDOperand Elt) {
+static inline bool isZeroNode(SDValue Elt) {
return ((isa<ConstantSDNode>(Elt) &&
cast<ConstantSDNode>(Elt)->getValue() == 0) ||
(isa<ConstantFPSDNode>(Elt) &&
@@ -969,11 +969,11 @@
/// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
/// match a load whose top elements are either undef or zeros. The load flavor
/// is derived from the type of N, which is either v4f32 or v2f64.
-bool X86DAGToDAGISel::SelectScalarSSELoad(SDOperand Op, SDOperand Pred,
- SDOperand N, SDOperand &Base,
- SDOperand &Scale, SDOperand &Index,
- SDOperand &Disp, SDOperand &InChain,
- SDOperand &OutChain) {
+bool X86DAGToDAGISel::SelectScalarSSELoad(SDValue Op, SDValue Pred,
+ SDValue N, SDValue &Base,
+ SDValue &Scale, SDValue &Index,
+ SDValue &Disp, SDValue &InChain,
+ SDValue &OutChain) {
if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
InChain = N.getOperand(0).getValue(1);
if (ISD::isNON_EXTLoad(InChain.Val) &&
@@ -1001,7 +1001,7 @@
if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp))
return false;
OutChain = LD->getChain();
- InChain = SDOperand(LD, 1);
+ InChain = SDValue(LD, 1);
return true;
}
return false;
@@ -1010,9 +1010,9 @@
/// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
/// mode it matches can be cost effectively emitted as an LEA instruction.
-bool X86DAGToDAGISel::SelectLEAAddr(SDOperand Op, SDOperand N,
- SDOperand &Base, SDOperand &Scale,
- SDOperand &Index, SDOperand &Disp) {
+bool X86DAGToDAGISel::SelectLEAAddr(SDValue Op, SDValue N,
+ SDValue &Base, SDValue &Scale,
+ SDValue &Index, SDValue &Disp) {
X86ISelAddressMode AM;
if (MatchAddress(N, AM))
return false;
@@ -1061,9 +1061,9 @@
return false;
}
-bool X86DAGToDAGISel::TryFoldLoad(SDOperand P, SDOperand N,
- SDOperand &Base, SDOperand &Scale,
- SDOperand &Index, SDOperand &Disp) {
+bool X86DAGToDAGISel::TryFoldLoad(SDValue P, SDValue N,
+ SDValue &Base, SDValue &Scale,
+ SDValue &Index, SDValue &Disp) {
if (ISD::isNON_EXTLoad(N.Val) &&
N.hasOneUse() &&
CanBeFoldedBy(N.Val, P.Val, P.Val))
@@ -1111,8 +1111,8 @@
return FindCallStartFromCall(Node->getOperand(0).Val);
}
-SDNode *X86DAGToDAGISel::getTruncate(SDOperand N0, MVT VT) {
- SDOperand SRIdx;
+SDNode *X86DAGToDAGISel::getTruncate(SDValue N0, MVT VT) {
+ SDValue SRIdx;
switch (VT.getSimpleVT()) {
default: assert(0 && "Unknown truncate!");
case MVT::i8:
@@ -1130,7 +1130,7 @@
Opc = X86::MOV32to32_;
break;
}
- N0 = SDOperand(CurDAG->getTargetNode(Opc, N0VT, MVT::Flag, N0), 0);
+ N0 = SDValue(CurDAG->getTargetNode(Opc, N0VT, MVT::Flag, N0), 0);
return CurDAG->getTargetNode(X86::EXTRACT_SUBREG,
VT, N0, SRIdx, N0.getValue(1));
}
@@ -1146,7 +1146,7 @@
}
-SDNode *X86DAGToDAGISel::Select(SDOperand N) {
+SDNode *X86DAGToDAGISel::Select(SDValue N) {
SDNode *Node = N.Val;
MVT NVT = Node->getValueType(0);
unsigned Opc, MOpc;
@@ -1183,13 +1183,13 @@
if (TM.getCodeModel() != CodeModel::Small)
break;
MVT PtrVT = TLI.getPointerTy();
- SDOperand N0 = N.getOperand(0);
- SDOperand N1 = N.getOperand(1);
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
if (N.Val->getValueType(0) == PtrVT &&
N0.getOpcode() == X86ISD::Wrapper &&
N1.getOpcode() == ISD::Constant) {
unsigned Offset = (unsigned)cast<ConstantSDNode>(N1)->getValue();
- SDOperand C(0, 0);
+ SDValue C(0, 0);
// TODO: handle ExternalSymbolSDNode.
if (GlobalAddressSDNode *G =
dyn_cast<GlobalAddressSDNode>(N0.getOperand(0))) {
@@ -1204,7 +1204,7 @@
if (C.Val) {
if (Subtarget->is64Bit()) {
- SDOperand Ops[] = { CurDAG->getRegister(0, PtrVT), getI8Imm(1),
+ SDValue Ops[] = { CurDAG->getRegister(0, PtrVT), getI8Imm(1),
CurDAG->getRegister(0, PtrVT), C };
return CurDAG->SelectNodeTo(N.Val, X86::LEA64r, MVT::i64, Ops, 4);
} else
@@ -1218,8 +1218,8 @@
case ISD::SMUL_LOHI:
case ISD::UMUL_LOHI: {
- SDOperand N0 = Node->getOperand(0);
- SDOperand N1 = Node->getOperand(1);
+ SDValue N0 = Node->getOperand(0);
+ SDValue N1 = Node->getOperand(1);
bool isSigned = Opcode == ISD::SMUL_LOHI;
if (!isSigned)
@@ -1248,7 +1248,7 @@
case MVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break;
}
- SDOperand Tmp0, Tmp1, Tmp2, Tmp3;
+ SDValue Tmp0, Tmp1, Tmp2, Tmp3;
bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
// multiplty is commmutative
if (!foldedLoad) {
@@ -1258,8 +1258,8 @@
}
AddToISelQueue(N0);
- SDOperand InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), LoReg,
- N0, SDOperand()).getValue(1);
+ SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), LoReg,
+ N0, SDValue()).getValue(1);
if (foldedLoad) {
AddToISelQueue(N1.getOperand(0));
@@ -1267,21 +1267,21 @@
AddToISelQueue(Tmp1);
AddToISelQueue(Tmp2);
AddToISelQueue(Tmp3);
- SDOperand Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag };
+ SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag };
SDNode *CNode =
CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Ops, 6);
- InFlag = SDOperand(CNode, 1);
+ InFlag = SDValue(CNode, 1);
// Update the chain.
- ReplaceUses(N1.getValue(1), SDOperand(CNode, 0));
+ ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
} else {
AddToISelQueue(N1);
InFlag =
- SDOperand(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
+ SDValue(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
}
// Copy the low half of the result, if it is needed.
if (!N.getValue(0).use_empty()) {
- SDOperand Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
+ SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
LoReg, NVT, InFlag);
InFlag = Result.getValue(2);
ReplaceUses(N.getValue(0), Result);
@@ -1293,18 +1293,18 @@
}
// Copy the high half of the result, if it is needed.
if (!N.getValue(1).use_empty()) {
- SDOperand Result;
+ SDValue Result;
if (HiReg == X86::AH && Subtarget->is64Bit()) {
// Prevent use of AH in a REX instruction by referencing AX instead.
// Shift it down 8 bits.
Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
X86::AX, MVT::i16, InFlag);
InFlag = Result.getValue(2);
- Result = SDOperand(CurDAG->getTargetNode(X86::SHR16ri, MVT::i16, Result,
+ Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, MVT::i16, Result,
CurDAG->getTargetConstant(8, MVT::i8)), 0);
// Then truncate it down to i8.
- SDOperand SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
- Result = SDOperand(CurDAG->getTargetNode(X86::EXTRACT_SUBREG,
+ SDValue SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
+ Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG,
MVT::i8, Result, SRIdx), 0);
} else {
Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
@@ -1328,8 +1328,8 @@
case ISD::SDIVREM:
case ISD::UDIVREM: {
- SDOperand N0 = Node->getOperand(0);
- SDOperand N1 = Node->getOperand(1);
+ SDValue N0 = Node->getOperand(0);
+ SDValue N1 = Node->getOperand(1);
bool isSigned = Opcode == ISD::SDIVREM;
if (!isSigned)
@@ -1375,46 +1375,46 @@
break;
}
- SDOperand Tmp0, Tmp1, Tmp2, Tmp3;
+ SDValue Tmp0, Tmp1, Tmp2, Tmp3;
bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
- SDOperand InFlag;
+ SDValue InFlag;
if (NVT == MVT::i8 && !isSigned) {
// Special case for div8, just use a move with zero extension to AX to
// clear the upper 8 bits (AH).
- SDOperand Tmp0, Tmp1, Tmp2, Tmp3, Move, Chain;
+ SDValue Tmp0, Tmp1, Tmp2, Tmp3, Move, Chain;
if (TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3)) {
- SDOperand Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N0.getOperand(0) };
+ SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N0.getOperand(0) };
AddToISelQueue(N0.getOperand(0));
AddToISelQueue(Tmp0);
AddToISelQueue(Tmp1);
AddToISelQueue(Tmp2);
AddToISelQueue(Tmp3);
Move =
- SDOperand(CurDAG->getTargetNode(X86::MOVZX16rm8, MVT::i16, MVT::Other,
+ SDValue(CurDAG->getTargetNode(X86::MOVZX16rm8, MVT::i16, MVT::Other,
Ops, 5), 0);
Chain = Move.getValue(1);
ReplaceUses(N0.getValue(1), Chain);
} else {
AddToISelQueue(N0);
Move =
- SDOperand(CurDAG->getTargetNode(X86::MOVZX16rr8, MVT::i16, N0), 0);
+ SDValue(CurDAG->getTargetNode(X86::MOVZX16rr8, MVT::i16, N0), 0);
Chain = CurDAG->getEntryNode();
}
- Chain = CurDAG->getCopyToReg(Chain, X86::AX, Move, SDOperand());
+ Chain = CurDAG->getCopyToReg(Chain, X86::AX, Move, SDValue());
InFlag = Chain.getValue(1);
} else {
AddToISelQueue(N0);
InFlag =
CurDAG->getCopyToReg(CurDAG->getEntryNode(),
- LoReg, N0, SDOperand()).getValue(1);
+ LoReg, N0, SDValue()).getValue(1);
if (isSigned) {
// Sign extend the low part into the high part.
InFlag =
- SDOperand(CurDAG->getTargetNode(SExtOpcode, MVT::Flag, InFlag), 0);
+ SDValue(CurDAG->getTargetNode(SExtOpcode, MVT::Flag, InFlag), 0);
} else {
// Zero out the high part, effectively zero extending the input.
- SDOperand ClrNode = SDOperand(CurDAG->getTargetNode(ClrOpcode, NVT), 0);
+ SDValue ClrNode = SDValue(CurDAG->getTargetNode(ClrOpcode, NVT), 0);
InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), HiReg,
ClrNode, InFlag).getValue(1);
}
@@ -1426,21 +1426,21 @@
AddToISelQueue(Tmp1);
AddToISelQueue(Tmp2);
AddToISelQueue(Tmp3);
- SDOperand Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag };
+ SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag };
SDNode *CNode =
CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Ops, 6);
- InFlag = SDOperand(CNode, 1);
+ InFlag = SDValue(CNode, 1);
// Update the chain.
- ReplaceUses(N1.getValue(1), SDOperand(CNode, 0));
+ ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
} else {
AddToISelQueue(N1);
InFlag =
- SDOperand(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
+ SDValue(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
}
// Copy the division (low) result, if it is needed.
if (!N.getValue(0).use_empty()) {
- SDOperand Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
+ SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
LoReg, NVT, InFlag);
InFlag = Result.getValue(2);
ReplaceUses(N.getValue(0), Result);
@@ -1452,18 +1452,18 @@
}
// Copy the remainder (high) result, if it is needed.
if (!N.getValue(1).use_empty()) {
- SDOperand Result;
+ SDValue Result;
if (HiReg == X86::AH && Subtarget->is64Bit()) {
// Prevent use of AH in a REX instruction by referencing AX instead.
// Shift it down 8 bits.
Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
X86::AX, MVT::i16, InFlag);
InFlag = Result.getValue(2);
- Result = SDOperand(CurDAG->getTargetNode(X86::SHR16ri, MVT::i16, Result,
+ Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, MVT::i16, Result,
CurDAG->getTargetConstant(8, MVT::i8)), 0);
// Then truncate it down to i8.
- SDOperand SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
- Result = SDOperand(CurDAG->getTargetNode(X86::EXTRACT_SUBREG,
+ SDValue SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
+ Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG,
MVT::i8, Result, SRIdx), 0);
} else {
Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
@@ -1490,7 +1490,7 @@
if (NVT == MVT::i8)
break;
- SDOperand N0 = Node->getOperand(0);
+ SDValue N0 = Node->getOperand(0);
// Get the subregsiter index for the type to extend.
MVT N0VT = N0.getValueType();
unsigned Idx = (N0VT == MVT::i32) ? X86::SUBREG_32BIT :
@@ -1503,9 +1503,9 @@
// If we have an index, generate an insert_subreg into undef.
AddToISelQueue(N0);
- SDOperand Undef =
- SDOperand(CurDAG->getTargetNode(X86::IMPLICIT_DEF, NVT), 0);
- SDOperand SRIdx = CurDAG->getTargetConstant(Idx, MVT::i32);
+ SDValue Undef =
+ SDValue(CurDAG->getTargetNode(X86::IMPLICIT_DEF, NVT), 0);
+ SDValue SRIdx = CurDAG->getTargetConstant(Idx, MVT::i32);
SDNode *ResNode = CurDAG->getTargetNode(X86::INSERT_SUBREG,
NVT, Undef, N0, SRIdx);
@@ -1519,11 +1519,11 @@
}
case ISD::SIGN_EXTEND_INREG: {
- SDOperand N0 = Node->getOperand(0);
+ SDValue N0 = Node->getOperand(0);
AddToISelQueue(N0);
MVT SVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
- SDOperand TruncOp = SDOperand(getTruncate(N0, SVT), 0);
+ SDValue TruncOp = SDValue(getTruncate(N0, SVT), 0);
unsigned Opc = 0;
switch (NVT.getSimpleVT()) {
default: assert(0 && "Unknown sign_extend_inreg!");
@@ -1564,7 +1564,7 @@
}
case ISD::TRUNCATE: {
- SDOperand Input = Node->getOperand(0);
+ SDValue Input = Node->getOperand(0);
AddToISelQueue(Node->getOperand(0));
SDNode *ResNode = getTruncate(Input, NVT);
@@ -1581,9 +1581,9 @@
case ISD::DECLARE: {
// Handle DECLARE nodes here because the second operand may have been
// wrapped in X86ISD::Wrapper.
- SDOperand Chain = Node->getOperand(0);
- SDOperand N1 = Node->getOperand(1);
- SDOperand N2 = Node->getOperand(2);
+ SDValue Chain = Node->getOperand(0);
+ SDValue N1 = Node->getOperand(1);
+ SDValue N2 = Node->getOperand(2);
if (!isa<FrameIndexSDNode>(N1))
break;
int FI = cast<FrameIndexSDNode>(N1)->getIndex();
@@ -1594,10 +1594,10 @@
isa<GlobalAddressSDNode>(N2.getOperand(0))) {
GlobalValue *GV =
cast<GlobalAddressSDNode>(N2.getOperand(0))->getGlobal();
- SDOperand Tmp1 = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
- SDOperand Tmp2 = CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy());
+ SDValue Tmp1 = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
+ SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy());
AddToISelQueue(Chain);
- SDOperand Ops[] = { Tmp1, Tmp2, Chain };
+ SDValue Ops[] = { Tmp1, Tmp2, Chain };
return CurDAG->getTargetNode(TargetInstrInfo::DECLARE,
MVT::Other, Ops, 3);
}
@@ -1621,9 +1621,9 @@
}
bool X86DAGToDAGISel::
-SelectInlineAsmMemoryOperand(const SDOperand &Op, char ConstraintCode,
- std::vector<SDOperand> &OutOps, SelectionDAG &DAG){
- SDOperand Op0, Op1, Op2, Op3;
+SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
+ std::vector<SDValue> &OutOps, SelectionDAG &DAG){
+ SDValue Op0, Op1, Op2, Op3;
switch (ConstraintCode) {
case 'o': // offsetable ??
case 'v': // not offsetable ??
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sun Jul 27 16:46:04 2008
@@ -41,7 +41,7 @@
using namespace llvm;
// Forward declarations.
-static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG);
+static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG);
X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
: TargetLowering(TM) {
@@ -755,7 +755,7 @@
}
-MVT X86TargetLowering::getSetCCResultType(const SDOperand &) const {
+MVT X86TargetLowering::getSetCCResultType(const SDValue &) const {
return MVT::i8;
}
@@ -818,7 +818,7 @@
/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
/// jumptable.
-SDOperand X86TargetLowering::getPICJumpTableRelocBase(SDOperand Table,
+SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
SelectionDAG &DAG) const {
if (usesGlobalOffsetTable())
return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy());
@@ -834,7 +834,7 @@
#include "X86GenCallingConv.inc"
/// LowerRET - Lower an ISD::RET node.
-SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
+SDValue X86TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
SmallVector<CCValAssign, 16> RVLocs;
@@ -850,14 +850,14 @@
if (RVLocs[i].isRegLoc())
DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
}
- SDOperand Chain = Op.getOperand(0);
+ SDValue Chain = Op.getOperand(0);
// Handle tail call return.
Chain = GetPossiblePreceedingTailCall(Chain, X86ISD::TAILCALL);
if (Chain.getOpcode() == X86ISD::TAILCALL) {
- SDOperand TailCall = Chain;
- SDOperand TargetAddress = TailCall.getOperand(1);
- SDOperand StackAdjustment = TailCall.getOperand(2);
+ SDValue TailCall = Chain;
+ SDValue TargetAddress = TailCall.getOperand(1);
+ SDValue StackAdjustment = TailCall.getOperand(2);
assert(((TargetAddress.getOpcode() == ISD::Register &&
(cast<RegisterSDNode>(TargetAddress)->getReg() == X86::ECX ||
cast<RegisterSDNode>(TargetAddress)->getReg() == X86::R9)) ||
@@ -867,7 +867,7 @@
assert(StackAdjustment.getOpcode() == ISD::Constant &&
"Expecting a const value");
- SmallVector<SDOperand,8> Operands;
+ SmallVector<SDValue,8> Operands;
Operands.push_back(Chain.getOperand(0));
Operands.push_back(TargetAddress);
Operands.push_back(StackAdjustment);
@@ -881,9 +881,9 @@
}
// Regular return.
- SDOperand Flag;
+ SDValue Flag;
- SmallVector<SDOperand, 6> RetOps;
+ SmallVector<SDValue, 6> RetOps;
RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
// Operand #1 = Bytes To Pop
RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
@@ -892,7 +892,7 @@
for (unsigned i = 0; i != RVLocs.size(); ++i) {
CCValAssign &VA = RVLocs[i];
assert(VA.isRegLoc() && "Can only return in registers!");
- SDOperand ValToCopy = Op.getOperand(i*2+1);
+ SDValue ValToCopy = Op.getOperand(i*2+1);
// Returns in ST0/ST1 are handled specially: these are pushed as operands to
// the RET instruction and handled by the FP Stackifier.
@@ -924,7 +924,7 @@
Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
FuncInfo->setSRetReturnReg(Reg);
}
- SDOperand Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy());
+ SDValue Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy());
Chain = DAG.getCopyToReg(Chain, X86::RAX, Val, Flag);
Flag = Chain.getValue(1);
@@ -946,7 +946,7 @@
/// being lowered. The returns a SDNode with the same number of values as the
/// ISD::CALL.
SDNode *X86TargetLowering::
-LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
+LowerCallResult(SDValue Chain, SDValue InFlag, SDNode *TheCall,
unsigned CallingConv, SelectionDAG &DAG) {
// Assign locations to each value returned by this call.
@@ -955,7 +955,7 @@
CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
- SmallVector<SDOperand, 8> ResultVals;
+ SmallVector<SDValue, 8> ResultVals;
// Copy all of the result registers out of their specified physreg.
for (unsigned i = 0; i != RVLocs.size(); ++i) {
@@ -971,7 +971,7 @@
Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
CopyVT, InFlag).getValue(1);
- SDOperand Val = Chain.getValue(0);
+ SDValue Val = Chain.getValue(0);
InFlag = Chain.getValue(2);
if (CopyVT != RVLocs[i].getValVT()) {
@@ -1015,7 +1015,7 @@
/// CallIsStructReturn - Determines whether a CALL node uses struct return
/// semantics.
-static bool CallIsStructReturn(SDOperand Op) {
+static bool CallIsStructReturn(SDValue Op) {
unsigned NumOps = (Op.getNumOperands() - 5) / 2;
if (!NumOps)
return false;
@@ -1025,7 +1025,7 @@
/// ArgsAreStructReturn - Determines whether a FORMAL_ARGUMENTS node uses struct
/// return semantics.
-static bool ArgsAreStructReturn(SDOperand Op) {
+static bool ArgsAreStructReturn(SDValue Op) {
unsigned NumArgs = Op.Val->getNumValues() - 1;
if (!NumArgs)
return false;
@@ -1036,7 +1036,7 @@
/// IsCalleePop - Determines whether a CALL or FORMAL_ARGUMENTS node requires
/// the callee to pop its own arguments. Callee pop is necessary to support tail
/// calls.
-bool X86TargetLowering::IsCalleePop(SDOperand Op) {
+bool X86TargetLowering::IsCalleePop(SDValue Op) {
bool IsVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
if (IsVarArg)
return false;
@@ -1055,7 +1055,7 @@
/// CCAssignFnForNode - Selects the correct CCAssignFn for a CALL or
/// FORMAL_ARGUMENTS node.
-CCAssignFn *X86TargetLowering::CCAssignFnForNode(SDOperand Op) const {
+CCAssignFn *X86TargetLowering::CCAssignFnForNode(SDValue Op) const {
unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
if (Subtarget->is64Bit()) {
@@ -1080,7 +1080,7 @@
/// NameDecorationForFORMAL_ARGUMENTS - Selects the appropriate decoration to
/// apply to a MachineFunction containing a given FORMAL_ARGUMENTS node.
NameDecorationStyle
-X86TargetLowering::NameDecorationForFORMAL_ARGUMENTS(SDOperand Op) {
+X86TargetLowering::NameDecorationForFORMAL_ARGUMENTS(SDValue Op) {
unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
if (CC == CallingConv::X86_FastCall)
return FastCall;
@@ -1111,19 +1111,19 @@
/// by "Src" to address "Dst" with size and alignment information specified by
/// the specific parameter attribute. The copy will be passed as a byval
/// function parameter.
-static SDOperand
-CreateCopyOfByValArgument(SDOperand Src, SDOperand Dst, SDOperand Chain,
+static SDValue
+CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
ISD::ArgFlagsTy Flags, SelectionDAG &DAG) {
- SDOperand SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
+ SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
return DAG.getMemcpy(Chain, Dst, Src, SizeNode, Flags.getByValAlign(),
/*AlwaysInline=*/true, NULL, 0, NULL, 0);
}
-SDOperand X86TargetLowering::LowerMemArgument(SDOperand Op, SelectionDAG &DAG,
+SDValue X86TargetLowering::LowerMemArgument(SDValue Op, SelectionDAG &DAG,
const CCValAssign &VA,
MachineFrameInfo *MFI,
unsigned CC,
- SDOperand Root, unsigned i) {
+ SDValue Root, unsigned i) {
// Create the nodes corresponding to a load from this parameter slot.
ISD::ArgFlagsTy Flags =
cast<ARG_FLAGSSDNode>(Op.getOperand(3 + i))->getArgFlags();
@@ -1136,15 +1136,15 @@
// could be overwritten by lowering of arguments in case of a tail call.
int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
VA.getLocMemOffset(), isImmutable);
- SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
+ SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
if (Flags.isByVal())
return FIN;
return DAG.getLoad(VA.getValVT(), Root, FIN,
PseudoSourceValue::getFixedStack(FI), 0);
}
-SDOperand
-X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
+SDValue
+X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
MachineFunction &MF = DAG.getMachineFunction();
X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
@@ -1158,7 +1158,7 @@
FuncInfo->setDecorationStyle(NameDecorationForFORMAL_ARGUMENTS(Op));
MachineFrameInfo *MFI = MF.getFrameInfo();
- SDOperand Root = Op.getOperand(0);
+ SDValue Root = Op.getOperand(0);
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
unsigned CC = MF.getFunction()->getCallingConv();
bool Is64Bit = Subtarget->is64Bit();
@@ -1172,7 +1172,7 @@
CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
CCInfo.AnalyzeFormalArguments(Op.Val, CCAssignFnForNode(Op));
- SmallVector<SDOperand, 8> ArgValues;
+ SmallVector<SDValue, 8> ArgValues;
unsigned LastVal = ~0U;
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
CCValAssign &VA = ArgLocs[i];
@@ -1215,7 +1215,7 @@
}
unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
- SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
+ SDValue ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
// If this is an 8 or 16-bit value, it is really passed promoted to 32
// bits. Insert an assert[sz]ext to capture this, then truncate to the
@@ -1259,7 +1259,7 @@
Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
FuncInfo->setSRetReturnReg(Reg);
}
- SDOperand Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]);
+ SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]);
Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root);
}
@@ -1316,15 +1316,15 @@
TotalNumXMMRegs * 16, 16);
// Store the integer parameter registers.
- SmallVector<SDOperand, 8> MemOps;
- SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
- SDOperand FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
+ SmallVector<SDValue, 8> MemOps;
+ SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
+ SDValue FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
DAG.getIntPtrConstant(VarArgsGPOffset));
for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
X86::GR64RegisterClass);
- SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
- SDOperand Store =
+ SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
+ SDValue Store =
DAG.getStore(Val.getValue(1), Val, FIN,
PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
MemOps.push_back(Store);
@@ -1338,8 +1338,8 @@
for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
X86::VR128RegisterClass);
- SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
- SDOperand Store =
+ SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
+ SDValue Store =
DAG.getStore(Val.getValue(1), Val, FIN,
PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
MemOps.push_back(Store);
@@ -1387,14 +1387,14 @@
ArgValues.size()).getValue(Op.ResNo);
}
-SDOperand
-X86TargetLowering::LowerMemOpCallTo(SDOperand Op, SelectionDAG &DAG,
- const SDOperand &StackPtr,
+SDValue
+X86TargetLowering::LowerMemOpCallTo(SDValue Op, SelectionDAG &DAG,
+ const SDValue &StackPtr,
const CCValAssign &VA,
- SDOperand Chain,
- SDOperand Arg) {
+ SDValue Chain,
+ SDValue Arg) {
unsigned LocMemOffset = VA.getLocMemOffset();
- SDOperand PtrOff = DAG.getIntPtrConstant(LocMemOffset);
+ SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
ISD::ArgFlagsTy Flags =
cast<ARG_FLAGSSDNode>(Op.getOperand(6+2*VA.getValNo()))->getArgFlags();
@@ -1407,10 +1407,10 @@
/// EmitTailCallLoadRetAddr - Emit a load of return adress if tail call
/// optimization is performed and it is required.
-SDOperand
+SDValue
X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
- SDOperand &OutRetAddr,
- SDOperand Chain,
+ SDValue &OutRetAddr,
+ SDValue Chain,
bool IsTailCall,
bool Is64Bit,
int FPDiff) {
@@ -1421,14 +1421,14 @@
OutRetAddr = getReturnAddressFrameIndex(DAG);
// Load the "old" Return address.
OutRetAddr = DAG.getLoad(VT, Chain,OutRetAddr, NULL, 0);
- return SDOperand(OutRetAddr.Val, 1);
+ return SDValue(OutRetAddr.Val, 1);
}
/// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
/// optimization is performed and it is required (FPDiff!=0).
-static SDOperand
+static SDValue
EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
- SDOperand Chain, SDOperand RetAddrFrIdx,
+ SDValue Chain, SDValue RetAddrFrIdx,
bool Is64Bit, int FPDiff) {
// Store the return address to the appropriate stack slot.
if (!FPDiff) return Chain;
@@ -1437,20 +1437,20 @@
int NewReturnAddrFI =
MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize);
MVT VT = Is64Bit ? MVT::i64 : MVT::i32;
- SDOperand NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
+ SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
Chain = DAG.getStore(Chain, RetAddrFrIdx, NewRetAddrFrIdx,
PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0);
return Chain;
}
-SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
+SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
MachineFunction &MF = DAG.getMachineFunction();
- SDOperand Chain = Op.getOperand(0);
+ SDValue Chain = Op.getOperand(0);
unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
bool IsTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0
&& CC == CallingConv::Fast && PerformTailCallOpt;
- SDOperand Callee = Op.getOperand(4);
+ SDValue Callee = Op.getOperand(4);
bool Is64Bit = Subtarget->is64Bit();
bool IsStructRet = CallIsStructReturn(Op);
@@ -1489,20 +1489,20 @@
Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes));
- SDOperand RetAddrFrIdx;
+ SDValue RetAddrFrIdx;
// Load return adress for tail calls.
Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, IsTailCall, Is64Bit,
FPDiff);
- SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
- SmallVector<SDOperand, 8> MemOpChains;
- SDOperand StackPtr;
+ SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
+ SmallVector<SDValue, 8> MemOpChains;
+ SDValue StackPtr;
// Walk the register/memloc assignments, inserting copies/loads. In the case
// of tail call optimization arguments are handle later.
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
CCValAssign &VA = ArgLocs[i];
- SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
+ SDValue Arg = Op.getOperand(5+2*VA.getValNo());
bool isByVal = cast<ARG_FLAGSSDNode>(Op.getOperand(6+2*VA.getValNo()))->
getArgFlags().isByVal();
@@ -1565,7 +1565,7 @@
// Build a sequence of copy-to-reg nodes chained together with token chain
// and flag operands which copy the outgoing args into registers.
- SDOperand InFlag;
+ SDValue InFlag;
// Tail call byval lowering might overwrite argument registers so in case of
// tail call optimization the copies to registers are lowered later.
if (!IsTailCall)
@@ -1624,17 +1624,17 @@
// For tail calls lower the arguments to the 'real' stack slot.
if (IsTailCall) {
- SmallVector<SDOperand, 8> MemOpChains2;
- SDOperand FIN;
+ SmallVector<SDValue, 8> MemOpChains2;
+ SDValue FIN;
int FI = 0;
// Do not flag preceeding copytoreg stuff together with the following stuff.
- InFlag = SDOperand();
+ InFlag = SDValue();
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
CCValAssign &VA = ArgLocs[i];
if (!VA.isRegLoc()) {
assert(VA.isMemLoc());
- SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
- SDOperand FlagsOp = Op.getOperand(6+2*VA.getValNo());
+ SDValue Arg = Op.getOperand(5+2*VA.getValNo());
+ SDValue FlagsOp = Op.getOperand(6+2*VA.getValNo());
ISD::ArgFlagsTy Flags =
cast<ARG_FLAGSSDNode>(FlagsOp)->getArgFlags();
// Create frame index.
@@ -1645,7 +1645,7 @@
if (Flags.isByVal()) {
// Copy relative to framepointer.
- SDOperand Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
+ SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
if (StackPtr.Val == 0)
StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
Source = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, Source);
@@ -1671,7 +1671,7 @@
InFlag);
InFlag = Chain.getValue(1);
}
- InFlag =SDOperand();
+ InFlag =SDValue();
// Store the return address to the appropriate stack slot.
Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
@@ -1701,7 +1701,7 @@
// Returns a chain & a flag for retval copy to use.
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
- SmallVector<SDOperand, 8> Ops;
+ SmallVector<SDValue, 8> Ops;
if (IsTailCall) {
Ops.push_back(Chain);
@@ -1748,7 +1748,7 @@
Chain = DAG.getNode(X86ISD::TAILCALL,
Op.Val->getVTList(), &Ops[0], Ops.size());
- return SDOperand(Chain.Val, Op.ResNo);
+ return SDValue(Chain.Val, Op.ResNo);
}
Chain = DAG.getNode(X86ISD::CALL, NodeTys, &Ops[0], Ops.size());
@@ -1775,7 +1775,7 @@
// Handle result values, copying them out of physregs into vregs that we
// return.
- return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
+ return SDValue(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
}
@@ -1839,8 +1839,8 @@
/// following the call is a return. A function is eligible if caller/callee
/// calling conventions match, currently only fastcc supports tail calls, and
/// the function CALL is immediatly followed by a RET.
-bool X86TargetLowering::IsEligibleForTailCallOptimization(SDOperand Call,
- SDOperand Ret,
+bool X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Call,
+ SDValue Ret,
SelectionDAG& DAG) const {
if (!PerformTailCallOpt)
return false;
@@ -1850,7 +1850,7 @@
unsigned CallerCC = MF.getFunction()->getCallingConv();
unsigned CalleeCC = cast<ConstantSDNode>(Call.getOperand(1))->getValue();
if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
- SDOperand Callee = Call.getOperand(4);
+ SDValue Callee = Call.getOperand(4);
// On x86/32Bit PIC/GOT tail calls are supported.
if (getTargetMachine().getRelocationModel() != Reloc::PIC_ ||
!Subtarget->isPICStyleGOT()|| !Subtarget->is64Bit())
@@ -1872,7 +1872,7 @@
//===----------------------------------------------------------------------===//
-SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
+SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
MachineFunction &MF = DAG.getMachineFunction();
X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
int ReturnAddrIndex = FuncInfo->getRAIndex();
@@ -1897,7 +1897,7 @@
/// translation. X86CC is the translated CondCode. LHS/RHS are modified as
/// needed.
static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
- unsigned &X86CC, SDOperand &LHS, SDOperand &RHS,
+ unsigned &X86CC, SDValue &LHS, SDValue &RHS,
SelectionDAG &DAG) {
X86CC = X86::COND_INVALID;
if (!isFP) {
@@ -1989,7 +1989,7 @@
/// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return
/// true if Op is undef or if its value falls within the specified range (L, H].
-static bool isUndefOrInRange(SDOperand Op, unsigned Low, unsigned Hi) {
+static bool isUndefOrInRange(SDValue Op, unsigned Low, unsigned Hi) {
if (Op.getOpcode() == ISD::UNDEF)
return true;
@@ -1999,7 +1999,7 @@
/// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return
/// true if Op is undef or if its value equal to the specified value.
-static bool isUndefOrEqual(SDOperand Op, unsigned Val) {
+static bool isUndefOrEqual(SDValue Op, unsigned Val) {
if (Op.getOpcode() == ISD::UNDEF)
return true;
return cast<ConstantSDNode>(Op)->getValue() == Val;
@@ -2015,7 +2015,7 @@
// Check if the value doesn't reference the second vector.
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
- SDOperand Arg = N->getOperand(i);
+ SDValue Arg = N->getOperand(i);
if (Arg.getOpcode() == ISD::UNDEF) continue;
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
if (cast<ConstantSDNode>(Arg)->getValue() >= e)
@@ -2035,7 +2035,7 @@
// Lower quadword copied in order.
for (unsigned i = 0; i != 4; ++i) {
- SDOperand Arg = N->getOperand(i);
+ SDValue Arg = N->getOperand(i);
if (Arg.getOpcode() == ISD::UNDEF) continue;
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
if (cast<ConstantSDNode>(Arg)->getValue() != i)
@@ -2044,7 +2044,7 @@
// Upper quadword shuffled.
for (unsigned i = 4; i != 8; ++i) {
- SDOperand Arg = N->getOperand(i);
+ SDValue Arg = N->getOperand(i);
if (Arg.getOpcode() == ISD::UNDEF) continue;
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
@@ -2185,7 +2185,7 @@
return false;
for (unsigned i = 0; i < NumElems/2; ++i) {
- SDOperand Arg = N->getOperand(i + NumElems/2);
+ SDValue Arg = N->getOperand(i + NumElems/2);
if (!isUndefOrEqual(Arg, i + NumElems))
return false;
}
@@ -2201,8 +2201,8 @@
return false;
for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
- SDOperand BitI = Elts[i];
- SDOperand BitI1 = Elts[i+1];
+ SDValue BitI = Elts[i];
+ SDValue BitI1 = Elts[i+1];
if (!isUndefOrEqual(BitI, j))
return false;
if (V2IsSplat) {
@@ -2230,8 +2230,8 @@
return false;
for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
- SDOperand BitI = Elts[i];
- SDOperand BitI1 = Elts[i+1];
+ SDValue BitI = Elts[i];
+ SDValue BitI1 = Elts[i+1];
if (!isUndefOrEqual(BitI, j + NumElts/2))
return false;
if (V2IsSplat) {
@@ -2262,8 +2262,8 @@
return false;
for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
- SDOperand BitI = N->getOperand(i);
- SDOperand BitI1 = N->getOperand(i+1);
+ SDValue BitI = N->getOperand(i);
+ SDValue BitI1 = N->getOperand(i+1);
if (!isUndefOrEqual(BitI, j))
return false;
@@ -2285,8 +2285,8 @@
return false;
for (unsigned i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
- SDOperand BitI = N->getOperand(i);
- SDOperand BitI1 = N->getOperand(i + 1);
+ SDValue BitI = N->getOperand(i);
+ SDValue BitI1 = N->getOperand(i + 1);
if (!isUndefOrEqual(BitI, j))
return false;
@@ -2333,7 +2333,7 @@
return false;
for (unsigned i = 1; i < NumOps; ++i) {
- SDOperand Arg = Ops[i];
+ SDValue Arg = Ops[i];
if (!(isUndefOrEqual(Arg, i+NumOps) ||
(V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) ||
(V2IsSplat && isUndefOrEqual(Arg, NumOps))))
@@ -2360,7 +2360,7 @@
// Expect 1, 1, 3, 3
for (unsigned i = 0; i < 2; ++i) {
- SDOperand Arg = N->getOperand(i);
+ SDValue Arg = N->getOperand(i);
if (Arg.getOpcode() == ISD::UNDEF) continue;
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
@@ -2369,7 +2369,7 @@
bool HasHi = false;
for (unsigned i = 2; i < 4; ++i) {
- SDOperand Arg = N->getOperand(i);
+ SDValue Arg = N->getOperand(i);
if (Arg.getOpcode() == ISD::UNDEF) continue;
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
@@ -2391,7 +2391,7 @@
// Expect 0, 0, 2, 2
for (unsigned i = 0; i < 2; ++i) {
- SDOperand Arg = N->getOperand(i);
+ SDValue Arg = N->getOperand(i);
if (Arg.getOpcode() == ISD::UNDEF) continue;
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
@@ -2400,7 +2400,7 @@
bool HasHi = false;
for (unsigned i = 2; i < 4; ++i) {
- SDOperand Arg = N->getOperand(i);
+ SDValue Arg = N->getOperand(i);
if (Arg.getOpcode() == ISD::UNDEF) continue;
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
@@ -2430,10 +2430,10 @@
// This is a splat operation if each element of the permute is the same, and
// if the value doesn't reference the second vector.
unsigned NumElems = N->getNumOperands();
- SDOperand ElementBase;
+ SDValue ElementBase;
unsigned i = 0;
for (; i != NumElems; ++i) {
- SDOperand Elt = N->getOperand(i);
+ SDValue Elt = N->getOperand(i);
if (isa<ConstantSDNode>(Elt)) {
ElementBase = Elt;
break;
@@ -2444,7 +2444,7 @@
return false;
for (; i != NumElems; ++i) {
- SDOperand Arg = N->getOperand(i);
+ SDValue Arg = N->getOperand(i);
if (Arg.getOpcode() == ISD::UNDEF) continue;
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
if (Arg != ElementBase) return false;
@@ -2485,7 +2485,7 @@
unsigned Mask = 0;
for (unsigned i = 0; i < NumOperands; ++i) {
unsigned Val = 0;
- SDOperand Arg = N->getOperand(NumOperands-i-1);
+ SDValue Arg = N->getOperand(NumOperands-i-1);
if (Arg.getOpcode() != ISD::UNDEF)
Val = cast<ConstantSDNode>(Arg)->getValue();
if (Val >= NumOperands) Val -= NumOperands;
@@ -2505,7 +2505,7 @@
// 8 nodes, but we only care about the last 4.
for (unsigned i = 7; i >= 4; --i) {
unsigned Val = 0;
- SDOperand Arg = N->getOperand(i);
+ SDValue Arg = N->getOperand(i);
if (Arg.getOpcode() != ISD::UNDEF)
Val = cast<ConstantSDNode>(Arg)->getValue();
Mask |= (Val - 4);
@@ -2524,7 +2524,7 @@
// 8 nodes, but we only care about the first 4.
for (int i = 3; i >= 0; --i) {
unsigned Val = 0;
- SDOperand Arg = N->getOperand(i);
+ SDValue Arg = N->getOperand(i);
if (Arg.getOpcode() != ISD::UNDEF)
Val = cast<ConstantSDNode>(Arg)->getValue();
Mask |= Val;
@@ -2546,7 +2546,7 @@
// Lower quadword shuffled.
for (unsigned i = 0; i != 4; ++i) {
- SDOperand Arg = N->getOperand(i);
+ SDValue Arg = N->getOperand(i);
if (Arg.getOpcode() == ISD::UNDEF) continue;
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
@@ -2556,7 +2556,7 @@
// Upper quadword shuffled.
for (unsigned i = 4; i != 8; ++i) {
- SDOperand Arg = N->getOperand(i);
+ SDValue Arg = N->getOperand(i);
if (Arg.getOpcode() == ISD::UNDEF) continue;
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
@@ -2569,17 +2569,17 @@
/// CommuteVectorShuffle - Swap vector_shuffle operands as well as
/// values in ther permute mask.
-static SDOperand CommuteVectorShuffle(SDOperand Op, SDOperand &V1,
- SDOperand &V2, SDOperand &Mask,
+static SDValue CommuteVectorShuffle(SDValue Op, SDValue &V1,
+ SDValue &V2, SDValue &Mask,
SelectionDAG &DAG) {
MVT VT = Op.getValueType();
MVT MaskVT = Mask.getValueType();
MVT EltVT = MaskVT.getVectorElementType();
unsigned NumElems = Mask.getNumOperands();
- SmallVector<SDOperand, 8> MaskVec;
+ SmallVector<SDValue, 8> MaskVec;
for (unsigned i = 0; i != NumElems; ++i) {
- SDOperand Arg = Mask.getOperand(i);
+ SDValue Arg = Mask.getOperand(i);
if (Arg.getOpcode() == ISD::UNDEF) {
MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
continue;
@@ -2600,13 +2600,13 @@
/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
/// the two vector operands have swapped position.
static
-SDOperand CommuteVectorShuffleMask(SDOperand Mask, SelectionDAG &DAG) {
+SDValue CommuteVectorShuffleMask(SDValue Mask, SelectionDAG &DAG) {
MVT MaskVT = Mask.getValueType();
MVT EltVT = MaskVT.getVectorElementType();
unsigned NumElems = Mask.getNumOperands();
- SmallVector<SDOperand, 8> MaskVec;
+ SmallVector<SDValue, 8> MaskVec;
for (unsigned i = 0; i != NumElems; ++i) {
- SDOperand Arg = Mask.getOperand(i);
+ SDValue Arg = Mask.getOperand(i);
if (Arg.getOpcode() == ISD::UNDEF) {
MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
continue;
@@ -2685,7 +2685,7 @@
if (N->getOpcode() != ISD::BUILD_VECTOR)
return false;
- SDOperand SplatValue = N->getOperand(0);
+ SDValue SplatValue = N->getOperand(0);
for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
if (N->getOperand(i) != SplatValue)
return false;
@@ -2698,12 +2698,12 @@
if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
return false;
- SDOperand V1 = N->getOperand(0);
- SDOperand V2 = N->getOperand(1);
- SDOperand Mask = N->getOperand(2);
+ SDValue V1 = N->getOperand(0);
+ SDValue V2 = N->getOperand(1);
+ SDValue Mask = N->getOperand(2);
unsigned NumElems = Mask.getNumOperands();
for (unsigned i = 0; i != NumElems; ++i) {
- SDOperand Arg = Mask.getOperand(i);
+ SDValue Arg = Mask.getOperand(i);
if (Arg.getOpcode() != ISD::UNDEF) {
unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
if (Val < NumElems && V1.getOpcode() != ISD::UNDEF)
@@ -2717,7 +2717,7 @@
/// isZeroNode - Returns true if Elt is a constant zero or a floating point
/// constant +0.0.
-static inline bool isZeroNode(SDOperand Elt) {
+static inline bool isZeroNode(SDValue Elt) {
return ((isa<ConstantSDNode>(Elt) &&
cast<ConstantSDNode>(Elt)->getValue() == 0) ||
(isa<ConstantFPSDNode>(Elt) &&
@@ -2730,12 +2730,12 @@
if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
return false;
- SDOperand V1 = N->getOperand(0);
- SDOperand V2 = N->getOperand(1);
- SDOperand Mask = N->getOperand(2);
+ SDValue V1 = N->getOperand(0);
+ SDValue V2 = N->getOperand(1);
+ SDValue Mask = N->getOperand(2);
unsigned NumElems = Mask.getNumOperands();
for (unsigned i = 0; i != NumElems; ++i) {
- SDOperand Arg = Mask.getOperand(i);
+ SDValue Arg = Mask.getOperand(i);
if (Arg.getOpcode() == ISD::UNDEF)
continue;
@@ -2761,20 +2761,20 @@
/// getZeroVector - Returns a vector of specified type with all zero elements.
///
-static SDOperand getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG) {
+static SDValue getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG) {
assert(VT.isVector() && "Expected a vector type");
// Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
// type. This ensures they get CSE'd.
- SDOperand Vec;
+ SDValue Vec;
if (VT.getSizeInBits() == 64) { // MMX
- SDOperand Cst = DAG.getTargetConstant(0, MVT::i32);
+ SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
} else if (HasSSE2) { // SSE2
- SDOperand Cst = DAG.getTargetConstant(0, MVT::i32);
+ SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
} else { // SSE1
- SDOperand Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
+ SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4f32, Cst, Cst, Cst, Cst);
}
return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
@@ -2782,13 +2782,13 @@
/// getOnesVector - Returns a vector of specified type with all bits set.
///
-static SDOperand getOnesVector(MVT VT, SelectionDAG &DAG) {
+static SDValue getOnesVector(MVT VT, SelectionDAG &DAG) {
assert(VT.isVector() && "Expected a vector type");
// Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
// type. This ensures they get CSE'd.
- SDOperand Cst = DAG.getTargetConstant(~0U, MVT::i32);
- SDOperand Vec;
+ SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
+ SDValue Vec;
if (VT.getSizeInBits() == 64) // MMX
Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
else // SSE
@@ -2799,14 +2799,14 @@
/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
/// that point to V2 points to its first element.
-static SDOperand NormalizeMask(SDOperand Mask, SelectionDAG &DAG) {
+static SDValue NormalizeMask(SDValue Mask, SelectionDAG &DAG) {
assert(Mask.getOpcode() == ISD::BUILD_VECTOR);
bool Changed = false;
- SmallVector<SDOperand, 8> MaskVec;
+ SmallVector<SDValue, 8> MaskVec;
unsigned NumElems = Mask.getNumOperands();
for (unsigned i = 0; i != NumElems; ++i) {
- SDOperand Arg = Mask.getOperand(i);
+ SDValue Arg = Mask.getOperand(i);
if (Arg.getOpcode() != ISD::UNDEF) {
unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
if (Val > NumElems) {
@@ -2825,11 +2825,11 @@
/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
/// operation of specified width.
-static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
+static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
MVT BaseVT = MaskVT.getVectorElementType();
- SmallVector<SDOperand, 8> MaskVec;
+ SmallVector<SDValue, 8> MaskVec;
MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
for (unsigned i = 1; i != NumElems; ++i)
MaskVec.push_back(DAG.getConstant(i, BaseVT));
@@ -2838,10 +2838,10 @@
/// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
/// of specified width.
-static SDOperand getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) {
+static SDValue getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) {
MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
MVT BaseVT = MaskVT.getVectorElementType();
- SmallVector<SDOperand, 8> MaskVec;
+ SmallVector<SDValue, 8> MaskVec;
for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
MaskVec.push_back(DAG.getConstant(i, BaseVT));
MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
@@ -2851,11 +2851,11 @@
/// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
/// of specified width.
-static SDOperand getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
+static SDValue getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
MVT BaseVT = MaskVT.getVectorElementType();
unsigned Half = NumElems/2;
- SmallVector<SDOperand, 8> MaskVec;
+ SmallVector<SDValue, 8> MaskVec;
for (unsigned i = 0; i != Half; ++i) {
MaskVec.push_back(DAG.getConstant(i + Half, BaseVT));
MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
@@ -2866,11 +2866,11 @@
/// getSwapEltZeroMask - Returns a vector_shuffle mask for a shuffle that swaps
/// element #0 of a vector with the specified index, leaving the rest of the
/// elements in place.
-static SDOperand getSwapEltZeroMask(unsigned NumElems, unsigned DestElt,
+static SDValue getSwapEltZeroMask(unsigned NumElems, unsigned DestElt,
SelectionDAG &DAG) {
MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
MVT BaseVT = MaskVT.getVectorElementType();
- SmallVector<SDOperand, 8> MaskVec;
+ SmallVector<SDValue, 8> MaskVec;
// Element #0 of the result gets the elt we are replacing.
MaskVec.push_back(DAG.getConstant(DestElt, BaseVT));
for (unsigned i = 1; i != NumElems; ++i)
@@ -2879,13 +2879,13 @@
}
/// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
-static SDOperand PromoteSplat(SDOperand Op, SelectionDAG &DAG, bool HasSSE2) {
+static SDValue PromoteSplat(SDValue Op, SelectionDAG &DAG, bool HasSSE2) {
MVT PVT = HasSSE2 ? MVT::v4i32 : MVT::v4f32;
MVT VT = Op.getValueType();
if (PVT == VT)
return Op;
- SDOperand V1 = Op.getOperand(0);
- SDOperand Mask = Op.getOperand(2);
+ SDValue V1 = Op.getOperand(0);
+ SDValue Mask = Op.getOperand(2);
unsigned NumElems = Mask.getNumOperands();
// Special handling of v4f32 -> v4i32.
if (VT != MVT::v4f32) {
@@ -2898,7 +2898,7 @@
}
V1 = DAG.getNode(ISD::BIT_CONVERT, PVT, V1);
- SDOperand Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, PVT, V1,
+ SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, PVT, V1,
DAG.getNode(ISD::UNDEF, PVT), Mask);
return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
}
@@ -2907,22 +2907,22 @@
/// vector of zero or undef vector. This produces a shuffle where the low
/// element of V2 is swizzled into the zero/undef vector, landing at element
/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
-static SDOperand getShuffleVectorZeroOrUndef(SDOperand V2, unsigned Idx,
+static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
bool isZero, bool HasSSE2,
SelectionDAG &DAG) {
MVT VT = V2.getValueType();
- SDOperand V1 = isZero
+ SDValue V1 = isZero
? getZeroVector(VT, HasSSE2, DAG) : DAG.getNode(ISD::UNDEF, VT);
unsigned NumElems = V2.getValueType().getVectorNumElements();
MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
MVT EVT = MaskVT.getVectorElementType();
- SmallVector<SDOperand, 16> MaskVec;
+ SmallVector<SDValue, 16> MaskVec;
for (unsigned i = 0; i != NumElems; ++i)
if (i == Idx) // If this is the insertion idx, put the low elt of V2 here.
MaskVec.push_back(DAG.getConstant(NumElems, EVT));
else
MaskVec.push_back(DAG.getConstant(i, EVT));
- SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
+ SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
&MaskVec[0], MaskVec.size());
return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
}
@@ -2930,18 +2930,18 @@
/// getNumOfConsecutiveZeros - Return the number of elements in a result of
/// a shuffle that is zero.
static
-unsigned getNumOfConsecutiveZeros(SDOperand Op, SDOperand Mask,
+unsigned getNumOfConsecutiveZeros(SDValue Op, SDValue Mask,
unsigned NumElems, bool Low,
SelectionDAG &DAG) {
unsigned NumZeros = 0;
for (unsigned i = 0; i < NumElems; ++i) {
unsigned Index = Low ? i : NumElems-i-1;
- SDOperand Idx = Mask.getOperand(Index);
+ SDValue Idx = Mask.getOperand(Index);
if (Idx.getOpcode() == ISD::UNDEF) {
++NumZeros;
continue;
}
- SDOperand Elt = DAG.getShuffleScalarElt(Op.Val, Index);
+ SDValue Elt = DAG.getShuffleScalarElt(Op.Val, Index);
if (Elt.Val && isZeroNode(Elt))
++NumZeros;
else
@@ -2952,8 +2952,8 @@
/// isVectorShift - Returns true if the shuffle can be implemented as a
/// logical left or right shift of a vector.
-static bool isVectorShift(SDOperand Op, SDOperand Mask, SelectionDAG &DAG,
- bool &isLeft, SDOperand &ShVal, unsigned &ShAmt) {
+static bool isVectorShift(SDValue Op, SDValue Mask, SelectionDAG &DAG,
+ bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
unsigned NumElems = Mask.getNumOperands();
isLeft = true;
@@ -2969,7 +2969,7 @@
bool SeenV2 = false;
for (unsigned i = NumZeros; i < NumElems; ++i) {
unsigned Val = isLeft ? (i - NumZeros) : i;
- SDOperand Idx = Mask.getOperand(isLeft ? i : (i - NumZeros));
+ SDValue Idx = Mask.getOperand(isLeft ? i : (i - NumZeros));
if (Idx.getOpcode() == ISD::UNDEF)
continue;
unsigned Index = cast<ConstantSDNode>(Idx)->getValue();
@@ -2993,13 +2993,13 @@
/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
///
-static SDOperand LowerBuildVectorv16i8(SDOperand Op, unsigned NonZeros,
+static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
unsigned NumNonZero, unsigned NumZero,
SelectionDAG &DAG, TargetLowering &TLI) {
if (NumNonZero > 8)
- return SDOperand();
+ return SDValue();
- SDOperand V(0, 0);
+ SDValue V(0, 0);
bool First = true;
for (unsigned i = 0; i < 16; ++i) {
bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
@@ -3012,7 +3012,7 @@
}
if ((i & 1) != 0) {
- SDOperand ThisElt(0, 0), LastElt(0, 0);
+ SDValue ThisElt(0, 0), LastElt(0, 0);
bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
if (LastIsNonZero) {
LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1));
@@ -3037,13 +3037,13 @@
/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
///
-static SDOperand LowerBuildVectorv8i16(SDOperand Op, unsigned NonZeros,
+static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
unsigned NumNonZero, unsigned NumZero,
SelectionDAG &DAG, TargetLowering &TLI) {
if (NumNonZero > 4)
- return SDOperand();
+ return SDValue();
- SDOperand V(0, 0);
+ SDValue V(0, 0);
bool First = true;
for (unsigned i = 0; i < 8; ++i) {
bool isNonZero = (NonZeros & (1 << i)) != 0;
@@ -3065,7 +3065,7 @@
/// getVShift - Return a vector logical shift node.
///
-static SDOperand getVShift(bool isLeft, MVT VT, SDOperand SrcOp,
+static SDValue getVShift(bool isLeft, MVT VT, SDValue SrcOp,
unsigned NumBits, SelectionDAG &DAG,
const TargetLowering &TLI) {
bool isMMX = VT.getSizeInBits() == 64;
@@ -3077,8 +3077,8 @@
DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
}
-SDOperand
-X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
+SDValue
+X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
// All zero's are handled with pxor, all one's are handled with pcmpeqd.
if (ISD::isBuildVectorAllZeros(Op.Val) || ISD::isBuildVectorAllOnes(Op.Val)) {
// Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
@@ -3101,9 +3101,9 @@
unsigned NumNonZero = 0;
unsigned NonZeros = 0;
bool IsAllConstants = true;
- SmallSet<SDOperand, 8> Values;
+ SmallSet<SDValue, 8> Values;
for (unsigned i = 0; i < NumElems; ++i) {
- SDOperand Elt = Op.getOperand(i);
+ SDValue Elt = Op.getOperand(i);
if (Elt.getOpcode() == ISD::UNDEF)
continue;
Values.insert(Elt);
@@ -3126,7 +3126,7 @@
// Special case for single non-zero, non-undef, element.
if (NumNonZero == 1 && NumElems <= 4) {
unsigned Idx = CountTrailingZeros_32(NonZeros);
- SDOperand Item = Op.getOperand(Idx);
+ SDValue Item = Op.getOperand(Idx);
// If this is an insertion of an i64 value on x86-32, and if the top bits of
// the value are obviously zero, truncate the value to i32 and do the
@@ -3150,7 +3150,7 @@
// Now we have our 32-bit value zero extended in the low element of
// a vector. If Idx != 0, swizzle it into place.
if (Idx != 0) {
- SDOperand Ops[] = {
+ SDValue Ops[] = {
Item, DAG.getNode(ISD::UNDEF, Item.getValueType()),
getSwapEltZeroMask(VecElts, Idx, DAG)
};
@@ -3184,7 +3184,7 @@
}
if (IsAllConstants) // Otherwise, it's better to do a constpool load.
- return SDOperand();
+ return SDValue();
// Otherwise, if this is a vector with i32 or f32 elements, and the element
// is a non-constant being inserted into an element other than the low one,
@@ -3199,10 +3199,10 @@
Subtarget->hasSSE2(), DAG);
MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
MVT MaskEVT = MaskVT.getVectorElementType();
- SmallVector<SDOperand, 8> MaskVec;
+ SmallVector<SDValue, 8> MaskVec;
for (unsigned i = 0; i < NumElems; i++)
MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
- SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
+ SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
&MaskVec[0], MaskVec.size());
return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item,
DAG.getNode(ISD::UNDEF, VT), Mask);
@@ -3211,41 +3211,41 @@
// Splat is obviously ok. Let legalizer expand it to a shuffle.
if (Values.size() == 1)
- return SDOperand();
+ return SDValue();
// A vector full of immediates; various special cases are already
// handled, so this is best done with a single constant-pool load.
if (IsAllConstants)
- return SDOperand();
+ return SDValue();
// Let legalizer expand 2-wide build_vectors.
if (EVTBits == 64) {
if (NumNonZero == 1) {
// One half is zero or undef.
unsigned Idx = CountTrailingZeros_32(NonZeros);
- SDOperand V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT,
+ SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT,
Op.getOperand(Idx));
return getShuffleVectorZeroOrUndef(V2, Idx, true,
Subtarget->hasSSE2(), DAG);
}
- return SDOperand();
+ return SDValue();
}
// If element VT is < 32 bits, convert it to inserts into a zero vector.
if (EVTBits == 8 && NumElems == 16) {
- SDOperand V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
+ SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
*this);
if (V.Val) return V;
}
if (EVTBits == 16 && NumElems == 8) {
- SDOperand V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
+ SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
*this);
if (V.Val) return V;
}
// If element VT is == 32 bits, turn it into a number of shuffles.
- SmallVector<SDOperand, 8> V;
+ SmallVector<SDValue, 8> V;
V.resize(NumElems);
if (NumElems == 4 && NumZero > 0) {
for (unsigned i = 0; i < 4; ++i) {
@@ -3279,7 +3279,7 @@
MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
MVT EVT = MaskVT.getVectorElementType();
- SmallVector<SDOperand, 8> MaskVec;
+ SmallVector<SDValue, 8> MaskVec;
bool Reverse = (NonZeros & 0x3) == 2;
for (unsigned i = 0; i < 2; ++i)
if (Reverse)
@@ -3292,7 +3292,7 @@
MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
else
MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
- SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
+ SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
&MaskVec[0], MaskVec.size());
return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask);
}
@@ -3303,7 +3303,7 @@
// Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
// : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
// Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
- SDOperand UnpckMask = getUnpacklMask(NumElems, DAG);
+ SDValue UnpckMask = getUnpacklMask(NumElems, DAG);
for (unsigned i = 0; i < NumElems; ++i)
V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
NumElems >>= 1;
@@ -3316,24 +3316,24 @@
return V[0];
}
- return SDOperand();
+ return SDValue();
}
static
-SDOperand LowerVECTOR_SHUFFLEv8i16(SDOperand V1, SDOperand V2,
- SDOperand PermMask, SelectionDAG &DAG,
+SDValue LowerVECTOR_SHUFFLEv8i16(SDValue V1, SDValue V2,
+ SDValue PermMask, SelectionDAG &DAG,
TargetLowering &TLI) {
- SDOperand NewV;
+ SDValue NewV;
MVT MaskVT = MVT::getIntVectorWithNumElements(8);
MVT MaskEVT = MaskVT.getVectorElementType();
MVT PtrVT = TLI.getPointerTy();
- SmallVector<SDOperand, 8> MaskElts(PermMask.Val->op_begin(),
+ SmallVector<SDValue, 8> MaskElts(PermMask.Val->op_begin(),
PermMask.Val->op_end());
// First record which half of which vector the low elements come from.
SmallVector<unsigned, 4> LowQuad(4);
for (unsigned i = 0; i < 4; ++i) {
- SDOperand Elt = MaskElts[i];
+ SDValue Elt = MaskElts[i];
if (Elt.getOpcode() == ISD::UNDEF)
continue;
unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
@@ -3352,7 +3352,7 @@
// Record which half of which vector the high elements come from.
SmallVector<unsigned, 4> HighQuad(4);
for (unsigned i = 4; i < 8; ++i) {
- SDOperand Elt = MaskElts[i];
+ SDValue Elt = MaskElts[i];
if (Elt.getOpcode() == ISD::UNDEF)
continue;
unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
@@ -3371,7 +3371,7 @@
// If it's possible to sort parts of either half with PSHUF{H|L}W, then do it.
if (BestLowQuad != -1 || BestHighQuad != -1) {
// First sort the 4 chunks in order using shufpd.
- SmallVector<SDOperand, 8> MaskVec;
+ SmallVector<SDValue, 8> MaskVec;
if (BestLowQuad != -1)
MaskVec.push_back(DAG.getConstant(BestLowQuad, MVT::i32));
else
@@ -3380,7 +3380,7 @@
MaskVec.push_back(DAG.getConstant(BestHighQuad, MVT::i32));
else
MaskVec.push_back(DAG.getConstant(1, MVT::i32));
- SDOperand Mask= DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, &MaskVec[0],2);
+ SDValue Mask= DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, &MaskVec[0],2);
NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64,
DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V1),
DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V2), Mask);
@@ -3393,7 +3393,7 @@
MaskVec.clear();
bool AnyOutOrder = false;
for (unsigned i = 0; i != 4; ++i) {
- SDOperand Elt = MaskElts[i];
+ SDValue Elt = MaskElts[i];
if (Elt.getOpcode() == ISD::UNDEF) {
MaskVec.push_back(Elt);
InOrder.set(i);
@@ -3411,7 +3411,7 @@
if (AnyOutOrder) {
for (unsigned i = 4; i != 8; ++i)
MaskVec.push_back(DAG.getConstant(i, MaskEVT));
- SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
+ SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
}
}
@@ -3423,7 +3423,7 @@
MaskVec.push_back(DAG.getConstant(i, MaskEVT));
bool AnyOutOrder = false;
for (unsigned i = 4; i != 8; ++i) {
- SDOperand Elt = MaskElts[i];
+ SDValue Elt = MaskElts[i];
if (Elt.getOpcode() == ISD::UNDEF) {
MaskVec.push_back(Elt);
InOrder.set(i);
@@ -3439,7 +3439,7 @@
}
}
if (AnyOutOrder) {
- SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
+ SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
}
}
@@ -3448,9 +3448,9 @@
for (unsigned i = 0; i != 8; ++i) {
if (InOrder[i])
continue;
- SDOperand Elt = MaskElts[i];
+ SDValue Elt = MaskElts[i];
unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
- SDOperand ExtOp = (EltIdx < 8)
+ SDValue ExtOp = (EltIdx < 8)
? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
DAG.getConstant(EltIdx, PtrVT))
: DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
@@ -3468,10 +3468,10 @@
unsigned V1FromV1 = 0;
unsigned V2InOrder = 0;
unsigned V2FromV2 = 0;
- SmallVector<SDOperand, 8> V1Elts;
- SmallVector<SDOperand, 8> V2Elts;
+ SmallVector<SDValue, 8> V1Elts;
+ SmallVector<SDValue, 8> V2Elts;
for (unsigned i = 0; i < 8; ++i) {
- SDOperand Elt = MaskElts[i];
+ SDValue Elt = MaskElts[i];
if (Elt.getOpcode() == ISD::UNDEF) {
V1Elts.push_back(Elt);
V2Elts.push_back(Elt);
@@ -3509,9 +3509,9 @@
if (V1FromV1) {
// If there are elements that are from V1 but out of place,
// then first sort them in place
- SmallVector<SDOperand, 8> MaskVec;
+ SmallVector<SDValue, 8> MaskVec;
for (unsigned i = 0; i < 8; ++i) {
- SDOperand Elt = V1Elts[i];
+ SDValue Elt = V1Elts[i];
if (Elt.getOpcode() == ISD::UNDEF) {
MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
continue;
@@ -3522,19 +3522,19 @@
else
MaskVec.push_back(DAG.getConstant(EltIdx, MaskEVT));
}
- SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
+ SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, V1, V1, Mask);
}
NewV = V1;
for (unsigned i = 0; i < 8; ++i) {
- SDOperand Elt = V1Elts[i];
+ SDValue Elt = V1Elts[i];
if (Elt.getOpcode() == ISD::UNDEF)
continue;
unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
if (EltIdx < 8)
continue;
- SDOperand ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
+ SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
DAG.getConstant(EltIdx - 8, PtrVT));
NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
DAG.getConstant(i, PtrVT));
@@ -3544,11 +3544,11 @@
// All elements are from V1.
NewV = V1;
for (unsigned i = 0; i < 8; ++i) {
- SDOperand Elt = V1Elts[i];
+ SDValue Elt = V1Elts[i];
if (Elt.getOpcode() == ISD::UNDEF)
continue;
unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
- SDOperand ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
+ SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
DAG.getConstant(EltIdx, PtrVT));
NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
DAG.getConstant(i, PtrVT));
@@ -3563,9 +3563,9 @@
/// the right sequence. e.g.
/// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
static
-SDOperand RewriteAsNarrowerShuffle(SDOperand V1, SDOperand V2,
+SDValue RewriteAsNarrowerShuffle(SDValue V1, SDValue V2,
MVT VT,
- SDOperand PermMask, SelectionDAG &DAG,
+ SDValue PermMask, SelectionDAG &DAG,
TargetLowering &TLI) {
unsigned NumElems = PermMask.getNumOperands();
unsigned NewWidth = (NumElems == 4) ? 2 : 4;
@@ -3587,18 +3587,18 @@
NewVT = MVT::v2f64;
}
unsigned Scale = NumElems / NewWidth;
- SmallVector<SDOperand, 8> MaskVec;
+ SmallVector<SDValue, 8> MaskVec;
for (unsigned i = 0; i < NumElems; i += Scale) {
unsigned StartIdx = ~0U;
for (unsigned j = 0; j < Scale; ++j) {
- SDOperand Elt = PermMask.getOperand(i+j);
+ SDValue Elt = PermMask.getOperand(i+j);
if (Elt.getOpcode() == ISD::UNDEF)
continue;
unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
if (StartIdx == ~0U)
StartIdx = EltIdx - (EltIdx % Scale);
if (EltIdx != StartIdx + j)
- return SDOperand();
+ return SDValue();
}
if (StartIdx == ~0U)
MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEltVT));
@@ -3615,8 +3615,8 @@
/// getVZextMovL - Return a zero-extending vector move low node.
///
-static SDOperand getVZextMovL(MVT VT, MVT OpVT,
- SDOperand SrcOp, SelectionDAG &DAG,
+static SDValue getVZextMovL(MVT VT, MVT OpVT,
+ SDValue SrcOp, SelectionDAG &DAG,
const X86Subtarget *Subtarget) {
if (VT == MVT::v2f64 || VT == MVT::v4f32) {
LoadSDNode *LD = NULL;
@@ -3647,18 +3647,18 @@
/// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
/// shuffles.
-static SDOperand
-LowerVECTOR_SHUFFLE_4wide(SDOperand V1, SDOperand V2,
- SDOperand PermMask, MVT VT, SelectionDAG &DAG) {
+static SDValue
+LowerVECTOR_SHUFFLE_4wide(SDValue V1, SDValue V2,
+ SDValue PermMask, MVT VT, SelectionDAG &DAG) {
MVT MaskVT = PermMask.getValueType();
MVT MaskEVT = MaskVT.getVectorElementType();
SmallVector<std::pair<int, int>, 8> Locs;
Locs.reserve(4);
- SmallVector<SDOperand, 8> Mask1(4, DAG.getNode(ISD::UNDEF, MaskEVT));
+ SmallVector<SDValue, 8> Mask1(4, DAG.getNode(ISD::UNDEF, MaskEVT));
unsigned NumHi = 0;
unsigned NumLo = 0;
for (unsigned i = 0; i != 4; ++i) {
- SDOperand Elt = PermMask.getOperand(i);
+ SDValue Elt = PermMask.getOperand(i);
if (Elt.getOpcode() == ISD::UNDEF) {
Locs[i] = std::make_pair(-1, -1);
} else {
@@ -3685,7 +3685,7 @@
DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
&Mask1[0], Mask1.size()));
- SmallVector<SDOperand, 8> Mask2(4, DAG.getNode(ISD::UNDEF, MaskEVT));
+ SmallVector<SDValue, 8> Mask2(4, DAG.getNode(ISD::UNDEF, MaskEVT));
for (unsigned i = 0; i != 4; ++i) {
if (Locs[i].first == -1)
continue;
@@ -3716,7 +3716,7 @@
// Find the element from V2.
unsigned HiIndex;
for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
- SDOperand Elt = PermMask.getOperand(HiIndex);
+ SDValue Elt = PermMask.getOperand(HiIndex);
if (Elt.getOpcode() == ISD::UNDEF)
continue;
unsigned Val = cast<ConstantSDNode>(Elt)->getValue();
@@ -3756,9 +3756,9 @@
// Break it into (shuffle shuffle_hi, shuffle_lo).
Locs.clear();
- SmallVector<SDOperand,8> LoMask(4, DAG.getNode(ISD::UNDEF, MaskEVT));
- SmallVector<SDOperand,8> HiMask(4, DAG.getNode(ISD::UNDEF, MaskEVT));
- SmallVector<SDOperand,8> *MaskPtr = &LoMask;
+ SmallVector<SDValue,8> LoMask(4, DAG.getNode(ISD::UNDEF, MaskEVT));
+ SmallVector<SDValue,8> HiMask(4, DAG.getNode(ISD::UNDEF, MaskEVT));
+ SmallVector<SDValue,8> *MaskPtr = &LoMask;
unsigned MaskIdx = 0;
unsigned LoIdx = 0;
unsigned HiIdx = 2;
@@ -3769,7 +3769,7 @@
LoIdx = 0;
HiIdx = 2;
}
- SDOperand Elt = PermMask.getOperand(i);
+ SDValue Elt = PermMask.getOperand(i);
if (Elt.getOpcode() == ISD::UNDEF) {
Locs[i] = std::make_pair(-1, -1);
} else if (cast<ConstantSDNode>(Elt)->getValue() < 4) {
@@ -3783,13 +3783,13 @@
}
}
- SDOperand LoShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
+ SDValue LoShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
&LoMask[0], LoMask.size()));
- SDOperand HiShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
+ SDValue HiShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
&HiMask[0], HiMask.size()));
- SmallVector<SDOperand, 8> MaskOps;
+ SmallVector<SDValue, 8> MaskOps;
for (unsigned i = 0; i != 4; ++i) {
if (Locs[i].first == -1) {
MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
@@ -3803,11 +3803,11 @@
&MaskOps[0], MaskOps.size()));
}
-SDOperand
-X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
- SDOperand V1 = Op.getOperand(0);
- SDOperand V2 = Op.getOperand(1);
- SDOperand PermMask = Op.getOperand(2);
+SDValue
+X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
+ SDValue V1 = Op.getOperand(0);
+ SDValue V2 = Op.getOperand(1);
+ SDValue PermMask = Op.getOperand(2);
MVT VT = Op.getValueType();
unsigned NumElems = PermMask.getNumOperands();
bool isMMX = VT.getSizeInBits() == 64;
@@ -3836,26 +3836,26 @@
// If the shuffle can be profitably rewritten as a narrower shuffle, then
// do it!
if (VT == MVT::v8i16 || VT == MVT::v16i8) {
- SDOperand NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this);
+ SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this);
if (NewOp.Val)
return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG));
} else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
// FIXME: Figure out a cleaner way to do this.
// Try to make use of movq to zero out the top part.
if (ISD::isBuildVectorAllZeros(V2.Val)) {
- SDOperand NewOp = RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
+ SDValue NewOp = RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
DAG, *this);
if (NewOp.Val) {
- SDOperand NewV1 = NewOp.getOperand(0);
- SDOperand NewV2 = NewOp.getOperand(1);
- SDOperand NewMask = NewOp.getOperand(2);
+ SDValue NewV1 = NewOp.getOperand(0);
+ SDValue NewV2 = NewOp.getOperand(1);
+ SDValue NewMask = NewOp.getOperand(2);
if (isCommutedMOVL(NewMask.Val, true, false)) {
NewOp = CommuteVectorShuffle(NewOp, NewV1, NewV2, NewMask, DAG);
return getVZextMovL(VT, NewOp.getValueType(), NewV2, DAG, Subtarget);
}
}
} else if (ISD::isBuildVectorAllZeros(V1.Val)) {
- SDOperand NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
+ SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
DAG, *this);
if (NewOp.Val && X86::isMOVLMask(NewOp.getOperand(2).Val))
return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
@@ -3866,7 +3866,7 @@
// Check if this can be converted into a logical shift.
bool isLeft = false;
unsigned ShAmt = 0;
- SDOperand ShVal;
+ SDValue ShVal;
bool isShift = isVectorShift(Op, PermMask, DAG, isLeft, ShVal, ShAmt);
if (isShift && ShVal.hasOneUse()) {
// If the shifted value has multiple uses, it may be cheaper to use
@@ -3925,7 +3925,7 @@
// V2 is a splat, so the mask may be malformed. That is, it may point
// to any V2 element. The instruction selectior won't like this. Get
// a corrected mask and commute to form a proper MOVS{S|D}.
- SDOperand NewMask = getMOVLMask(NumElems, DAG);
+ SDValue NewMask = getMOVLMask(NumElems, DAG);
if (NewMask.Val != PermMask.Val)
Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
}
@@ -3942,13 +3942,13 @@
// Normalize mask so all entries that point to V2 points to its first
// element then try to match unpck{h|l} again. If match, return a
// new vector_shuffle with the corrected mask.
- SDOperand NewMask = NormalizeMask(PermMask, DAG);
+ SDValue NewMask = NormalizeMask(PermMask, DAG);
if (NewMask.Val != PermMask.Val) {
if (X86::isUNPCKLMask(PermMask.Val, true)) {
- SDOperand NewMask = getUnpacklMask(NumElems, DAG);
+ SDValue NewMask = getUnpacklMask(NumElems, DAG);
return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
} else if (X86::isUNPCKHMask(PermMask.Val, true)) {
- SDOperand NewMask = getUnpackhMask(NumElems, DAG);
+ SDValue NewMask = getUnpackhMask(NumElems, DAG);
return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
}
}
@@ -4005,7 +4005,7 @@
// Handle v8i16 specifically since SSE can do byte extraction and insertion.
if (VT == MVT::v8i16) {
- SDOperand NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG, *this);
+ SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG, *this);
if (NewOp.Val)
return NewOp;
}
@@ -4014,23 +4014,23 @@
if (NumElems == 4 && !isMMX)
return LowerVECTOR_SHUFFLE_4wide(V1, V2, PermMask, VT, DAG);
- return SDOperand();
+ return SDValue();
}
-SDOperand
-X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDOperand Op,
+SDValue
+X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
SelectionDAG &DAG) {
MVT VT = Op.getValueType();
if (VT.getSizeInBits() == 8) {
- SDOperand Extract = DAG.getNode(X86ISD::PEXTRB, MVT::i32,
+ SDValue Extract = DAG.getNode(X86ISD::PEXTRB, MVT::i32,
Op.getOperand(0), Op.getOperand(1));
- SDOperand Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract,
+ SDValue Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract,
DAG.getValueType(VT));
return DAG.getNode(ISD::TRUNCATE, VT, Assert);
} else if (VT.getSizeInBits() == 16) {
- SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, MVT::i32,
+ SDValue Extract = DAG.getNode(X86ISD::PEXTRW, MVT::i32,
Op.getOperand(0), Op.getOperand(1));
- SDOperand Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract,
+ SDValue Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract,
DAG.getValueType(VT));
return DAG.getNode(ISD::TRUNCATE, VT, Assert);
} else if (VT == MVT::f32) {
@@ -4038,28 +4038,28 @@
// the result back to FR32 register. It's only worth matching if the
// result has a single use which is a store or a bitcast to i32.
if (!Op.hasOneUse())
- return SDOperand();
+ return SDValue();
SDNode *User = *Op.Val->use_begin();
if (User->getOpcode() != ISD::STORE &&
(User->getOpcode() != ISD::BIT_CONVERT ||
User->getValueType(0) != MVT::i32))
- return SDOperand();
- SDOperand Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
+ return SDValue();
+ SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Op.getOperand(0)),
Op.getOperand(1));
return DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Extract);
}
- return SDOperand();
+ return SDValue();
}
-SDOperand
-X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
+SDValue
+X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
if (!isa<ConstantSDNode>(Op.getOperand(1)))
- return SDOperand();
+ return SDValue();
if (Subtarget->hasSSE41()) {
- SDOperand Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
+ SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
if (Res.Val)
return Res;
}
@@ -4067,7 +4067,7 @@
MVT VT = Op.getValueType();
// TODO: handle v16i8.
if (VT.getSizeInBits() == 16) {
- SDOperand Vec = Op.getOperand(0);
+ SDValue Vec = Op.getOperand(0);
unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
if (Idx == 0)
return DAG.getNode(ISD::TRUNCATE, MVT::i16,
@@ -4076,9 +4076,9 @@
Op.getOperand(1)));
// Transform it so it match pextrw which produces a 32-bit result.
MVT EVT = (MVT::SimpleValueType)(VT.getSimpleVT()+1);
- SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, EVT,
+ SDValue Extract = DAG.getNode(X86ISD::PEXTRW, EVT,
Op.getOperand(0), Op.getOperand(1));
- SDOperand Assert = DAG.getNode(ISD::AssertZext, EVT, Extract,
+ SDValue Assert = DAG.getNode(ISD::AssertZext, EVT, Extract,
DAG.getValueType(VT));
return DAG.getNode(ISD::TRUNCATE, VT, Assert);
} else if (VT.getSizeInBits() == 32) {
@@ -4087,7 +4087,7 @@
return Op;
// SHUFPS the element to the lowest double word, then movss.
MVT MaskVT = MVT::getIntVectorWithNumElements(4);
- SmallVector<SDOperand, 8> IdxVec;
+ SmallVector<SDValue, 8> IdxVec;
IdxVec.
push_back(DAG.getConstant(Idx, MaskVT.getVectorElementType()));
IdxVec.
@@ -4096,9 +4096,9 @@
push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
IdxVec.
push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
- SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
+ SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
&IdxVec[0], IdxVec.size());
- SDOperand Vec = Op.getOperand(0);
+ SDValue Vec = Op.getOperand(0);
Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
@@ -4115,30 +4115,30 @@
// Note if the lower 64 bits of the result of the UNPCKHPD is then stored
// to a f64mem, the whole operation is folded into a single MOVHPDmr.
MVT MaskVT = MVT::getIntVectorWithNumElements(2);
- SmallVector<SDOperand, 8> IdxVec;
+ SmallVector<SDValue, 8> IdxVec;
IdxVec.push_back(DAG.getConstant(1, MaskVT.getVectorElementType()));
IdxVec.
push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
- SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
+ SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
&IdxVec[0], IdxVec.size());
- SDOperand Vec = Op.getOperand(0);
+ SDValue Vec = Op.getOperand(0);
Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
DAG.getIntPtrConstant(0));
}
- return SDOperand();
+ return SDValue();
}
-SDOperand
-X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDOperand Op, SelectionDAG &DAG){
+SDValue
+X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
MVT VT = Op.getValueType();
MVT EVT = VT.getVectorElementType();
- SDOperand N0 = Op.getOperand(0);
- SDOperand N1 = Op.getOperand(1);
- SDOperand N2 = Op.getOperand(2);
+ SDValue N0 = Op.getOperand(0);
+ SDValue N1 = Op.getOperand(1);
+ SDValue N2 = Op.getOperand(2);
if ((EVT.getSizeInBits() == 8) || (EVT.getSizeInBits() == 16)) {
unsigned Opc = (EVT.getSizeInBits() == 8) ? X86ISD::PINSRB
@@ -4162,11 +4162,11 @@
N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue() << 4);
return DAG.getNode(X86ISD::INSERTPS, VT, N0, N1, N2);
}
- return SDOperand();
+ return SDValue();
}
-SDOperand
-X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
+SDValue
+X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
MVT VT = Op.getValueType();
MVT EVT = VT.getVectorElementType();
@@ -4174,11 +4174,11 @@
return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
if (EVT == MVT::i8)
- return SDOperand();
+ return SDValue();
- SDOperand N0 = Op.getOperand(0);
- SDOperand N1 = Op.getOperand(1);
- SDOperand N2 = Op.getOperand(2);
+ SDValue N0 = Op.getOperand(0);
+ SDValue N1 = Op.getOperand(1);
+ SDValue N2 = Op.getOperand(2);
if (EVT.getSizeInBits() == 16) {
// Transform it so it match pinsrw which expects a 16-bit value in a GR32
@@ -4189,18 +4189,18 @@
N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue());
return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
}
- return SDOperand();
+ return SDValue();
}
-SDOperand
-X86TargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
+SDValue
+X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
if (Op.getValueType() == MVT::v2f32)
return DAG.getNode(ISD::BIT_CONVERT, MVT::v2f32,
DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2i32,
DAG.getNode(ISD::BIT_CONVERT, MVT::i32,
Op.getOperand(0))));
- SDOperand AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0));
+ SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0));
MVT VT = MVT::v2i32;
switch (Op.getValueType().getSimpleVT()) {
default: break;
@@ -4219,10 +4219,10 @@
// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
// be used to form addressing mode. These wrapped nodes will be selected
// into MOV32ri.
-SDOperand
-X86TargetLowering::LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
+SDValue
+X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
- SDOperand Result = DAG.getTargetConstantPool(CP->getConstVal(),
+ SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(),
getPointerTy(),
CP->getAlignment());
Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
@@ -4237,10 +4237,10 @@
return Result;
}
-SDOperand
-X86TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
+SDValue
+X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
- SDOperand Result = DAG.getTargetGlobalAddress(GV, getPointerTy());
+ SDValue Result = DAG.getTargetGlobalAddress(GV, getPointerTy());
Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
// With PIC, the address is actually $g + Offset.
if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
@@ -4263,22 +4263,22 @@
}
// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
-static SDOperand
+static SDValue
LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
const MVT PtrVT) {
- SDOperand InFlag;
- SDOperand Chain = DAG.getCopyToReg(DAG.getEntryNode(), X86::EBX,
+ SDValue InFlag;
+ SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), X86::EBX,
DAG.getNode(X86ISD::GlobalBaseReg,
PtrVT), InFlag);
InFlag = Chain.getValue(1);
// emit leal symbol at TLSGD(,%ebx,1), %eax
SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
- SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
+ SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
GA->getValueType(0),
GA->getOffset());
- SDOperand Ops[] = { Chain, TGA, InFlag };
- SDOperand Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 3);
+ SDValue Ops[] = { Chain, TGA, InFlag };
+ SDValue Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 3);
InFlag = Result.getValue(2);
Chain = Result.getValue(1);
@@ -4288,7 +4288,7 @@
InFlag = Chain.getValue(1);
NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
- SDOperand Ops1[] = { Chain,
+ SDValue Ops1[] = { Chain,
DAG.getTargetExternalSymbol("___tls_get_addr",
PtrVT),
DAG.getRegister(X86::EAX, PtrVT),
@@ -4301,18 +4301,18 @@
}
// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
-static SDOperand
+static SDValue
LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
const MVT PtrVT) {
- SDOperand InFlag, Chain;
+ SDValue InFlag, Chain;
// emit leaq symbol at TLSGD(%rip), %rdi
SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
- SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
+ SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
GA->getValueType(0),
GA->getOffset());
- SDOperand Ops[] = { DAG.getEntryNode(), TGA};
- SDOperand Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 2);
+ SDValue Ops[] = { DAG.getEntryNode(), TGA};
+ SDValue Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 2);
Chain = Result.getValue(1);
InFlag = Result.getValue(2);
@@ -4322,7 +4322,7 @@
InFlag = Chain.getValue(1);
NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
- SDOperand Ops1[] = { Chain,
+ SDValue Ops1[] = { Chain,
DAG.getTargetExternalSymbol("___tls_get_addr",
PtrVT),
DAG.getRegister(X86::RDI, PtrVT),
@@ -4335,16 +4335,16 @@
// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
// "local exec" model.
-static SDOperand LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
+static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
const MVT PtrVT) {
// Get the Thread Pointer
- SDOperand ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, PtrVT);
+ SDValue ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, PtrVT);
// emit "addl x at ntpoff,%eax" (local exec) or "addl x at indntpoff,%eax" (initial
// exec)
- SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
+ SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
GA->getValueType(0),
GA->getOffset());
- SDOperand Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA);
+ SDValue Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA);
if (GA->getGlobal()->isDeclaration()) // initial exec TLS model
Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset,
@@ -4355,8 +4355,8 @@
return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset);
}
-SDOperand
-X86TargetLowering::LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) {
+SDValue
+X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
// TODO: implement the "local dynamic" model
// TODO: implement the "initial exec"model for pic executables
assert(Subtarget->isTargetELF() &&
@@ -4374,10 +4374,10 @@
}
}
-SDOperand
-X86TargetLowering::LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG) {
+SDValue
+X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
- SDOperand Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
+ SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
// With PIC, the address is actually $g + Offset.
if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
@@ -4390,9 +4390,9 @@
return Result;
}
-SDOperand X86TargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
+SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
- SDOperand Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
+ SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
// With PIC, the address is actually $g + Offset.
if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
@@ -4407,19 +4407,19 @@
/// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
/// take a 2 x i32 value to shift plus a shift amount.
-SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) {
+SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
assert(Op.getNumOperands() == 3 && "Not a double-shift!");
MVT VT = Op.getValueType();
unsigned VTBits = VT.getSizeInBits();
bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
- SDOperand ShOpLo = Op.getOperand(0);
- SDOperand ShOpHi = Op.getOperand(1);
- SDOperand ShAmt = Op.getOperand(2);
- SDOperand Tmp1 = isSRA ?
+ SDValue ShOpLo = Op.getOperand(0);
+ SDValue ShOpHi = Op.getOperand(1);
+ SDValue ShAmt = Op.getOperand(2);
+ SDValue Tmp1 = isSRA ?
DAG.getNode(ISD::SRA, VT, ShOpHi, DAG.getConstant(VTBits - 1, MVT::i8)) :
DAG.getConstant(0, VT);
- SDOperand Tmp2, Tmp3;
+ SDValue Tmp2, Tmp3;
if (Op.getOpcode() == ISD::SHL_PARTS) {
Tmp2 = DAG.getNode(X86ISD::SHLD, VT, ShOpHi, ShOpLo, ShAmt);
Tmp3 = DAG.getNode(ISD::SHL, VT, ShOpLo, ShAmt);
@@ -4428,15 +4428,15 @@
Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, VT, ShOpHi, ShAmt);
}
- SDOperand AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt,
+ SDValue AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt,
DAG.getConstant(VTBits, MVT::i8));
- SDOperand Cond = DAG.getNode(X86ISD::CMP, VT,
+ SDValue Cond = DAG.getNode(X86ISD::CMP, VT,
AndNode, DAG.getConstant(0, MVT::i8));
- SDOperand Hi, Lo;
- SDOperand CC = DAG.getConstant(X86::COND_NE, MVT::i8);
- SDOperand Ops0[4] = { Tmp2, Tmp3, CC, Cond };
- SDOperand Ops1[4] = { Tmp3, Tmp1, CC, Cond };
+ SDValue Hi, Lo;
+ SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
+ SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
+ SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
if (Op.getOpcode() == ISD::SHL_PARTS) {
Hi = DAG.getNode(X86ISD::CMOV, VT, Ops0, 4);
@@ -4446,27 +4446,27 @@
Hi = DAG.getNode(X86ISD::CMOV, VT, Ops1, 4);
}
- SDOperand Ops[2] = { Lo, Hi };
+ SDValue Ops[2] = { Lo, Hi };
return DAG.getMergeValues(Ops, 2);
}
-SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
+SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
MVT SrcVT = Op.getOperand(0).getValueType();
assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
"Unknown SINT_TO_FP to lower!");
// These are really Legal; caller falls through into that case.
if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
- return SDOperand();
+ return SDValue();
if (SrcVT == MVT::i64 && Op.getValueType() != MVT::f80 &&
Subtarget->is64Bit())
- return SDOperand();
+ return SDValue();
unsigned Size = SrcVT.getSizeInBits()/8;
MachineFunction &MF = DAG.getMachineFunction();
int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
- SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
- SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0),
+ SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
+ SDValue Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0),
StackSlot,
PseudoSourceValue::getFixedStack(SSFI), 0);
@@ -4477,25 +4477,25 @@
Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
else
Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
- SmallVector<SDOperand, 8> Ops;
+ SmallVector<SDValue, 8> Ops;
Ops.push_back(Chain);
Ops.push_back(StackSlot);
Ops.push_back(DAG.getValueType(SrcVT));
- SDOperand Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD,
+ SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD,
Tys, &Ops[0], Ops.size());
if (useSSE) {
Chain = Result.getValue(1);
- SDOperand InFlag = Result.getValue(2);
+ SDValue InFlag = Result.getValue(2);
// FIXME: Currently the FST is flagged to the FILD_FLAG. This
// shouldn't be necessary except that RFP cannot be live across
// multiple blocks. When stackifier is fixed, they can be uncoupled.
MachineFunction &MF = DAG.getMachineFunction();
int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
- SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
+ SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
Tys = DAG.getVTList(MVT::Other);
- SmallVector<SDOperand, 8> Ops;
+ SmallVector<SDValue, 8> Ops;
Ops.push_back(Chain);
Ops.push_back(Result);
Ops.push_back(StackSlot);
@@ -4509,8 +4509,8 @@
return Result;
}
-std::pair<SDOperand,SDOperand> X86TargetLowering::
-FP_TO_SINTHelper(SDOperand Op, SelectionDAG &DAG) {
+std::pair<SDValue,SDValue> X86TargetLowering::
+FP_TO_SINTHelper(SDValue Op, SelectionDAG &DAG) {
assert(Op.getValueType().getSimpleVT() <= MVT::i64 &&
Op.getValueType().getSimpleVT() >= MVT::i16 &&
"Unknown FP_TO_SINT to lower!");
@@ -4518,18 +4518,18 @@
// These are really Legal.
if (Op.getValueType() == MVT::i32 &&
isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
- return std::make_pair(SDOperand(), SDOperand());
+ return std::make_pair(SDValue(), SDValue());
if (Subtarget->is64Bit() &&
Op.getValueType() == MVT::i64 &&
Op.getOperand(0).getValueType() != MVT::f80)
- return std::make_pair(SDOperand(), SDOperand());
+ return std::make_pair(SDValue(), SDValue());
// We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
// stack slot.
MachineFunction &MF = DAG.getMachineFunction();
unsigned MemSize = Op.getValueType().getSizeInBits()/8;
int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
- SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
+ SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
unsigned Opc;
switch (Op.getValueType().getSimpleVT()) {
default: assert(0 && "Invalid FP_TO_SINT to lower!");
@@ -4538,14 +4538,14 @@
case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
}
- SDOperand Chain = DAG.getEntryNode();
- SDOperand Value = Op.getOperand(0);
+ SDValue Chain = DAG.getEntryNode();
+ SDValue Value = Op.getOperand(0);
if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
Chain = DAG.getStore(Chain, Value, StackSlot,
PseudoSourceValue::getFixedStack(SSFI), 0);
SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
- SDOperand Ops[] = {
+ SDValue Ops[] = {
Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
};
Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
@@ -4555,30 +4555,30 @@
}
// Build the FP_TO_INT*_IN_MEM
- SDOperand Ops[] = { Chain, Value, StackSlot };
- SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops, 3);
+ SDValue Ops[] = { Chain, Value, StackSlot };
+ SDValue FIST = DAG.getNode(Opc, MVT::Other, Ops, 3);
return std::make_pair(FIST, StackSlot);
}
-SDOperand X86TargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
- std::pair<SDOperand,SDOperand> Vals = FP_TO_SINTHelper(Op, DAG);
- SDOperand FIST = Vals.first, StackSlot = Vals.second;
- if (FIST.Val == 0) return SDOperand();
+SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
+ std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(Op, DAG);
+ SDValue FIST = Vals.first, StackSlot = Vals.second;
+ if (FIST.Val == 0) return SDValue();
// Load the result.
return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
}
SDNode *X86TargetLowering::ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG) {
- std::pair<SDOperand,SDOperand> Vals = FP_TO_SINTHelper(SDOperand(N, 0), DAG);
- SDOperand FIST = Vals.first, StackSlot = Vals.second;
+ std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(SDValue(N, 0), DAG);
+ SDValue FIST = Vals.first, StackSlot = Vals.second;
if (FIST.Val == 0) return 0;
MVT VT = N->getValueType(0);
// Return a load from the stack slot.
- SDOperand Res = DAG.getLoad(VT, FIST, StackSlot, NULL, 0);
+ SDValue Res = DAG.getLoad(VT, FIST, StackSlot, NULL, 0);
// Use MERGE_VALUES to drop the chain result value and get a node with one
// result. This requires turning off getMergeValues simplification, since
@@ -4586,7 +4586,7 @@
return DAG.getMergeValues(&Res, 1, false).Val;
}
-SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) {
+SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
MVT VT = Op.getValueType();
MVT EltVT = VT;
if (VT.isVector())
@@ -4604,14 +4604,14 @@
CV.push_back(C);
}
Constant *C = ConstantVector::get(CV);
- SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
- SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
+ SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
+ SDValue Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
PseudoSourceValue::getConstantPool(), 0,
false, 16);
return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
}
-SDOperand X86TargetLowering::LowerFNEG(SDOperand Op, SelectionDAG &DAG) {
+SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
MVT VT = Op.getValueType();
MVT EltVT = VT;
unsigned EltNum = 1;
@@ -4632,8 +4632,8 @@
CV.push_back(C);
}
Constant *C = ConstantVector::get(CV);
- SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
- SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
+ SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
+ SDValue Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
PseudoSourceValue::getConstantPool(), 0,
false, 16);
if (VT.isVector()) {
@@ -4646,9 +4646,9 @@
}
}
-SDOperand X86TargetLowering::LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
- SDOperand Op0 = Op.getOperand(0);
- SDOperand Op1 = Op.getOperand(1);
+SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
+ SDValue Op0 = Op.getOperand(0);
+ SDValue Op1 = Op.getOperand(1);
MVT VT = Op.getValueType();
MVT SrcVT = Op1.getValueType();
@@ -4678,11 +4678,11 @@
CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
}
Constant *C = ConstantVector::get(CV);
- SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
- SDOperand Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx,
+ SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
+ SDValue Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx,
PseudoSourceValue::getConstantPool(), 0,
false, 16);
- SDOperand SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1);
+ SDValue SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1);
// Shift sign bit right or left if the two operands have different types.
if (SrcVT.bitsGT(VT)) {
@@ -4708,21 +4708,21 @@
}
C = ConstantVector::get(CV);
CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
- SDOperand Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
+ SDValue Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
PseudoSourceValue::getConstantPool(), 0,
false, 16);
- SDOperand Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2);
+ SDValue Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2);
// Or the value with the sign bit.
return DAG.getNode(X86ISD::FOR, VT, Val, SignBit);
}
-SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
+SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
- SDOperand Cond;
- SDOperand Op0 = Op.getOperand(0);
- SDOperand Op1 = Op.getOperand(1);
- SDOperand CC = Op.getOperand(2);
+ SDValue Cond;
+ SDValue Op0 = Op.getOperand(0);
+ SDValue Op1 = Op.getOperand(1);
+ SDValue CC = Op.getOperand(2);
ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
unsigned X86CC;
@@ -4740,27 +4740,27 @@
switch (SetCCOpcode) {
default: assert(false && "Illegal floating point SetCC!");
case ISD::SETOEQ: { // !PF & ZF
- SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8,
+ SDValue Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8,
DAG.getConstant(X86::COND_NP, MVT::i8), Cond);
- SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
+ SDValue Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
DAG.getConstant(X86::COND_E, MVT::i8), Cond);
return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
}
case ISD::SETUNE: { // PF | !ZF
- SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8,
+ SDValue Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8,
DAG.getConstant(X86::COND_P, MVT::i8), Cond);
- SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
+ SDValue Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
DAG.getConstant(X86::COND_NE, MVT::i8), Cond);
return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
}
}
}
-SDOperand X86TargetLowering::LowerVSETCC(SDOperand Op, SelectionDAG &DAG) {
- SDOperand Cond;
- SDOperand Op0 = Op.getOperand(0);
- SDOperand Op1 = Op.getOperand(1);
- SDOperand CC = Op.getOperand(2);
+SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
+ SDValue Cond;
+ SDValue Op0 = Op.getOperand(0);
+ SDValue Op1 = Op.getOperand(1);
+ SDValue CC = Op.getOperand(2);
MVT VT = Op.getValueType();
ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
@@ -4798,13 +4798,13 @@
// In the two special cases we can't handle, emit two comparisons.
if (SSECC == 8) {
if (SetCCOpcode == ISD::SETUEQ) {
- SDOperand UNORD, EQ;
+ SDValue UNORD, EQ;
UNORD = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
EQ = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
return DAG.getNode(ISD::OR, VT, UNORD, EQ);
}
else if (SetCCOpcode == ISD::SETONE) {
- SDOperand ORD, NEQ;
+ SDValue ORD, NEQ;
ORD = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
NEQ = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
return DAG.getNode(ISD::AND, VT, ORD, NEQ);
@@ -4849,32 +4849,32 @@
// bits of the inputs before performing those operations.
if (FlipSigns) {
MVT EltVT = VT.getVectorElementType();
- SDOperand SignBit = DAG.getConstant(EltVT.getIntegerVTSignBit(), EltVT);
- std::vector<SDOperand> SignBits(VT.getVectorNumElements(), SignBit);
- SDOperand SignVec = DAG.getNode(ISD::BUILD_VECTOR, VT, &SignBits[0],
+ SDValue SignBit = DAG.getConstant(EltVT.getIntegerVTSignBit(), EltVT);
+ std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
+ SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, VT, &SignBits[0],
SignBits.size());
Op0 = DAG.getNode(ISD::XOR, VT, Op0, SignVec);
Op1 = DAG.getNode(ISD::XOR, VT, Op1, SignVec);
}
- SDOperand Result = DAG.getNode(Opc, VT, Op0, Op1);
+ SDValue Result = DAG.getNode(Opc, VT, Op0, Op1);
// If the logical-not of the result is required, perform that now.
if (Invert) {
MVT EltVT = VT.getVectorElementType();
- SDOperand NegOne = DAG.getConstant(EltVT.getIntegerVTBitMask(), EltVT);
- std::vector<SDOperand> NegOnes(VT.getVectorNumElements(), NegOne);
- SDOperand NegOneV = DAG.getNode(ISD::BUILD_VECTOR, VT, &NegOnes[0],
+ SDValue NegOne = DAG.getConstant(EltVT.getIntegerVTBitMask(), EltVT);
+ std::vector<SDValue> NegOnes(VT.getVectorNumElements(), NegOne);
+ SDValue NegOneV = DAG.getNode(ISD::BUILD_VECTOR, VT, &NegOnes[0],
NegOnes.size());
Result = DAG.getNode(ISD::XOR, VT, Result, NegOneV);
}
return Result;
}
-SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) {
+SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
bool addTest = true;
- SDOperand Cond = Op.getOperand(0);
- SDOperand CC;
+ SDValue Cond = Op.getOperand(0);
+ SDValue CC;
if (Cond.getOpcode() == ISD::SETCC)
Cond = LowerSETCC(Cond, DAG);
@@ -4884,7 +4884,7 @@
if (Cond.getOpcode() == X86ISD::SETCC) {
CC = Cond.getOperand(0);
- SDOperand Cmp = Cond.getOperand(1);
+ SDValue Cmp = Cond.getOperand(1);
unsigned Opc = Cmp.getOpcode();
MVT VT = Op.getValueType();
@@ -4908,7 +4908,7 @@
const MVT *VTs = DAG.getNodeValueTypes(Op.getValueType(),
MVT::Flag);
- SmallVector<SDOperand, 4> Ops;
+ SmallVector<SDValue, 4> Ops;
// X86ISD::CMOV means set the result (which is operand 1) to the RHS if
// condition is true.
Ops.push_back(Op.getOperand(2));
@@ -4918,12 +4918,12 @@
return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
}
-SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) {
+SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
bool addTest = true;
- SDOperand Chain = Op.getOperand(0);
- SDOperand Cond = Op.getOperand(1);
- SDOperand Dest = Op.getOperand(2);
- SDOperand CC;
+ SDValue Chain = Op.getOperand(0);
+ SDValue Cond = Op.getOperand(1);
+ SDValue Dest = Op.getOperand(2);
+ SDValue CC;
if (Cond.getOpcode() == ISD::SETCC)
Cond = LowerSETCC(Cond, DAG);
@@ -4933,7 +4933,7 @@
if (Cond.getOpcode() == X86ISD::SETCC) {
CC = Cond.getOperand(0);
- SDOperand Cmp = Cond.getOperand(1);
+ SDValue Cmp = Cond.getOperand(1);
unsigned Opc = Cmp.getOpcode();
if (Opc == X86ISD::CMP ||
Opc == X86ISD::COMI ||
@@ -4957,18 +4957,18 @@
// bytes in one go. Touching the stack at 4K increments is necessary to ensure
// that the guard pages used by the OS virtual memory manager are allocated in
// correct sequence.
-SDOperand
-X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op,
+SDValue
+X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
SelectionDAG &DAG) {
assert(Subtarget->isTargetCygMing() &&
"This should be used only on Cygwin/Mingw targets");
// Get the inputs.
- SDOperand Chain = Op.getOperand(0);
- SDOperand Size = Op.getOperand(1);
+ SDValue Chain = Op.getOperand(0);
+ SDValue Size = Op.getOperand(1);
// FIXME: Ensure alignment here
- SDOperand Flag;
+ SDValue Flag;
MVT IntPtr = getPointerTy();
MVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
@@ -4979,7 +4979,7 @@
Flag = Chain.getValue(1);
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
- SDOperand Ops[] = { Chain,
+ SDValue Ops[] = { Chain,
DAG.getTargetExternalSymbol("_alloca", IntPtr),
DAG.getRegister(X86::EAX, IntPtr),
DAG.getRegister(X86StackPtr, SPTy),
@@ -4994,15 +4994,15 @@
Chain = DAG.getCopyFromReg(Chain, X86StackPtr, SPTy).getValue(1);
- SDOperand Ops1[2] = { Chain.getValue(0), Chain };
+ SDValue Ops1[2] = { Chain.getValue(0), Chain };
return DAG.getMergeValues(Ops1, 2);
}
-SDOperand
+SDValue
X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG,
- SDOperand Chain,
- SDOperand Dst, SDOperand Src,
- SDOperand Size, unsigned Align,
+ SDValue Chain,
+ SDValue Dst, SDValue Src,
+ SDValue Size, unsigned Align,
const Value *DstSV, uint64_t DstSVOff) {
ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
@@ -5012,7 +5012,7 @@
if ((Align & 3) == 0 ||
!ConstantSize ||
ConstantSize->getValue() > getSubtarget()->getMaxInlineSizeThreshold()) {
- SDOperand InFlag(0, 0);
+ SDValue InFlag(0, 0);
// Check to see if there is a specialized entry-point for memory zeroing.
ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
@@ -5027,7 +5027,7 @@
Args.push_back(Entry);
Entry.Node = Size;
Args.push_back(Entry);
- std::pair<SDOperand,SDOperand> CallResult =
+ std::pair<SDValue,SDValue> CallResult =
LowerCallTo(Chain, Type::VoidTy, false, false, false, CallingConv::C,
false, DAG.getExternalSymbol(bzeroEntry, IntPtr),
Args, DAG);
@@ -5035,13 +5035,13 @@
}
// Otherwise have the target-independent code call memset.
- return SDOperand();
+ return SDValue();
}
uint64_t SizeVal = ConstantSize->getValue();
- SDOperand InFlag(0, 0);
+ SDValue InFlag(0, 0);
MVT AVT;
- SDOperand Count;
+ SDValue Count;
ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
unsigned BytesLeft = 0;
bool TwoRepStos = false;
@@ -5098,7 +5098,7 @@
InFlag = Chain.getValue(1);
SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
- SmallVector<SDOperand, 8> Ops;
+ SmallVector<SDValue, 8> Ops;
Ops.push_back(Chain);
Ops.push_back(DAG.getValueType(AVT));
Ops.push_back(InFlag);
@@ -5108,7 +5108,7 @@
InFlag = Chain.getValue(1);
Count = Size;
MVT CVT = Count.getValueType();
- SDOperand Left = DAG.getNode(ISD::AND, CVT, Count,
+ SDValue Left = DAG.getNode(ISD::AND, CVT, Count,
DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
Left, InFlag);
@@ -5137,11 +5137,11 @@
return Chain;
}
-SDOperand
+SDValue
X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG,
- SDOperand Chain,
- SDOperand Dst, SDOperand Src,
- SDOperand Size, unsigned Align,
+ SDValue Chain,
+ SDValue Dst, SDValue Src,
+ SDValue Size, unsigned Align,
bool AlwaysInline,
const Value *DstSV, uint64_t DstSVOff,
const Value *SrcSV, uint64_t SrcSVOff){
@@ -5150,10 +5150,10 @@
// within a subtarget-specific limit.
ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
if (!ConstantSize)
- return SDOperand();
+ return SDValue();
uint64_t SizeVal = ConstantSize->getValue();
if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
- return SDOperand();
+ return SDValue();
MVT AVT;
unsigned BytesLeft = 0;
@@ -5168,10 +5168,10 @@
unsigned UBytes = AVT.getSizeInBits() / 8;
unsigned CountVal = SizeVal / UBytes;
- SDOperand Count = DAG.getIntPtrConstant(CountVal);
+ SDValue Count = DAG.getIntPtrConstant(CountVal);
BytesLeft = SizeVal % UBytes;
- SDOperand InFlag(0, 0);
+ SDValue InFlag(0, 0);
Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
Count, InFlag);
InFlag = Chain.getValue(1);
@@ -5183,13 +5183,13 @@
InFlag = Chain.getValue(1);
SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
- SmallVector<SDOperand, 8> Ops;
+ SmallVector<SDValue, 8> Ops;
Ops.push_back(Chain);
Ops.push_back(DAG.getValueType(AVT));
Ops.push_back(InFlag);
- SDOperand RepMovs = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
+ SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
- SmallVector<SDOperand, 4> Results;
+ SmallVector<SDValue, 4> Results;
Results.push_back(RepMovs);
if (BytesLeft) {
// Handle the last 1 - 7 bytes.
@@ -5214,26 +5214,26 @@
/// Expand the result of: i64,outchain = READCYCLECOUNTER inchain
SDNode *X86TargetLowering::ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG){
SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
- SDOperand TheChain = N->getOperand(0);
- SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheChain, 1);
+ SDValue TheChain = N->getOperand(0);
+ SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheChain, 1);
if (Subtarget->is64Bit()) {
- SDOperand rax = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1));
- SDOperand rdx = DAG.getCopyFromReg(rax.getValue(1), X86::RDX,
+ SDValue rax = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1));
+ SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), X86::RDX,
MVT::i64, rax.getValue(2));
- SDOperand Tmp = DAG.getNode(ISD::SHL, MVT::i64, rdx,
+ SDValue Tmp = DAG.getNode(ISD::SHL, MVT::i64, rdx,
DAG.getConstant(32, MVT::i8));
- SDOperand Ops[] = {
+ SDValue Ops[] = {
DAG.getNode(ISD::OR, MVT::i64, rax, Tmp), rdx.getValue(1)
};
return DAG.getMergeValues(Ops, 2).Val;
}
- SDOperand eax = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1));
- SDOperand edx = DAG.getCopyFromReg(eax.getValue(1), X86::EDX,
+ SDValue eax = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1));
+ SDValue edx = DAG.getCopyFromReg(eax.getValue(1), X86::EDX,
MVT::i32, eax.getValue(2));
// Use a buildpair to merge the two 32-bit values into a 64-bit one.
- SDOperand Ops[] = { eax, edx };
+ SDValue Ops[] = { eax, edx };
Ops[0] = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Ops, 2);
// Use a MERGE_VALUES to return the value and chain.
@@ -5241,13 +5241,13 @@
return DAG.getMergeValues(Ops, 2).Val;
}
-SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) {
+SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
if (!Subtarget->is64Bit()) {
// vastart just stores the address of the VarArgsFrameIndex slot into the
// memory location argument.
- SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
+ SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV, 0);
}
@@ -5256,10 +5256,10 @@
// fp_offset (48 - 48 + 8 * 16)
// overflow_arg_area (point to parameters coming in memory).
// reg_save_area
- SmallVector<SDOperand, 8> MemOps;
- SDOperand FIN = Op.getOperand(1);
+ SmallVector<SDValue, 8> MemOps;
+ SDValue FIN = Op.getOperand(1);
// Store gp_offset
- SDOperand Store = DAG.getStore(Op.getOperand(0),
+ SDValue Store = DAG.getStore(Op.getOperand(0),
DAG.getConstant(VarArgsGPOffset, MVT::i32),
FIN, SV, 0);
MemOps.push_back(Store);
@@ -5273,36 +5273,36 @@
// Store ptr to overflow_arg_area
FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
- SDOperand OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
+ SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV, 0);
MemOps.push_back(Store);
// Store ptr to reg_save_area.
FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(8));
- SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
+ SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV, 0);
MemOps.push_back(Store);
return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size());
}
-SDOperand X86TargetLowering::LowerVAARG(SDOperand Op, SelectionDAG &DAG) {
+SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) {
// X86-64 va_list is a struct { i32, i32, i8*, i8* }.
assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
- SDOperand Chain = Op.getOperand(0);
- SDOperand SrcPtr = Op.getOperand(1);
- SDOperand SrcSV = Op.getOperand(2);
+ SDValue Chain = Op.getOperand(0);
+ SDValue SrcPtr = Op.getOperand(1);
+ SDValue SrcSV = Op.getOperand(2);
assert(0 && "VAArgInst is not yet implemented for x86-64!");
abort();
- return SDOperand();
+ return SDValue();
}
-SDOperand X86TargetLowering::LowerVACOPY(SDOperand Op, SelectionDAG &DAG) {
+SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
// X86-64 va_list is a struct { i32, i32, i8*, i8* }.
assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
- SDOperand Chain = Op.getOperand(0);
- SDOperand DstPtr = Op.getOperand(1);
- SDOperand SrcPtr = Op.getOperand(2);
+ SDValue Chain = Op.getOperand(0);
+ SDValue DstPtr = Op.getOperand(1);
+ SDValue SrcPtr = Op.getOperand(2);
const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
@@ -5311,11 +5311,11 @@
DstSV, 0, SrcSV, 0);
}
-SDOperand
-X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
+SDValue
+X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
switch (IntNo) {
- default: return SDOperand(); // Don't custom lower most intrinsics.
+ default: return SDValue(); // Don't custom lower most intrinsics.
// Comparison intrinsics.
case Intrinsic::x86_sse_comieq_ss:
case Intrinsic::x86_sse_comilt_ss:
@@ -5408,12 +5408,12 @@
}
unsigned X86CC;
- SDOperand LHS = Op.getOperand(1);
- SDOperand RHS = Op.getOperand(2);
+ SDValue LHS = Op.getOperand(1);
+ SDValue RHS = Op.getOperand(2);
translateX86CC(CC, true, X86CC, LHS, RHS, DAG);
- SDOperand Cond = DAG.getNode(Opc, MVT::i32, LHS, RHS);
- SDOperand SetCC = DAG.getNode(X86ISD::SETCC, MVT::i8,
+ SDValue Cond = DAG.getNode(Opc, MVT::i32, LHS, RHS);
+ SDValue SetCC = DAG.getNode(X86ISD::SETCC, MVT::i8,
DAG.getConstant(X86CC, MVT::i8), Cond);
return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC);
}
@@ -5436,9 +5436,9 @@
case Intrinsic::x86_mmx_psrli_q:
case Intrinsic::x86_mmx_psrai_w:
case Intrinsic::x86_mmx_psrai_d: {
- SDOperand ShAmt = Op.getOperand(2);
+ SDValue ShAmt = Op.getOperand(2);
if (isa<ConstantSDNode>(ShAmt))
- return SDOperand();
+ return SDValue();
unsigned NewIntNo = 0;
MVT ShAmtVT = MVT::v4i32;
@@ -5509,49 +5509,49 @@
}
}
-SDOperand X86TargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) {
+SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
// Depths > 0 not supported yet!
if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
- return SDOperand();
+ return SDValue();
// Just load the return address
- SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
+ SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
}
-SDOperand X86TargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) {
+SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
// Depths > 0 not supported yet!
if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
- return SDOperand();
+ return SDValue();
- SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
+ SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
return DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI,
DAG.getIntPtrConstant(!Subtarget->is64Bit() ? 4 : 8));
}
-SDOperand X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDOperand Op,
+SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
SelectionDAG &DAG) {
// Is not yet supported on x86-64
if (Subtarget->is64Bit())
- return SDOperand();
+ return SDValue();
return DAG.getIntPtrConstant(8);
}
-SDOperand X86TargetLowering::LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG)
+SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
{
assert(!Subtarget->is64Bit() &&
"Lowering of eh_return builtin is not supported yet on x86-64");
MachineFunction &MF = DAG.getMachineFunction();
- SDOperand Chain = Op.getOperand(0);
- SDOperand Offset = Op.getOperand(1);
- SDOperand Handler = Op.getOperand(2);
+ SDValue Chain = Op.getOperand(0);
+ SDValue Offset = Op.getOperand(1);
+ SDValue Handler = Op.getOperand(2);
- SDOperand Frame = DAG.getRegister(RegInfo->getFrameRegister(MF),
+ SDValue Frame = DAG.getRegister(RegInfo->getFrameRegister(MF),
getPointerTy());
- SDOperand StoreAddr = DAG.getNode(ISD::SUB, getPointerTy(), Frame,
+ SDValue StoreAddr = DAG.getNode(ISD::SUB, getPointerTy(), Frame,
DAG.getIntPtrConstant(-4UL));
StoreAddr = DAG.getNode(ISD::ADD, getPointerTy(), StoreAddr, Offset);
Chain = DAG.getStore(Chain, Handler, StoreAddr, NULL, 0);
@@ -5562,12 +5562,12 @@
Chain, DAG.getRegister(X86::ECX, getPointerTy()));
}
-SDOperand X86TargetLowering::LowerTRAMPOLINE(SDOperand Op,
+SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
SelectionDAG &DAG) {
- SDOperand Root = Op.getOperand(0);
- SDOperand Trmp = Op.getOperand(1); // trampoline
- SDOperand FPtr = Op.getOperand(2); // nested function
- SDOperand Nest = Op.getOperand(3); // 'nest' parameter value
+ SDValue Root = Op.getOperand(0);
+ SDValue Trmp = Op.getOperand(1); // trampoline
+ SDValue FPtr = Op.getOperand(2); // nested function
+ SDValue Nest = Op.getOperand(3); // 'nest' parameter value
const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
@@ -5575,7 +5575,7 @@
((X86TargetMachine&)getTargetMachine()).getInstrInfo();
if (Subtarget->is64Bit()) {
- SDOperand OutChains[6];
+ SDValue OutChains[6];
// Large code-model.
@@ -5589,7 +5589,7 @@
// Load the pointer to the nested function into R11.
unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
- SDOperand Addr = Trmp;
+ SDValue Addr = Trmp;
OutChains[0] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
TrmpAddr, 0);
@@ -5617,7 +5617,7 @@
OutChains[5] = DAG.getStore(Root, DAG.getConstant(ModRM, MVT::i8), Addr,
TrmpAddr, 22);
- SDOperand Ops[] =
+ SDValue Ops[] =
{ Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 6) };
return DAG.getMergeValues(Ops, 2);
} else {
@@ -5663,8 +5663,8 @@
break;
}
- SDOperand OutChains[4];
- SDOperand Addr, Disp;
+ SDValue OutChains[4];
+ SDValue Addr, Disp;
Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(10, MVT::i32));
Disp = DAG.getNode(ISD::SUB, MVT::i32, FPtr, Addr);
@@ -5685,13 +5685,13 @@
Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(6, MVT::i32));
OutChains[3] = DAG.getStore(Root, Disp, Addr, TrmpAddr, 6, false, 1);
- SDOperand Ops[] =
+ SDValue Ops[] =
{ Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 4) };
return DAG.getMergeValues(Ops, 2);
}
}
-SDOperand X86TargetLowering::LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG) {
+SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
/*
The rounding mode is in bits 11:10 of FPSR, and has the following
settings:
@@ -5719,27 +5719,27 @@
// Save FP Control Word to stack slot
int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment);
- SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
+ SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
- SDOperand Chain = DAG.getNode(X86ISD::FNSTCW16m, MVT::Other,
+ SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, MVT::Other,
DAG.getEntryNode(), StackSlot);
// Load FP Control Word from stack slot
- SDOperand CWD = DAG.getLoad(MVT::i16, Chain, StackSlot, NULL, 0);
+ SDValue CWD = DAG.getLoad(MVT::i16, Chain, StackSlot, NULL, 0);
// Transform as necessary
- SDOperand CWD1 =
+ SDValue CWD1 =
DAG.getNode(ISD::SRL, MVT::i16,
DAG.getNode(ISD::AND, MVT::i16,
CWD, DAG.getConstant(0x800, MVT::i16)),
DAG.getConstant(11, MVT::i8));
- SDOperand CWD2 =
+ SDValue CWD2 =
DAG.getNode(ISD::SRL, MVT::i16,
DAG.getNode(ISD::AND, MVT::i16,
CWD, DAG.getConstant(0x400, MVT::i16)),
DAG.getConstant(9, MVT::i8));
- SDOperand RetVal =
+ SDValue RetVal =
DAG.getNode(ISD::AND, MVT::i16,
DAG.getNode(ISD::ADD, MVT::i16,
DAG.getNode(ISD::OR, MVT::i16, CWD1, CWD2),
@@ -5751,7 +5751,7 @@
ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
}
-SDOperand X86TargetLowering::LowerCTLZ(SDOperand Op, SelectionDAG &DAG) {
+SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
MVT VT = Op.getValueType();
MVT OpVT = VT;
unsigned NumBits = VT.getSizeInBits();
@@ -5768,7 +5768,7 @@
Op = DAG.getNode(X86ISD::BSR, VTs, Op);
// If src is zero (i.e. bsr sets ZF), returns NumBits.
- SmallVector<SDOperand, 4> Ops;
+ SmallVector<SDValue, 4> Ops;
Ops.push_back(Op);
Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT));
Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
@@ -5783,7 +5783,7 @@
return Op;
}
-SDOperand X86TargetLowering::LowerCTTZ(SDOperand Op, SelectionDAG &DAG) {
+SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
MVT VT = Op.getValueType();
MVT OpVT = VT;
unsigned NumBits = VT.getSizeInBits();
@@ -5799,7 +5799,7 @@
Op = DAG.getNode(X86ISD::BSF, VTs, Op);
// If src is zero (i.e. bsf sets ZF), returns NumBits.
- SmallVector<SDOperand, 4> Ops;
+ SmallVector<SDValue, 4> Ops;
Ops.push_back(Op);
Ops.push_back(DAG.getConstant(NumBits, OpVT));
Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
@@ -5811,7 +5811,7 @@
return Op;
}
-SDOperand X86TargetLowering::LowerCMP_SWAP(SDOperand Op, SelectionDAG &DAG) {
+SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
MVT T = Op.getValueType();
unsigned Reg = 0;
unsigned size = 0;
@@ -5825,19 +5825,19 @@
if (Subtarget->is64Bit()) {
Reg = X86::RAX; size = 8;
} else //Should go away when LowerType stuff lands
- return SDOperand(ExpandATOMIC_CMP_SWAP(Op.Val, DAG), 0);
+ return SDValue(ExpandATOMIC_CMP_SWAP(Op.Val, DAG), 0);
break;
};
- SDOperand cpIn = DAG.getCopyToReg(Op.getOperand(0), Reg,
- Op.getOperand(3), SDOperand());
- SDOperand Ops[] = { cpIn.getValue(0),
+ SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), Reg,
+ Op.getOperand(3), SDValue());
+ SDValue Ops[] = { cpIn.getValue(0),
Op.getOperand(1),
Op.getOperand(2),
DAG.getTargetConstant(size, MVT::i8),
cpIn.getValue(1) };
SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
- SDOperand Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, Tys, Ops, 5);
- SDOperand cpOut =
+ SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, Tys, Ops, 5);
+ SDValue cpOut =
DAG.getCopyFromReg(Result.getValue(0), Reg, T, Result.getValue(1));
return cpOut;
}
@@ -5845,16 +5845,16 @@
SDNode* X86TargetLowering::ExpandATOMIC_CMP_SWAP(SDNode* Op, SelectionDAG &DAG) {
MVT T = Op->getValueType(0);
assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
- SDOperand cpInL, cpInH;
+ SDValue cpInL, cpInH;
cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(3),
DAG.getConstant(0, MVT::i32));
cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(3),
DAG.getConstant(1, MVT::i32));
cpInL = DAG.getCopyToReg(Op->getOperand(0), X86::EAX,
- cpInL, SDOperand());
+ cpInL, SDValue());
cpInH = DAG.getCopyToReg(cpInL.getValue(0), X86::EDX,
cpInH, cpInL.getValue(1));
- SDOperand swapInL, swapInH;
+ SDValue swapInL, swapInH;
swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(2),
DAG.getConstant(0, MVT::i32));
swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(2),
@@ -5863,25 +5863,25 @@
swapInL, cpInH.getValue(1));
swapInH = DAG.getCopyToReg(swapInL.getValue(0), X86::ECX,
swapInH, swapInL.getValue(1));
- SDOperand Ops[] = { swapInH.getValue(0),
+ SDValue Ops[] = { swapInH.getValue(0),
Op->getOperand(1),
swapInH.getValue(1)};
SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
- SDOperand Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, Tys, Ops, 3);
- SDOperand cpOutL = DAG.getCopyFromReg(Result.getValue(0), X86::EAX, MVT::i32,
+ SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, Tys, Ops, 3);
+ SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), X86::EAX, MVT::i32,
Result.getValue(1));
- SDOperand cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), X86::EDX, MVT::i32,
+ SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), X86::EDX, MVT::i32,
cpOutL.getValue(2));
- SDOperand OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
- SDOperand ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2);
- SDOperand Vals[2] = { ResultVal, cpOutH.getValue(1) };
+ SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
+ SDValue ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2);
+ SDValue Vals[2] = { ResultVal, cpOutH.getValue(1) };
return DAG.getMergeValues(Vals, 2).Val;
}
SDNode* X86TargetLowering::ExpandATOMIC_LOAD_SUB(SDNode* Op, SelectionDAG &DAG) {
MVT T = Op->getValueType(0);
assert (T == MVT::i32 && "Only know how to expand i32 Atomic Load Sub");
- SDOperand negOp = DAG.getNode(ISD::SUB, T,
+ SDValue negOp = DAG.getNode(ISD::SUB, T,
DAG.getConstant(0, T), Op->getOperand(2));
return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, Op->getOperand(0),
Op->getOperand(1), negOp,
@@ -5891,7 +5891,7 @@
/// LowerOperation - Provide custom lowering hooks for some operations.
///
-SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
+SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
switch (Op.getOpcode()) {
default: assert(0 && "Should not custom lower this!");
case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
@@ -5937,7 +5937,7 @@
// FIXME: REMOVE THIS WHEN LegalizeDAGTypes lands.
case ISD::READCYCLECOUNTER:
- return SDOperand(ExpandREADCYCLECOUNTER(Op.Val, DAG), 0);
+ return SDValue(ExpandREADCYCLECOUNTER(Op.Val, DAG), 0);
}
}
@@ -6092,7 +6092,7 @@
/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
/// are assumed to be legal.
bool
-X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT VT) const {
+X86TargetLowering::isShuffleMaskLegal(SDValue Mask, MVT VT) const {
// Only do shuffles on 128-bit vector types for now.
if (VT.getSizeInBits() == 64) return false;
return (Mask.Val->getNumOperands() <= 4 ||
@@ -6107,7 +6107,7 @@
}
bool
-X86TargetLowering::isVectorClearMaskLegal(const std::vector<SDOperand> &BVOps,
+X86TargetLowering::isVectorClearMaskLegal(const std::vector<SDValue> &BVOps,
MVT EVT, SelectionDAG &DAG) const {
unsigned NumElts = BVOps.size();
// Only do shuffles on 128-bit vector types for now.
@@ -6484,7 +6484,7 @@
// X86 Optimization Hooks
//===----------------------------------------------------------------------===//
-void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
+void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
const APInt &Mask,
APInt &KnownZero,
APInt &KnownOne,
@@ -6531,21 +6531,21 @@
return false;
}
-static bool EltsFromConsecutiveLoads(SDNode *N, SDOperand PermMask,
+static bool EltsFromConsecutiveLoads(SDNode *N, SDValue PermMask,
unsigned NumElems, MVT EVT,
SDNode *&Base,
SelectionDAG &DAG, MachineFrameInfo *MFI,
const TargetLowering &TLI) {
Base = NULL;
for (unsigned i = 0; i < NumElems; ++i) {
- SDOperand Idx = PermMask.getOperand(i);
+ SDValue Idx = PermMask.getOperand(i);
if (Idx.getOpcode() == ISD::UNDEF) {
if (!Base)
return false;
continue;
}
- SDOperand Elt = DAG.getShuffleScalarElt(N, i);
+ SDValue Elt = DAG.getShuffleScalarElt(N, i);
if (!Elt.Val ||
(Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.Val)))
return false;
@@ -6569,17 +6569,17 @@
/// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
/// if the load addresses are consecutive, non-overlapping, and in the right
/// order.
-static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
+static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
const TargetLowering &TLI) {
MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
MVT VT = N->getValueType(0);
MVT EVT = VT.getVectorElementType();
- SDOperand PermMask = N->getOperand(2);
+ SDValue PermMask = N->getOperand(2);
unsigned NumElems = PermMask.getNumOperands();
SDNode *Base = NULL;
if (!EltsFromConsecutiveLoads(N, PermMask, NumElems, EVT, Base,
DAG, MFI, TLI))
- return SDOperand();
+ return SDValue();
LoadSDNode *LD = cast<LoadSDNode>(Base);
if (isBaseAlignmentOfN(16, Base->getOperand(1).Val, TLI))
@@ -6591,14 +6591,14 @@
}
/// PerformBuildVectorCombine - build_vector 0,(load i64 / f64) -> movq / movsd.
-static SDOperand PerformBuildVectorCombine(SDNode *N, SelectionDAG &DAG,
+static SDValue PerformBuildVectorCombine(SDNode *N, SelectionDAG &DAG,
const X86Subtarget *Subtarget,
const TargetLowering &TLI) {
unsigned NumOps = N->getNumOperands();
// Ignore single operand BUILD_VECTOR.
if (NumOps == 1)
- return SDOperand();
+ return SDValue();
MVT VT = N->getValueType(0);
MVT EVT = VT.getVectorElementType();
@@ -6606,20 +6606,20 @@
// We are looking for load i64 and zero extend. We want to transform
// it before legalizer has a chance to expand it. Also look for i64
// BUILD_PAIR bit casted to f64.
- return SDOperand();
+ return SDValue();
// This must be an insertion into a zero vector.
- SDOperand HighElt = N->getOperand(1);
+ SDValue HighElt = N->getOperand(1);
if (!isZeroNode(HighElt))
- return SDOperand();
+ return SDValue();
// Value must be a load.
SDNode *Base = N->getOperand(0).Val;
if (!isa<LoadSDNode>(Base)) {
if (Base->getOpcode() != ISD::BIT_CONVERT)
- return SDOperand();
+ return SDValue();
Base = Base->getOperand(0).Val;
if (!isa<LoadSDNode>(Base))
- return SDOperand();
+ return SDValue();
}
// Transform it into VZEXT_LOAD addr.
@@ -6627,23 +6627,23 @@
// Load must not be an extload.
if (LD->getExtensionType() != ISD::NON_EXTLOAD)
- return SDOperand();
+ return SDValue();
return DAG.getNode(X86ISD::VZEXT_LOAD, VT, LD->getChain(), LD->getBasePtr());
}
/// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
-static SDOperand PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
+static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
const X86Subtarget *Subtarget) {
- SDOperand Cond = N->getOperand(0);
+ SDValue Cond = N->getOperand(0);
// If we have SSE[12] support, try to form min/max nodes.
if (Subtarget->hasSSE2() &&
(N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) {
if (Cond.getOpcode() == ISD::SETCC) {
// Get the LHS/RHS of the select.
- SDOperand LHS = N->getOperand(1);
- SDOperand RHS = N->getOperand(2);
+ SDValue LHS = N->getOperand(1);
+ SDValue RHS = N->getOperand(2);
ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
unsigned Opcode = 0;
@@ -6701,11 +6701,11 @@
}
- return SDOperand();
+ return SDValue();
}
/// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
-static SDOperand PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
+static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
const X86Subtarget *Subtarget) {
// Turn load->store of MMX types into GPR load/stores. This avoids clobbering
// the FP state in cases where an emms may be missing.
@@ -6720,7 +6720,7 @@
SDNode* LdVal = St->getValue().Val;
LoadSDNode *Ld = 0;
int TokenFactorIndex = -1;
- SmallVector<SDOperand, 8> Ops;
+ SmallVector<SDValue, 8> Ops;
SDNode* ChainVal = St->getChain().Val;
// Must be a store of a load. We currently handle two cases: the load
// is a direct child, and it's under an intervening TokenFactor. It is
@@ -6740,11 +6740,11 @@
if (Ld) {
// If we are a 64-bit capable x86, lower to a single movq load/store pair.
if (Subtarget->is64Bit()) {
- SDOperand NewLd = DAG.getLoad(MVT::i64, Ld->getChain(),
+ SDValue NewLd = DAG.getLoad(MVT::i64, Ld->getChain(),
Ld->getBasePtr(), Ld->getSrcValue(),
Ld->getSrcValueOffset(), Ld->isVolatile(),
Ld->getAlignment());
- SDOperand NewChain = NewLd.getValue(1);
+ SDValue NewChain = NewLd.getValue(1);
if (TokenFactorIndex != -1) {
Ops.push_back(NewChain);
NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0],
@@ -6756,19 +6756,19 @@
}
// Otherwise, lower to two 32-bit copies.
- SDOperand LoAddr = Ld->getBasePtr();
- SDOperand HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr,
+ SDValue LoAddr = Ld->getBasePtr();
+ SDValue HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr,
DAG.getConstant(4, MVT::i32));
- SDOperand LoLd = DAG.getLoad(MVT::i32, Ld->getChain(), LoAddr,
+ SDValue LoLd = DAG.getLoad(MVT::i32, Ld->getChain(), LoAddr,
Ld->getSrcValue(), Ld->getSrcValueOffset(),
Ld->isVolatile(), Ld->getAlignment());
- SDOperand HiLd = DAG.getLoad(MVT::i32, Ld->getChain(), HiAddr,
+ SDValue HiLd = DAG.getLoad(MVT::i32, Ld->getChain(), HiAddr,
Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
Ld->isVolatile(),
MinAlign(Ld->getAlignment(), 4));
- SDOperand NewChain = LoLd.getValue(1);
+ SDValue NewChain = LoLd.getValue(1);
if (TokenFactorIndex != -1) {
Ops.push_back(LoLd);
Ops.push_back(HiLd);
@@ -6780,22 +6780,22 @@
HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr,
DAG.getConstant(4, MVT::i32));
- SDOperand LoSt = DAG.getStore(NewChain, LoLd, LoAddr,
+ SDValue LoSt = DAG.getStore(NewChain, LoLd, LoAddr,
St->getSrcValue(), St->getSrcValueOffset(),
St->isVolatile(), St->getAlignment());
- SDOperand HiSt = DAG.getStore(NewChain, HiLd, HiAddr,
+ SDValue HiSt = DAG.getStore(NewChain, HiLd, HiAddr,
St->getSrcValue(), St->getSrcValueOffset()+4,
St->isVolatile(),
MinAlign(St->getAlignment(), 4));
return DAG.getNode(ISD::TokenFactor, MVT::Other, LoSt, HiSt);
}
}
- return SDOperand();
+ return SDValue();
}
/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
/// X86ISD::FXOR nodes.
-static SDOperand PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
+static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
// F[X]OR(0.0, x) -> x
// F[X]OR(x, 0.0) -> x
@@ -6805,11 +6805,11 @@
if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
if (C->getValueAPF().isPosZero())
return N->getOperand(0);
- return SDOperand();
+ return SDValue();
}
/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
-static SDOperand PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
+static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
// FAND(0.0, x) -> 0.0
// FAND(x, 0.0) -> 0.0
if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
@@ -6818,11 +6818,11 @@
if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
if (C->getValueAPF().isPosZero())
return N->getOperand(1);
- return SDOperand();
+ return SDValue();
}
-SDOperand X86TargetLowering::PerformDAGCombine(SDNode *N,
+SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
DAGCombinerInfo &DCI) const {
SelectionDAG &DAG = DCI.DAG;
switch (N->getOpcode()) {
@@ -6837,7 +6837,7 @@
case X86ISD::FAND: return PerformFANDCombine(N, DAG);
}
- return SDOperand();
+ return SDValue();
}
//===----------------------------------------------------------------------===//
@@ -6887,11 +6887,11 @@
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
/// vector. If it is invalid, don't add anything to Ops.
-void X86TargetLowering::LowerAsmOperandForConstraint(SDOperand Op,
+void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
char Constraint,
- std::vector<SDOperand>&Ops,
+ std::vector<SDValue>&Ops,
SelectionDAG &DAG) const {
- SDOperand Result(0, 0);
+ SDValue Result(0, 0);
switch (Constraint) {
default: break;
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Sun Jul 27 16:46:04 2008
@@ -325,7 +325,7 @@
/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
/// jumptable.
- SDOperand getPICJumpTableRelocBase(SDOperand Table,
+ SDValue getPICJumpTableRelocBase(SDValue Table,
SelectionDAG &DAG) const;
// Return the number of bytes that a function should pop when it returns (in
@@ -357,7 +357,7 @@
/// LowerOperation - Provide custom lowering hooks for some operations.
///
- virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
+ virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
/// ReplaceNodeResults - Replace a node with an illegal result type
/// with a new node built out of custom code.
@@ -365,7 +365,7 @@
virtual SDNode *ReplaceNodeResults(SDNode *N, SelectionDAG &DAG);
- virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
+ virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *MBB);
@@ -376,12 +376,12 @@
virtual const char *getTargetNodeName(unsigned Opcode) const;
/// getSetCCResultType - Return the ISD::SETCC ValueType
- virtual MVT getSetCCResultType(const SDOperand &) const;
+ virtual MVT getSetCCResultType(const SDValue &) const;
/// computeMaskedBitsForTargetNode - Determine which of the bits specified
/// in Mask are known to be either zero or one and return them in the
/// KnownZero/KnownOne bitsets.
- virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
+ virtual void computeMaskedBitsForTargetNode(const SDValue Op,
const APInt &Mask,
APInt &KnownZero,
APInt &KnownOne,
@@ -391,7 +391,7 @@
virtual bool
isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const;
- SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
+ SDValue getReturnAddressFrameIndex(SelectionDAG &DAG);
ConstraintType getConstraintType(const std::string &Constraint) const;
@@ -403,9 +403,9 @@
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
/// vector. If it is invalid, don't add anything to Ops.
- virtual void LowerAsmOperandForConstraint(SDOperand Op,
+ virtual void LowerAsmOperandForConstraint(SDValue Op,
char ConstraintLetter,
- std::vector<SDOperand> &Ops,
+ std::vector<SDValue> &Ops,
SelectionDAG &DAG) const;
/// getRegForInlineAsmConstraint - Given a physical register constraint
@@ -430,13 +430,13 @@
/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
/// By default, if a target supports the VECTOR_SHUFFLE node, all mask
/// values are assumed to be legal.
- virtual bool isShuffleMaskLegal(SDOperand Mask, MVT VT) const;
+ virtual bool isShuffleMaskLegal(SDValue Mask, MVT VT) const;
/// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
/// used by Targets can use this to indicate if there is a suitable
/// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
/// pool entry.
- virtual bool isVectorClearMaskLegal(const std::vector<SDOperand> &BVOps,
+ virtual bool isVectorClearMaskLegal(const std::vector<SDValue> &BVOps,
MVT EVT, SelectionDAG &DAG) const;
/// ShouldShrinkFPConstant - If true, then instruction selection should
@@ -452,8 +452,8 @@
/// IsEligibleForTailCallOptimization - Check whether the call is eligible
/// for tail call optimization. Target which want to do tail call
/// optimization should implement this function.
- virtual bool IsEligibleForTailCallOptimization(SDOperand Call,
- SDOperand Ret,
+ virtual bool IsEligibleForTailCallOptimization(SDValue Call,
+ SDValue Ret,
SelectionDAG &DAG) const;
virtual const X86Subtarget* getSubtarget() {
@@ -483,87 +483,87 @@
bool X86ScalarSSEf32;
bool X86ScalarSSEf64;
- SDNode *LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode*TheCall,
+ SDNode *LowerCallResult(SDValue Chain, SDValue InFlag, SDNode*TheCall,
unsigned CallingConv, SelectionDAG &DAG);
- SDOperand LowerMemArgument(SDOperand Op, SelectionDAG &DAG,
+ SDValue LowerMemArgument(SDValue Op, SelectionDAG &DAG,
const CCValAssign &VA, MachineFrameInfo *MFI,
- unsigned CC, SDOperand Root, unsigned i);
+ unsigned CC, SDValue Root, unsigned i);
- SDOperand LowerMemOpCallTo(SDOperand Op, SelectionDAG &DAG,
- const SDOperand &StackPtr,
- const CCValAssign &VA, SDOperand Chain,
- SDOperand Arg);
+ SDValue LowerMemOpCallTo(SDValue Op, SelectionDAG &DAG,
+ const SDValue &StackPtr,
+ const CCValAssign &VA, SDValue Chain,
+ SDValue Arg);
// Call lowering helpers.
- bool IsCalleePop(SDOperand Op);
+ bool IsCalleePop(SDValue Op);
bool CallRequiresGOTPtrInReg(bool Is64Bit, bool IsTailCall);
bool CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall);
- SDOperand EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDOperand &OutRetAddr,
- SDOperand Chain, bool IsTailCall, bool Is64Bit,
+ SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
+ SDValue Chain, bool IsTailCall, bool Is64Bit,
int FPDiff);
- CCAssignFn *CCAssignFnForNode(SDOperand Op) const;
- NameDecorationStyle NameDecorationForFORMAL_ARGUMENTS(SDOperand Op);
+ CCAssignFn *CCAssignFnForNode(SDValue Op) const;
+ NameDecorationStyle NameDecorationForFORMAL_ARGUMENTS(SDValue Op);
unsigned GetAlignedArgumentStackSize(unsigned StackSize, SelectionDAG &DAG);
- std::pair<SDOperand,SDOperand> FP_TO_SINTHelper(SDOperand Op,
+ std::pair<SDValue,SDValue> FP_TO_SINTHelper(SDValue Op,
SelectionDAG &DAG);
- SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerEXTRACT_VECTOR_ELT_SSE4(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerINSERT_VECTOR_ELT_SSE4(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerShift(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerFABS(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerFNEG(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerVSETCC(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerSELECT(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerBRCOND(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerMEMSET(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerVACOPY(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerFRAME_TO_ARGS_OFFSET(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerTRAMPOLINE(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerCTLZ(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerCTTZ(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerCMP_SWAP(SDOperand Op, SelectionDAG &DAG);
+ SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerShift(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerFABS(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerCALL(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerRET(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG);
SDNode *ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG);
SDNode *ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG);
SDNode *ExpandATOMIC_CMP_SWAP(SDNode *N, SelectionDAG &DAG);
SDNode *ExpandATOMIC_LOAD_SUB(SDNode *N, SelectionDAG &DAG);
- SDOperand EmitTargetCodeForMemset(SelectionDAG &DAG,
- SDOperand Chain,
- SDOperand Dst, SDOperand Src,
- SDOperand Size, unsigned Align,
+ SDValue EmitTargetCodeForMemset(SelectionDAG &DAG,
+ SDValue Chain,
+ SDValue Dst, SDValue Src,
+ SDValue Size, unsigned Align,
const Value *DstSV, uint64_t DstSVOff);
- SDOperand EmitTargetCodeForMemcpy(SelectionDAG &DAG,
- SDOperand Chain,
- SDOperand Dst, SDOperand Src,
- SDOperand Size, unsigned Align,
+ SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG,
+ SDValue Chain,
+ SDValue Dst, SDValue Src,
+ SDValue Size, unsigned Align,
bool AlwaysInline,
const Value *DstSV, uint64_t DstSVOff,
const Value *SrcSV, uint64_t SrcSVOff);
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Sun Jul 27 16:46:04 2008
@@ -2262,12 +2262,12 @@
const TargetOperandInfo &TOI = TID.OpInfo[Index];
const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
- std::vector<SDOperand> AddrOps;
- std::vector<SDOperand> BeforeOps;
- std::vector<SDOperand> AfterOps;
+ std::vector<SDValue> AddrOps;
+ std::vector<SDValue> BeforeOps;
+ std::vector<SDValue> AfterOps;
unsigned NumOps = N->getNumOperands();
for (unsigned i = 0; i != NumOps-1; ++i) {
- SDOperand Op = N->getOperand(i);
+ SDValue Op = N->getOperand(i);
if (i >= Index && i < Index+4)
AddrOps.push_back(Op);
else if (i < Index)
@@ -2275,7 +2275,7 @@
else if (i > Index)
AfterOps.push_back(Op);
}
- SDOperand Chain = N->getOperand(NumOps-1);
+ SDValue Chain = N->getOperand(NumOps-1);
AddrOps.push_back(Chain);
// Emit the load instruction.
@@ -2306,7 +2306,7 @@
VTs.push_back(VT);
}
if (Load)
- BeforeOps.push_back(SDOperand(Load, 0));
+ BeforeOps.push_back(SDValue(Load, 0));
std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
SDNode *NewNode= DAG.getTargetNode(Opc, VTs, &BeforeOps[0], BeforeOps.size());
NewNodes.push_back(NewNode);
@@ -2314,7 +2314,7 @@
// Emit the store instruction.
if (FoldedStore) {
AddrOps.pop_back();
- AddrOps.push_back(SDOperand(NewNode, 0));
+ AddrOps.push_back(SDValue(NewNode, 0));
AddrOps.push_back(Chain);
bool isAligned = (RI.getStackAlignment() >= 16) ||
RI.needsStackRealignment(MF);
Modified: llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp Sun Jul 27 16:46:04 2008
@@ -963,7 +963,7 @@
}
// Compute the constraint code and ConstraintType to use.
- TLI->ComputeConstraintToUse(OpInfo, SDOperand());
+ TLI->ComputeConstraintToUse(OpInfo, SDValue());
if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
OpInfo.isIndirect) {
Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=54128&r1=54127&r2=54128&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Sun Jul 27 16:46:04 2008
@@ -254,7 +254,7 @@
std::string ClassName = CGP.getSDNodeInfo(SDNode).getSDClassName();
const char *C2 = ClassName == "SDNode" ? "N" : "inN";
- OS << "inline SDOperand Transform_" << I->first << "(SDNode *" << C2
+ OS << "inline SDValue Transform_" << I->first << "(SDNode *" << C2
<< ") {\n";
if (ClassName != "SDNode")
OS << " " << ClassName << " *N = cast<" << ClassName << ">(inN);\n";
@@ -347,7 +347,7 @@
/// tested, and if true, the match fails) [when 1], or normal code to emit
/// [when 0], or initialization code to emit [when 2].
std::vector<std::pair<unsigned, std::string> > &GeneratedCode;
- /// GeneratedDecl - This is the set of all SDOperand declarations needed for
+ /// GeneratedDecl - This is the set of all SDValue declarations needed for
/// the set of patterns for each top-level opcode.
std::set<std::string> &GeneratedDecl;
/// TargetOpcodes - The target specific opcodes used by the resulting
@@ -536,7 +536,7 @@
} else
FoundChain = true;
ChainName = "Chain" + ChainSuffix;
- emitInit("SDOperand " + ChainName + " = " + RootName +
+ emitInit("SDValue " + ChainName + " = " + RootName +
".getOperand(0);");
}
}
@@ -578,9 +578,9 @@
N->getChild(1)->getPredicateFn().empty()) {
if (IntInit *II = dynamic_cast<IntInit*>(N->getChild(1)->getLeafValue())) {
if (!isPowerOf2_32(II->getValue())) { // Don't bother with single bits.
- emitInit("SDOperand " + RootName + "0" + " = " +
+ emitInit("SDValue " + RootName + "0" + " = " +
RootName + ".getOperand(" + utostr(0) + ");");
- emitInit("SDOperand " + RootName + "1" + " = " +
+ emitInit("SDValue " + RootName + "1" + " = " +
RootName + ".getOperand(" + utostr(1) + ");");
emitCheck("isa<ConstantSDNode>(" + RootName + "1)");
@@ -597,7 +597,7 @@
}
for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i, ++OpNo) {
- emitInit("SDOperand " + RootName + utostr(OpNo) + " = " +
+ emitInit("SDValue " + RootName + utostr(OpNo) + " = " +
RootName + ".getOperand(" +utostr(OpNo) + ");");
EmitChildMatchCode(N->getChild(i), N, RootName + utostr(OpNo), RootName,
@@ -611,13 +611,13 @@
unsigned NumOps = CP->getNumOperands();
for (unsigned i = 0; i < NumOps; ++i) {
emitDecl("CPTmp" + utostr(i));
- emitCode("SDOperand CPTmp" + utostr(i) + ";");
+ emitCode("SDValue CPTmp" + utostr(i) + ";");
}
if (CP->hasProperty(SDNPHasChain)) {
emitDecl("CPInChain");
emitDecl("Chain" + ChainSuffix);
- emitCode("SDOperand CPInChain;");
- emitCode("SDOperand Chain" + ChainSuffix + ";");
+ emitCode("SDValue CPInChain;");
+ emitCode("SDValue Chain" + ChainSuffix + ";");
}
std::string Code = Fn + "(" + RootName + ", " + RootName;
@@ -685,7 +685,7 @@
unsigned NumOps = CP->getNumOperands();
for (unsigned i = 0; i < NumOps; ++i) {
emitDecl("CPTmp" + utostr(i));
- emitCode("SDOperand CPTmp" + utostr(i) + ";");
+ emitCode("SDValue CPTmp" + utostr(i) + ";");
}
if (CP->hasProperty(SDNPHasChain)) {
const SDNodeInfo &PInfo = CGP.getSDNodeInfo(Parent->getOperator());
@@ -694,8 +694,8 @@
ChainName = "Chain" + ChainSuffix;
emitDecl("CPInChain");
emitDecl(ChainName);
- emitCode("SDOperand CPInChain;");
- emitCode("SDOperand " + ChainName + ";");
+ emitCode("SDValue CPInChain;");
+ emitCode("SDValue " + ChainName + ";");
}
std::string Code = Fn + "(";
@@ -794,7 +794,7 @@
case MVT::i32: CastType = "unsigned"; break;
case MVT::i64: CastType = "uint64_t"; break;
}
- emitCode("SDOperand " + TmpVar +
+ emitCode("SDValue " + TmpVar +
" = CurDAG->getTargetConstant(((" + CastType +
") cast<ConstantSDNode>(" + Val + ")->getValue()), " +
getEnumName(N->getTypeNum(0)) + ");");
@@ -806,7 +806,7 @@
} else if (!N->isLeaf() && N->getOperator()->getName() == "fpimm") {
assert(N->getExtTypes().size() == 1 && "Multiple types not handled!");
std::string TmpVar = "Tmp" + utostr(ResNo);
- emitCode("SDOperand " + TmpVar +
+ emitCode("SDValue " + TmpVar +
" = CurDAG->getTargetConstantFP(cast<ConstantFPSDNode>(" +
Val + ")->getValueAPF(), cast<ConstantFPSDNode>(" + Val +
")->getValueType(0));");
@@ -820,7 +820,7 @@
// Transform ExternalSymbol to TargetExternalSymbol
if (Op && Op->getName() == "externalsym") {
std::string TmpVar = "Tmp"+utostr(ResNo);
- emitCode("SDOperand " + TmpVar + " = CurDAG->getTarget"
+ emitCode("SDValue " + TmpVar + " = CurDAG->getTarget"
"ExternalSymbol(cast<ExternalSymbolSDNode>(" +
Val + ")->getSymbol(), " +
getEnumName(N->getTypeNum(0)) + ");");
@@ -837,7 +837,7 @@
if (Op && (Op->getName() == "globaladdr" ||
Op->getName() == "globaltlsaddr")) {
std::string TmpVar = "Tmp" + utostr(ResNo);
- emitCode("SDOperand " + TmpVar + " = CurDAG->getTarget"
+ emitCode("SDValue " + TmpVar + " = CurDAG->getTarget"
"GlobalAddress(cast<GlobalAddressSDNode>(" + Val +
")->getGlobal(), " + getEnumName(N->getTypeNum(0)) +
");");
@@ -881,13 +881,13 @@
if (DefInit *DI = dynamic_cast<DefInit*>(N->getLeafValue())) {
unsigned ResNo = TmpNo++;
if (DI->getDef()->isSubClassOf("Register")) {
- emitCode("SDOperand Tmp" + utostr(ResNo) + " = CurDAG->getRegister(" +
+ emitCode("SDValue Tmp" + utostr(ResNo) + " = CurDAG->getRegister(" +
getQualifiedName(DI->getDef()) + ", " +
getEnumName(N->getTypeNum(0)) + ");");
NodeOps.push_back("Tmp" + utostr(ResNo));
return NodeOps;
} else if (DI->getDef()->getName() == "zero_reg") {
- emitCode("SDOperand Tmp" + utostr(ResNo) +
+ emitCode("SDValue Tmp" + utostr(ResNo) +
" = CurDAG->getRegister(0, " +
getEnumName(N->getTypeNum(0)) + ");");
NodeOps.push_back("Tmp" + utostr(ResNo));
@@ -896,7 +896,7 @@
} else if (IntInit *II = dynamic_cast<IntInit*>(N->getLeafValue())) {
unsigned ResNo = TmpNo++;
assert(N->getExtTypes().size() == 1 && "Multiple types not handled!");
- emitCode("SDOperand Tmp" + utostr(ResNo) +
+ emitCode("SDValue Tmp" + utostr(ResNo) +
" = CurDAG->getTargetConstant(0x" + itohexstr(II->getValue()) +
"ULL, " + getEnumName(N->getTypeNum(0)) + ");");
NodeOps.push_back("Tmp" + utostr(ResNo));
@@ -948,7 +948,7 @@
"(N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);");
}
if (IsVariadic)
- emitCode("SmallVector<SDOperand, 8> Ops" + utostr(OpcNo) + ";");
+ emitCode("SmallVector<SDValue, 8> Ops" + utostr(OpcNo) + ";");
// How many results is this pattern expected to produce?
unsigned NumPatResults = 0;
@@ -964,7 +964,7 @@
// TokenFactor with it and the chain of the folded op as the new chain.
// We could potentially be doing multiple levels of folding, in that
// case, the TokenFactor can have more operands.
- emitCode("SmallVector<SDOperand, 8> InChains;");
+ emitCode("SmallVector<SDValue, 8> InChains;");
for (unsigned i = 0, e = OrigChains.size(); i < e; ++i) {
emitCode("if (" + OrigChains[i].first + ".Val != " +
OrigChains[i].second + ".Val) {");
@@ -1022,7 +1022,7 @@
InFlagDecled, ResNodeDecled, true);
if (NodeHasOptInFlag || NodeHasInFlag || HasImpInputs) {
if (!InFlagDecled) {
- emitCode("SDOperand InFlag(0, 0);");
+ emitCode("SDValue InFlag(0, 0);");
InFlagDecled = true;
}
if (NodeHasOptInFlag) {
@@ -1042,7 +1042,7 @@
std::string NodeName;
if (!isRoot) {
NodeName = "Tmp" + utostr(ResNo);
- CodePrefix = "SDOperand " + NodeName + "(";
+ CodePrefix = "SDValue " + NodeName + "(";
} else {
NodeName = "ResNode";
if (!ResNodeDecled) {
@@ -1103,7 +1103,7 @@
if (II.isSimpleLoad | II.mayLoad | II.mayStore) {
std::vector<std::string>::const_iterator mi, mie;
for (mi = LSI.begin(), mie = LSI.end(); mi != mie; ++mi) {
- emitCode("SDOperand LSI_" + *mi + " = "
+ emitCode("SDValue LSI_" + *mi + " = "
"CurDAG->getMemOperand(cast<MemSDNode>(" +
*mi + ")->getMemOperand());");
if (IsVariadic)
@@ -1138,7 +1138,7 @@
for (unsigned i = 0; i != NumOps; ++i)
Code += ", " + AllOps[i];
} else {
- std::string OpsCode = "SDOperand Ops" + utostr(OpsNo) + "[] = { ";
+ std::string OpsCode = "SDValue Ops" + utostr(OpsNo) + "[] = { ";
for (unsigned i = 0; i != NumOps; ++i) {
OpsCode += AllOps[i];
if (i != NumOps-1)
@@ -1165,12 +1165,12 @@
if (NodeHasOutFlag) {
if (!InFlagDecled) {
- After.push_back("SDOperand InFlag(ResNode, " +
+ After.push_back("SDValue InFlag(ResNode, " +
utostr(NumResults+NumDstRegs+(unsigned)NodeHasChain) +
");");
InFlagDecled = true;
} else
- After.push_back("InFlag = SDOperand(ResNode, " +
+ After.push_back("InFlag = SDValue(ResNode, " +
utostr(NumResults+NumDstRegs+(unsigned)NodeHasChain) +
");");
}
@@ -1178,23 +1178,23 @@
if (FoldedChains.size() > 0) {
std::string Code;
for (unsigned j = 0, e = FoldedChains.size(); j < e; j++) {
- ReplaceFroms.push_back("SDOperand(" +
+ ReplaceFroms.push_back("SDValue(" +
FoldedChains[j].first + ".Val, " +
utostr(FoldedChains[j].second) +
")");
- ReplaceTos.push_back("SDOperand(ResNode, " +
+ ReplaceTos.push_back("SDValue(ResNode, " +
utostr(NumResults+NumDstRegs) + ")");
}
}
if (NodeHasOutFlag) {
if (FoldedFlag.first != "") {
- ReplaceFroms.push_back("SDOperand(" + FoldedFlag.first + ".Val, " +
+ ReplaceFroms.push_back("SDValue(" + FoldedFlag.first + ".Val, " +
utostr(FoldedFlag.second) + ")");
ReplaceTos.push_back("InFlag");
} else {
assert(NodeHasProperty(Pattern, SDNPOutFlag, CGP));
- ReplaceFroms.push_back("SDOperand(N.Val, " +
+ ReplaceFroms.push_back("SDValue(N.Val, " +
utostr(NumPatResults + (unsigned)InputHasChain)
+ ")");
ReplaceTos.push_back("InFlag");
@@ -1202,9 +1202,9 @@
}
if (!ReplaceFroms.empty() && InputHasChain) {
- ReplaceFroms.push_back("SDOperand(N.Val, " +
+ ReplaceFroms.push_back("SDValue(N.Val, " +
utostr(NumPatResults) + ")");
- ReplaceTos.push_back("SDOperand(" + ChainName + ".Val, " +
+ ReplaceTos.push_back("SDValue(" + ChainName + ".Val, " +
ChainName + ".ResNo" + ")");
ChainAssignmentNeeded |= NodeHasChain;
}
@@ -1215,12 +1215,12 @@
} else if (InputHasChain && !NodeHasChain) {
// One of the inner node produces a chain.
if (NodeHasOutFlag) {
- ReplaceFroms.push_back("SDOperand(N.Val, " +
+ ReplaceFroms.push_back("SDValue(N.Val, " +
utostr(NumPatResults+1) +
")");
- ReplaceTos.push_back("SDOperand(ResNode, N.ResNo-1)");
+ ReplaceTos.push_back("SDValue(ResNode, N.ResNo-1)");
}
- ReplaceFroms.push_back("SDOperand(N.Val, " +
+ ReplaceFroms.push_back("SDValue(N.Val, " +
utostr(NumPatResults) + ")");
ReplaceTos.push_back(ChainName);
}
@@ -1230,10 +1230,10 @@
// Remember which op produces the chain.
std::string ChainAssign;
if (!isRoot)
- ChainAssign = ChainName + " = SDOperand(" + NodeName +
+ ChainAssign = ChainName + " = SDValue(" + NodeName +
".Val, " + utostr(NumResults+NumDstRegs) + ");";
else
- ChainAssign = ChainName + " = SDOperand(" + NodeName +
+ ChainAssign = ChainName + " = SDValue(" + NodeName +
", " + utostr(NumResults+NumDstRegs) + ");";
After.push_front(ChainAssign);
@@ -1243,11 +1243,11 @@
After.push_back("ReplaceUses(" + ReplaceFroms[0] + ", " +
ReplaceTos[0] + ");");
} else if (!ReplaceFroms.empty()) {
- After.push_back("const SDOperand Froms[] = {");
+ After.push_back("const SDValue Froms[] = {");
for (unsigned i = 0, e = ReplaceFroms.size(); i != e; ++i)
After.push_back(" " + ReplaceFroms[i] + (i + 1 != e ? "," : ""));
After.push_back("};");
- After.push_back("const SDOperand Tos[] = {");
+ After.push_back("const SDValue Tos[] = {");
for (unsigned i = 0, e = ReplaceFroms.size(); i != e; ++i)
After.push_back(" " + ReplaceTos[i] + (i + 1 != e ? "," : ""));
After.push_back("};");
@@ -1288,7 +1288,7 @@
EmitResultCode(N->getChild(0), DstRegs, InFlagDecled,
ResNodeDecled, true);
unsigned ResNo = TmpNo++;
- emitCode("SDOperand Tmp" + utostr(ResNo) + " = Transform_" + Op->getName()
+ emitCode("SDValue Tmp" + utostr(ResNo) + " = Transform_" + Op->getName()
+ "(" + Ops.back() + ".Val);");
NodeOps.push_back("Tmp" + utostr(ResNo));
if (isRoot)
@@ -1356,20 +1356,20 @@
MVT::SimpleValueType RVT = getRegisterValueType(RR, T);
if (RVT == MVT::Flag) {
if (!InFlagDecled) {
- emitCode("SDOperand InFlag = " + RootName + utostr(OpNo) + ";");
+ emitCode("SDValue InFlag = " + RootName + utostr(OpNo) + ";");
InFlagDecled = true;
} else
emitCode("InFlag = " + RootName + utostr(OpNo) + ";");
emitCode("AddToISelQueue(InFlag);");
} else {
if (!ChainEmitted) {
- emitCode("SDOperand Chain = CurDAG->getEntryNode();");
+ emitCode("SDValue Chain = CurDAG->getEntryNode();");
ChainName = "Chain";
ChainEmitted = true;
}
emitCode("AddToISelQueue(" + RootName + utostr(OpNo) + ");");
if (!InFlagDecled) {
- emitCode("SDOperand InFlag(0, 0);");
+ emitCode("SDValue InFlag(0, 0);");
InFlagDecled = true;
}
std::string Decl = (!ResNodeDecled) ? "SDNode *" : "";
@@ -1377,8 +1377,8 @@
", " + getQualifiedName(RR) +
", " + RootName + utostr(OpNo) + ", InFlag).Val;");
ResNodeDecled = true;
- emitCode(ChainName + " = SDOperand(ResNode, 0);");
- emitCode("InFlag = SDOperand(ResNode, 1);");
+ emitCode(ChainName + " = SDValue(ResNode, 0);");
+ emitCode("InFlag = SDValue(ResNode, 1);");
}
}
}
@@ -1387,7 +1387,7 @@
if (HasInFlag) {
if (!InFlagDecled) {
- emitCode("SDOperand InFlag = " + RootName +
+ emitCode("SDValue InFlag = " + RootName +
".getOperand(" + utostr(OpNo) + ");");
InFlagDecled = true;
} else
@@ -1767,7 +1767,7 @@
AddedInits.push_back(GeneratedCode[j].second);
}
- std::string CalleeCode = "(const SDOperand &N";
+ std::string CalleeCode = "(const SDValue &N";
std::string CallerCode = "(N";
for (unsigned j = 0, e = TargetOpcodes.size(); j != e; ++j) {
CalleeCode += ", unsigned Opc" + utostr(j);
@@ -1780,7 +1780,7 @@
for (std::set<std::string>::iterator
I = Decls.begin(), E = Decls.end(); I != E; ++I) {
std::string Name = *I;
- CalleeCode += ", SDOperand &" + Name;
+ CalleeCode += ", SDValue &" + Name;
CallerCode += ", " + Name;
}
@@ -1845,7 +1845,7 @@
OpVTI->second.push_back(OpVTStr);
OS << "SDNode *Select_" << getLegalCName(OpName)
- << OpVTStr << "(const SDOperand &N) {\n";
+ << OpVTStr << "(const SDValue &N) {\n";
// Loop through and reverse all of the CodeList vectors, as we will be
// accessing them from their logical front, but accessing the end of a
@@ -1884,8 +1884,8 @@
}
// Emit boilerplate.
- OS << "SDNode *Select_INLINEASM(SDOperand N) {\n"
- << " std::vector<SDOperand> Ops(N.Val->op_begin(), N.Val->op_end());\n"
+ OS << "SDNode *Select_INLINEASM(SDValue N) {\n"
+ << " std::vector<SDValue> Ops(N.Val->op_begin(), N.Val->op_end());\n"
<< " SelectInlineAsmMemoryOperands(Ops, *CurDAG);\n\n"
<< " // Ensure that the asm operands are themselves selected.\n"
@@ -1895,38 +1895,38 @@
<< " std::vector<MVT> VTs;\n"
<< " VTs.push_back(MVT::Other);\n"
<< " VTs.push_back(MVT::Flag);\n"
- << " SDOperand New = CurDAG->getNode(ISD::INLINEASM, VTs, &Ops[0], "
+ << " SDValue New = CurDAG->getNode(ISD::INLINEASM, VTs, &Ops[0], "
"Ops.size());\n"
<< " return New.Val;\n"
<< "}\n\n";
- OS << "SDNode *Select_UNDEF(const SDOperand &N) {\n"
+ OS << "SDNode *Select_UNDEF(const SDValue &N) {\n"
<< " return CurDAG->SelectNodeTo(N.Val, TargetInstrInfo::IMPLICIT_DEF,\n"
<< " N.getValueType());\n"
<< "}\n\n";
- OS << "SDNode *Select_DBG_LABEL(const SDOperand &N) {\n"
- << " SDOperand Chain = N.getOperand(0);\n"
+ OS << "SDNode *Select_DBG_LABEL(const SDValue &N) {\n"
+ << " SDValue Chain = N.getOperand(0);\n"
<< " unsigned C = cast<LabelSDNode>(N)->getLabelID();\n"
- << " SDOperand Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
+ << " SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
<< " AddToISelQueue(Chain);\n"
<< " return CurDAG->SelectNodeTo(N.Val, TargetInstrInfo::DBG_LABEL,\n"
<< " MVT::Other, Tmp, Chain);\n"
<< "}\n\n";
- OS << "SDNode *Select_EH_LABEL(const SDOperand &N) {\n"
- << " SDOperand Chain = N.getOperand(0);\n"
+ OS << "SDNode *Select_EH_LABEL(const SDValue &N) {\n"
+ << " SDValue Chain = N.getOperand(0);\n"
<< " unsigned C = cast<LabelSDNode>(N)->getLabelID();\n"
- << " SDOperand Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
+ << " SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
<< " AddToISelQueue(Chain);\n"
<< " return CurDAG->SelectNodeTo(N.Val, TargetInstrInfo::EH_LABEL,\n"
<< " MVT::Other, Tmp, Chain);\n"
<< "}\n\n";
- OS << "SDNode *Select_DECLARE(const SDOperand &N) {\n"
- << " SDOperand Chain = N.getOperand(0);\n"
- << " SDOperand N1 = N.getOperand(1);\n"
- << " SDOperand N2 = N.getOperand(2);\n"
+ OS << "SDNode *Select_DECLARE(const SDValue &N) {\n"
+ << " SDValue Chain = N.getOperand(0);\n"
+ << " SDValue N1 = N.getOperand(1);\n"
+ << " SDValue N2 = N.getOperand(2);\n"
<< " if (!isa<FrameIndexSDNode>(N1) || !isa<GlobalAddressSDNode>(N2)) {\n"
<< " cerr << \"Cannot yet select llvm.dbg.declare: \";\n"
<< " N.Val->dump(CurDAG);\n"
@@ -1934,31 +1934,31 @@
<< " }\n"
<< " int FI = cast<FrameIndexSDNode>(N1)->getIndex();\n"
<< " GlobalValue *GV = cast<GlobalAddressSDNode>(N2)->getGlobal();\n"
- << " SDOperand Tmp1 = "
+ << " SDValue Tmp1 = "
<< "CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());\n"
- << " SDOperand Tmp2 = "
+ << " SDValue Tmp2 = "
<< "CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy());\n"
<< " AddToISelQueue(Chain);\n"
<< " return CurDAG->SelectNodeTo(N.Val, TargetInstrInfo::DECLARE,\n"
<< " MVT::Other, Tmp1, Tmp2, Chain);\n"
<< "}\n\n";
- OS << "SDNode *Select_EXTRACT_SUBREG(const SDOperand &N) {\n"
- << " SDOperand N0 = N.getOperand(0);\n"
- << " SDOperand N1 = N.getOperand(1);\n"
+ OS << "SDNode *Select_EXTRACT_SUBREG(const SDValue &N) {\n"
+ << " SDValue N0 = N.getOperand(0);\n"
+ << " SDValue N1 = N.getOperand(1);\n"
<< " unsigned C = cast<ConstantSDNode>(N1)->getValue();\n"
- << " SDOperand Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
+ << " SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
<< " AddToISelQueue(N0);\n"
<< " return CurDAG->SelectNodeTo(N.Val, TargetInstrInfo::EXTRACT_SUBREG,\n"
<< " N.getValueType(), N0, Tmp);\n"
<< "}\n\n";
- OS << "SDNode *Select_INSERT_SUBREG(const SDOperand &N) {\n"
- << " SDOperand N0 = N.getOperand(0);\n"
- << " SDOperand N1 = N.getOperand(1);\n"
- << " SDOperand N2 = N.getOperand(2);\n"
+ OS << "SDNode *Select_INSERT_SUBREG(const SDValue &N) {\n"
+ << " SDValue N0 = N.getOperand(0);\n"
+ << " SDValue N1 = N.getOperand(1);\n"
+ << " SDValue N2 = N.getOperand(2);\n"
<< " unsigned C = cast<ConstantSDNode>(N2)->getValue();\n"
- << " SDOperand Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
+ << " SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
<< " AddToISelQueue(N1);\n"
<< " AddToISelQueue(N0);\n"
<< " return CurDAG->SelectNodeTo(N.Val, TargetInstrInfo::INSERT_SUBREG,\n"
@@ -1966,7 +1966,7 @@
<< "}\n\n";
OS << "// The main instruction selector code.\n"
- << "SDNode *SelectCode(SDOperand N) {\n"
+ << "SDNode *SelectCode(SDValue N) {\n"
<< " if (N.isMachineOpcode()) {\n"
<< " return NULL; // Already selected.\n"
<< " }\n\n"
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