[llvm-commits] [llvm] r48143 - in /llvm/trunk/lib/Target/PowerPC: PPCISelLowering.cpp PPCInstrInfo.cpp PPCInstrInfo.td PPCRegisterInfo.cpp PPCRegisterInfo.td
Evan Cheng
evan.cheng at apple.com
Mon Mar 10 10:09:08 PDT 2008
Very nice. Thanks! Some comments below:
On Mar 10, 2008, at 7:12 AM, Nicolas Geoffray wrote:
> Author: geoffray
> Date: Mon Mar 10 09:12:10 2008
> New Revision: 48143
>
> URL: http://llvm.org/viewvc/llvm-project?rev=48143&view=rev
> Log:
> Add description of individual bits in CR. This fix PR1765.
>
>
>
> Modified:
> llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
> llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
> llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
> llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
> llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=48143&r1=48142&r2=48143&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Mon Mar 10
> 09:12:10 2008
> @@ -1950,8 +1950,8 @@
>
> // With the ELF 32 ABI, set CR6 to true if this is a vararg call.
> if (isVarArg && isELF32_ABI) {
> - SDOperand SetCR(DAG.getTargetNode(PPC::SETCR, MVT::i32), 0);
> - Chain = DAG.getCopyToReg(Chain, PPC::CR6, SetCR, InFlag);
> + SDOperand SetCR(DAG.getTargetNode(PPC::CRSET, MVT::i32), 0);
> + Chain = DAG.getCopyToReg(Chain, PPC::CR1EQ, SetCR, InFlag);
> InFlag = Chain.getValue(1);
> }
>
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=48143&r1=48142&r2=48143&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Mon Mar 10
> 09:12:10 2008
> @@ -314,6 +314,8 @@
> BuildMI(MBB, MI, get(PPC::MCRF), DestReg).addReg(SrcReg);
> } else if (DestRC == PPC::VRRCRegisterClass) {
> BuildMI(MBB, MI, get(PPC::VOR),
> DestReg).addReg(SrcReg).addReg(SrcReg);
> + } else if (DestRC == PPC::CRBITRCRegisterClass) {
> + BuildMI(MBB, MI, get(PPC::CROR),
> DestReg).addReg(SrcReg).addReg(SrcReg);
> } else {
> cerr << "Attempt to copy register that is not GPR or FPR";
> abort();
> @@ -379,6 +381,35 @@
> .addReg(PPC::R0, false,
> false, isKill),
> FrameIdx));
> }
> + } else if (RC == PPC::CRBITRCRegisterClass) {
> + // FIXME: We use CRi here because there is no mtcrf on a bit.
> Since the
> + // backend currently only uses CR1EQ as an individual bit, this
> should
> + // not cause any bug. If we need other uses of CR bits, the
> following
> + // code may be invalid.
I don't think this is right. Any of the CR registers may be used,
right? Bill recently added register scavenging support to PPC (not yet
turned on). I think that's the way to go?
I suspect this is also very inefficient. CopyCost = -1 doesn't work
because the scheduler PPC uses hasn't been taught to deal with
expensive register copies. That's another todo in case this is a
performance issue (which I suspect it is?)
>
> + if (SrcReg >= PPC::CR0LT || SrcReg <= PPC::CR0UN)
> + return StoreRegToStackSlot(TII, PPC::CR0, isKill, FrameIdx,
> + PPC::CRRCRegisterClass, NewMIs);
> + else if (SrcReg >= PPC::CR1LT || SrcReg <= PPC::CR1UN)
> + return StoreRegToStackSlot(TII, PPC::CR1, isKill, FrameIdx,
> + PPC::CRRCRegisterClass, NewMIs);
> + if (SrcReg >= PPC::CR2LT || SrcReg <= PPC::CR2UN)
> + return StoreRegToStackSlot(TII, PPC::CR2, isKill, FrameIdx,
> + PPC::CRRCRegisterClass, NewMIs);
> + if (SrcReg >= PPC::CR3LT || SrcReg <= PPC::CR3UN)
> + return StoreRegToStackSlot(TII, PPC::CR3, isKill, FrameIdx,
> + PPC::CRRCRegisterClass, NewMIs);
> + if (SrcReg >= PPC::CR4LT || SrcReg <= PPC::CR4UN)
> + return StoreRegToStackSlot(TII, PPC::CR4, isKill, FrameIdx,
> + PPC::CRRCRegisterClass, NewMIs);
> + if (SrcReg >= PPC::CR5LT || SrcReg <= PPC::CR5UN)
> + return StoreRegToStackSlot(TII, PPC::CR5, isKill, FrameIdx,
> + PPC::CRRCRegisterClass, NewMIs);
> + if (SrcReg >= PPC::CR6LT || SrcReg <= PPC::CR6UN)
> + return StoreRegToStackSlot(TII, PPC::CR6, isKill, FrameIdx,
> + PPC::CRRCRegisterClass, NewMIs);
> + if (SrcReg >= PPC::CR7LT || SrcReg <= PPC::CR7UN)
> + return StoreRegToStackSlot(TII, PPC::CR7, isKill, FrameIdx,
> + PPC::CRRCRegisterClass, NewMIs);
Stylistic nitpick. Please use the if else to find the right CR
register than issue the StoreRegToStackSlot:
if (...)
Reg = PPC:CR0
else if (...)
Reg = PPC:CR1
...
StoreRegToStack(TII, Reg, isKill, FrameIdx, PPC::CRRCRegisterClass,
NewMIs)
Thanks,
Evan
>
> } else if (RC == PPC::VRRCRegisterClass) {
> // We don't have indexed addressing for vector loads. Emit:
> // R0 = ADDI FI#
> @@ -501,6 +532,31 @@
> }
>
> NewMIs.push_back(BuildMI(TII.get(PPC::MTCRF),
> DestReg).addReg(PPC::R0));
> + } else if (RC == PPC::CRBITRCRegisterClass) {
> + if (DestReg >= PPC::CR0LT || DestReg <= PPC::CR0UN)
> + return LoadRegFromStackSlot(TII, PPC::CR0, FrameIdx,
> + PPC::CRRCRegisterClass, NewMIs);
> + else if (DestReg >= PPC::CR1LT || DestReg <= PPC::CR1UN)
> + return LoadRegFromStackSlot(TII, PPC::CR1, FrameIdx,
> + PPC::CRRCRegisterClass, NewMIs);
> + if (DestReg >= PPC::CR2LT || DestReg <= PPC::CR2UN)
> + return LoadRegFromStackSlot(TII, PPC::CR2, FrameIdx,
> + PPC::CRRCRegisterClass, NewMIs);
> + if (DestReg >= PPC::CR3LT || DestReg <= PPC::CR3UN)
> + return LoadRegFromStackSlot(TII, PPC::CR3, FrameIdx,
> + PPC::CRRCRegisterClass, NewMIs);
> + if (DestReg >= PPC::CR4LT || DestReg <= PPC::CR4UN)
> + return LoadRegFromStackSlot(TII, PPC::CR4, FrameIdx,
> + PPC::CRRCRegisterClass, NewMIs);
> + if (DestReg >= PPC::CR5LT || DestReg <= PPC::CR5UN)
> + return LoadRegFromStackSlot(TII, PPC::CR5, FrameIdx,
> + PPC::CRRCRegisterClass, NewMIs);
> + if (DestReg >= PPC::CR6LT || DestReg <= PPC::CR6UN)
> + return LoadRegFromStackSlot(TII, PPC::CR6, FrameIdx,
> + PPC::CRRCRegisterClass, NewMIs);
> + if (DestReg >= PPC::CR7LT || DestReg <= PPC::CR7UN)
> + return LoadRegFromStackSlot(TII, PPC::CR7, FrameIdx,
> + PPC::CRRCRegisterClass, NewMIs);
> } else if (RC == PPC::VRRCRegisterClass) {
> // We don't have indexed addressing for vector loads. Emit:
> // R0 = ADDI FI#
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=48143&r1=48142&r2=48143&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Mon Mar 10
> 09:12:10 2008
> @@ -408,7 +408,9 @@
> F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
>
> V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
> LR,CTR,
> - CR0,CR1,CR5,CR6,CR7] in {
> + CR0,CR1,CR5,CR6,CR7,
> +
> CR0LT,CR0GT,CR0EQ,CR0UN,CR1LT,CR1GT,CR1EQ,CR1UN,CR5LT,CR5GT,CR5EQ,
> + CR5UN,CR6LT,CR6GT,CR6EQ,CR6UN,CR7LT,CR7GT,CR7EQ,CR7UN] in {
> // Convenient aliases for call instructions
> def BL_Macho : IForm<18, 0, 1,
> (outs), (ins calltarget:$func, variable_ops),
> @@ -429,7 +431,9 @@
> F0,F1,F2,F3,F4,F5,F6,F7,F8,
>
> V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
> LR,CTR,
> - CR0,CR1,CR5,CR6,CR7] in {
> + CR0,CR1,CR5,CR6,CR7,
> +
> CR0LT,CR0GT,CR0EQ,CR0UN,CR1LT,CR1GT,CR1EQ,CR1UN,CR5LT,CR5GT,CR5EQ,
> + CR5UN,CR6LT,CR6GT,CR6EQ,CR6UN,CR7LT,CR7GT,CR7EQ,CR7UN] in {
> // Convenient aliases for call instructions
> def BL_ELF : IForm<18, 0, 1,
> (outs), (ins calltarget:$func, variable_ops),
> @@ -860,11 +864,17 @@
> "mcrf $BF, $BFA", BrMCR>,
> PPC970_DGroup_First, PPC970_Unit_CRU;
>
> -def CREQV : XLForm_1<19, 289, (outs CRRC:$CRD), (ins CRRC:$CRA,
> CRRC:$CRB),
> +def CREQV : XLForm_1<19, 289, (outs CRBITRC:$CRD),
> + (ins CRBITRC:$CRA, CRBITRC:$CRB),
> "creqv $CRD, $CRA, $CRB", BrCR,
> []>;
>
> -def SETCR : XLForm_1_ext<19, 289, (outs CRRC:$dst), (ins),
> +def CROR : XLForm_1<19, 449, (outs CRBITRC:$CRD),
> + (ins CRBITRC:$CRA, CRBITRC:$CRB),
> + "cror $CRD, $CRA, $CRB", BrCR,
> + []>;
> +
> +def CRSET : XLForm_1_ext<19, 289, (outs CRBITRC:$dst), (ins),
> "creqv $dst, $dst, $dst", BrCR,
> []>;
>
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=48143&r1=48142&r2=48143&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Mon Mar 10
> 09:12:10 2008
> @@ -60,38 +60,38 @@
> using namespace PPC;
> switch (RegEnum) {
> case 0: return 0;
> - case R0 : case X0 : case F0 : case V0 : case CR0: return 0;
> - case R1 : case X1 : case F1 : case V1 : case CR1: return 1;
> - case R2 : case X2 : case F2 : case V2 : case CR2: return 2;
> - case R3 : case X3 : case F3 : case V3 : case CR3: return 3;
> - case R4 : case X4 : case F4 : case V4 : case CR4: return 4;
> - case R5 : case X5 : case F5 : case V5 : case CR5: return 5;
> - case R6 : case X6 : case F6 : case V6 : case CR6: return 6;
> - case R7 : case X7 : case F7 : case V7 : case CR7: return 7;
> - case R8 : case X8 : case F8 : case V8 : return 8;
> - case R9 : case X9 : case F9 : case V9 : return 9;
> - case R10: case X10: case F10: case V10: return 10;
> - case R11: case X11: case F11: case V11: return 11;
> - case R12: case X12: case F12: case V12: return 12;
> - case R13: case X13: case F13: case V13: return 13;
> - case R14: case X14: case F14: case V14: return 14;
> - case R15: case X15: case F15: case V15: return 15;
> - case R16: case X16: case F16: case V16: return 16;
> - case R17: case X17: case F17: case V17: return 17;
> - case R18: case X18: case F18: case V18: return 18;
> - case R19: case X19: case F19: case V19: return 19;
> - case R20: case X20: case F20: case V20: return 20;
> - case R21: case X21: case F21: case V21: return 21;
> - case R22: case X22: case F22: case V22: return 22;
> - case R23: case X23: case F23: case V23: return 23;
> - case R24: case X24: case F24: case V24: return 24;
> - case R25: case X25: case F25: case V25: return 25;
> - case R26: case X26: case F26: case V26: return 26;
> - case R27: case X27: case F27: case V27: return 27;
> - case R28: case X28: case F28: case V28: return 28;
> - case R29: case X29: case F29: case V29: return 29;
> - case R30: case X30: case F30: case V30: return 30;
> - case R31: case X31: case F31: case V31: return 31;
> + case R0 : case X0 : case F0 : case V0 : case CR0: case CR0LT:
> return 0;
> + case R1 : case X1 : case F1 : case V1 : case CR1: case CR0GT:
> return 1;
> + case R2 : case X2 : case F2 : case V2 : case CR2: case CR0EQ:
> return 2;
> + case R3 : case X3 : case F3 : case V3 : case CR3: case CR0UN:
> return 3;
> + case R4 : case X4 : case F4 : case V4 : case CR4: case CR1LT:
> return 4;
> + case R5 : case X5 : case F5 : case V5 : case CR5: case CR1GT:
> return 5;
> + case R6 : case X6 : case F6 : case V6 : case CR6: case CR1EQ:
> return 6;
> + case R7 : case X7 : case F7 : case V7 : case CR7: case CR1UN:
> return 7;
> + case R8 : case X8 : case F8 : case V8 : case CR2LT: return 8;
> + case R9 : case X9 : case F9 : case V9 : case CR2GT: return 9;
> + case R10: case X10: case F10: case V10: case CR2EQ: return 10;
> + case R11: case X11: case F11: case V11: case CR2UN: return 11;
> + case R12: case X12: case F12: case V12: case CR3LT: return 12;
> + case R13: case X13: case F13: case V13: case CR3GT: return 13;
> + case R14: case X14: case F14: case V14: case CR3EQ: return 14;
> + case R15: case X15: case F15: case V15: case CR3UN: return 15;
> + case R16: case X16: case F16: case V16: case CR4LT: return 16;
> + case R17: case X17: case F17: case V17: case CR4GT: return 17;
> + case R18: case X18: case F18: case V18: case CR4EQ: return 18;
> + case R19: case X19: case F19: case V19: case CR4UN: return 19;
> + case R20: case X20: case F20: case V20: case CR5LT: return 20;
> + case R21: case X21: case F21: case V21: case CR5GT: return 21;
> + case R22: case X22: case F22: case V22: case CR5EQ: return 22;
> + case R23: case X23: case F23: case V23: case CR5UN: return 23;
> + case R24: case X24: case F24: case V24: case CR6LT: return 24;
> + case R25: case X25: case F25: case V25: case CR6GT: return 25;
> + case R26: case X26: case F26: case V26: case CR6EQ: return 26;
> + case R27: case X27: case F27: case V27: case CR6UN: return 27;
> + case R28: case X28: case F28: case V28: case CR7LT: return 28;
> + case R29: case X29: case F29: case V29: case CR7GT: return 29;
> + case R30: case X30: case F30: case V30: case CR7EQ: return 30;
> + case R31: case X31: case F31: case V31: case CR7UN: return 31;
> default:
> cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!
> \n";
> abort();
> @@ -149,6 +149,10 @@
> PPC::V24, PPC::V25, PPC::V26, PPC::V27,
> PPC::V28, PPC::V29, PPC::V30, PPC::V31,
>
> + PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
> + PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
> + PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
> +
> PPC::LR, 0
> };
>
> @@ -172,6 +176,10 @@
> PPC::V24, PPC::V25, PPC::V26, PPC::V27,
> PPC::V28, PPC::V29, PPC::V30, PPC::V31,
>
> + PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
> + PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
> + PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
> +
> PPC::LR, 0
> };
> // 64-bit Darwin calling convention.
> @@ -193,6 +201,10 @@
> PPC::V24, PPC::V25, PPC::V26, PPC::V27,
> PPC::V28, PPC::V29, PPC::V30, PPC::V31,
>
> + PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
> + PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
> + PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
> +
> PPC::LR8, 0
> };
>
> @@ -226,6 +238,13 @@
>
> &PPC
> ::VRRCRegClass
> ,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
>
> &PPC
> ::VRRCRegClass
> ,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
>
> +
> &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
> + &PPC::CRBITRCRegClass,
> +
> &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
> + &PPC::CRBITRCRegClass,
> +
> &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
> + &PPC::CRBITRCRegClass,
> +
> &PPC::GPRCRegClass, 0
> };
>
> @@ -250,6 +269,13 @@
>
> &PPC
> ::VRRCRegClass
> ,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
>
> &PPC
> ::VRRCRegClass
> ,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
>
> +
> &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
> + &PPC::CRBITRCRegClass,
> +
> &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
> + &PPC::CRBITRCRegClass,
> +
> &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
> + &PPC::CRBITRCRegClass,
> +
> &PPC::GPRCRegClass, 0
> };
>
> @@ -273,6 +299,13 @@
>
> &PPC
> ::VRRCRegClass
> ,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
>
> &PPC
> ::VRRCRegClass
> ,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
>
> +
> &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
> + &PPC::CRBITRCRegClass,
> +
> &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
> + &PPC::CRBITRCRegClass,
> +
> &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
> + &PPC::CRBITRCRegClass,
> +
> &PPC::G8RCRegClass, 0
> };
>
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td?rev=48143&r1=48142&r2=48143&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td Mon Mar 10
> 09:12:10 2008
> @@ -331,4 +331,19 @@
>
> def CRRC : RegisterClass<"PPC", [i32], 32, [CR0, CR1, CR5, CR6, CR7,
> CR2,
> CR3, CR4]>;
> +
> +def CRBITRC : RegisterClass<"PPC", [i32], 32,
> + [CR0LT, CR0GT, CR0EQ, CR0UN,
> + CR1LT, CR1GT, CR1EQ, CR1UN,
> + CR2LT, CR2GT, CR2EQ, CR2UN,
> + CR3LT, CR3GT, CR3EQ, CR3UN,
> + CR4LT, CR4GT, CR4EQ, CR4UN,
> + CR5LT, CR5GT, CR5EQ, CR5UN,
> + CR6LT, CR6GT, CR6EQ, CR6UN,
> + CR7LT, CR7GT, CR7EQ, CR7UN
> + ]>
> +{
> + let CopyCost = -1;
> +}
> +
>
>
>
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