[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h X86InstrInfo.td
Nate Begeman
natebegeman at mac.com
Thu Feb 16 21:44:12 PST 2006
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.85 -> 1.86
X86ISelLowering.h updated: 1.26 -> 1.27
X86InstrInfo.td updated: 1.236 -> 1.237
---
Log message:
kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.
---
Diffs of the changes: (+28 -77)
X86ISelLowering.cpp | 30 ------------------------
X86ISelLowering.h | 10 --------
X86InstrInfo.td | 65 ++++++++++++++++++++++------------------------------
3 files changed, 28 insertions(+), 77 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.85 llvm/lib/Target/X86/X86ISelLowering.cpp:1.86
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.85 Thu Feb 16 18:03:04 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu Feb 16 23:43:56 2006
@@ -160,8 +160,6 @@
// Darwin ABI issue.
setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
// 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
- setOperationAction(ISD::ADD_PARTS , MVT::i32 , Custom);
- setOperationAction(ISD::SUB_PARTS , MVT::i32 , Custom);
setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
@@ -1270,30 +1268,6 @@
SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
switch (Op.getOpcode()) {
default: assert(0 && "Should not custom lower this!");
- case ISD::ADD_PARTS:
- case ISD::SUB_PARTS: {
- assert(Op.getNumOperands() == 4 && Op.getValueType() == MVT::i32 &&
- "Not an i64 add/sub!");
- bool isAdd = Op.getOpcode() == ISD::ADD_PARTS;
- std::vector<MVT::ValueType> Tys;
- Tys.push_back(MVT::i32);
- Tys.push_back(MVT::Flag);
- std::vector<SDOperand> Ops;
- Ops.push_back(Op.getOperand(0));
- Ops.push_back(Op.getOperand(2));
- SDOperand Lo = DAG.getNode(isAdd ? X86ISD::ADD_FLAG : X86ISD::SUB_FLAG,
- Tys, Ops);
- SDOperand Hi = DAG.getNode(isAdd ? X86ISD::ADC : X86ISD::SBB, MVT::i32,
- Op.getOperand(1), Op.getOperand(3),
- Lo.getValue(1));
- Tys.clear();
- Tys.push_back(MVT::i32);
- Tys.push_back(MVT::i32);
- Ops.clear();
- Ops.push_back(Lo);
- Ops.push_back(Hi);
- return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
- }
case ISD::SHL_PARTS:
case ISD::SRA_PARTS:
case ISD::SRL_PARTS: {
@@ -1910,10 +1884,6 @@
const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
switch (Opcode) {
default: return NULL;
- case X86ISD::ADD_FLAG: return "X86ISD::ADD_FLAG";
- case X86ISD::SUB_FLAG: return "X86ISD::SUB_FLAG";
- case X86ISD::ADC: return "X86ISD::ADC";
- case X86ISD::SBB: return "X86ISD::SBB";
case X86ISD::SHLD: return "X86ISD::SHLD";
case X86ISD::SHRD: return "X86ISD::SHRD";
case X86ISD::FAND: return "X86ISD::FAND";
Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.26 llvm/lib/Target/X86/X86ISelLowering.h:1.27
--- llvm/lib/Target/X86/X86ISelLowering.h:1.26 Thu Feb 16 15:11:51 2006
+++ llvm/lib/Target/X86/X86ISelLowering.h Thu Feb 16 23:43:56 2006
@@ -26,16 +26,6 @@
// Start the numbering where the builtin ops leave off.
FIRST_NUMBER = ISD::BUILTIN_OP_END+X86::INSTRUCTION_LIST_END,
- /// ADD_FLAG, SUB_FLAG - Same as ISD::ADD and ISD::SUB except it also
- /// produces a flag result.
- ADD_FLAG,
- SUB_FLAG,
-
- /// ADC, SBB - Add with carry and subtraction with borrow. These
- /// correspond to X86::ADCxx and X86::SBBxx instructions.
- ADC,
- SBB,
-
/// SHLD, SHRD - Double shift instructions. These correspond to
/// X86::SHLDxx and X86::SHRDxx instructions.
SHLD,
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.236 llvm/lib/Target/X86/X86InstrInfo.td:1.237
--- llvm/lib/Target/X86/X86InstrInfo.td:1.236 Thu Feb 16 17:59:30 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td Thu Feb 16 23:43:56 2006
@@ -56,15 +56,6 @@
def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
-def X86addflag : SDNode<"X86ISD::ADD_FLAG", SDTIntBinOp ,
- [SDNPCommutative, SDNPAssociative, SDNPOutFlag]>;
-def X86subflag : SDNode<"X86ISD::SUB_FLAG", SDTIntBinOp,
- [SDNPOutFlag]>;
-def X86adc : SDNode<"X86ISD::ADC" , SDTIntBinOp ,
- [SDNPCommutative, SDNPAssociative, SDNPInFlag]>;
-def X86sbb : SDNode<"X86ISD::SBB" , SDTIntBinOp,
- [SDNPInFlag]>;
-
def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
@@ -1873,28 +1864,28 @@
let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
def ADC32rr : I<0x11, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
"adc{l} {$src2, $dst|$dst, $src2}",
- [(set R32:$dst, (X86adc R32:$src1, R32:$src2))]>;
+ [(set R32:$dst, (adde R32:$src1, R32:$src2))]>;
}
def ADC32rm : I<0x13, MRMSrcMem , (ops R32:$dst, R32:$src1, i32mem:$src2),
"adc{l} {$src2, $dst|$dst, $src2}",
- [(set R32:$dst, (X86adc R32:$src1, (load addr:$src2)))]>;
+ [(set R32:$dst, (adde R32:$src1, (load addr:$src2)))]>;
def ADC32ri : Ii32<0x81, MRM2r, (ops R32:$dst, R32:$src1, i32imm:$src2),
"adc{l} {$src2, $dst|$dst, $src2}",
- [(set R32:$dst, (X86adc R32:$src1, imm:$src2))]>;
+ [(set R32:$dst, (adde R32:$src1, imm:$src2))]>;
def ADC32ri8 : Ii8<0x83, MRM2r, (ops R32:$dst, R32:$src1, i32i8imm:$src2),
"adc{l} {$src2, $dst|$dst, $src2}",
- [(set R32:$dst, (X86adc R32:$src1, i32immSExt8:$src2))]>;
+ [(set R32:$dst, (adde R32:$src1, i32immSExt8:$src2))]>;
let isTwoAddress = 0 in {
def ADC32mr : I<0x11, MRMDestMem, (ops i32mem:$dst, R32:$src2),
"adc{l} {$src2, $dst|$dst, $src2}",
- [(store (X86adc (load addr:$dst), R32:$src2), addr:$dst)]>;
+ [(store (adde (load addr:$dst), R32:$src2), addr:$dst)]>;
def ADC32mi : Ii32<0x81, MRM2m, (ops i32mem:$dst, i32imm:$src2),
"adc{l} {$src2, $dst|$dst, $src2}",
- [(store (X86adc (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
+ [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
def ADC32mi8 : Ii8<0x83, MRM2m, (ops i32mem:$dst, i32i8imm :$src2),
"adc{l} {$src2, $dst|$dst, $src2}",
- [(store (X86adc (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
+ [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
}
def SUB8rr : I<0x28, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2),
@@ -1964,51 +1955,51 @@
def SBB32rr : I<0x19, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
"sbb{l} {$src2, $dst|$dst, $src2}",
- [(set R32:$dst, (X86sbb R32:$src1, R32:$src2))]>;
+ [(set R32:$dst, (sube R32:$src1, R32:$src2))]>;
let isTwoAddress = 0 in {
def SBB32mr : I<0x19, MRMDestMem, (ops i32mem:$dst, R32:$src2),
"sbb{l} {$src2, $dst|$dst, $src2}",
- [(store (X86sbb (load addr:$dst), R32:$src2), addr:$dst)]>;
+ [(store (sube (load addr:$dst), R32:$src2), addr:$dst)]>;
def SBB8mi : Ii32<0x80, MRM3m, (ops i8mem:$dst, i8imm:$src2),
"sbb{b} {$src2, $dst|$dst, $src2}",
- [(store (X86sbb (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
+ [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
def SBB16mi : Ii32<0x81, MRM3m, (ops i16mem:$dst, i16imm:$src2),
"sbb{w} {$src2, $dst|$dst, $src2}",
- [(store (X86sbb (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
+ [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
OpSize;
def SBB32mi : Ii32<0x81, MRM3m, (ops i32mem:$dst, i32imm:$src2),
"sbb{l} {$src2, $dst|$dst, $src2}",
- [(store (X86sbb (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
+ [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
def SBB16mi8 : Ii8<0x83, MRM3m, (ops i16mem:$dst, i16i8imm :$src2),
"sbb{w} {$src2, $dst|$dst, $src2}",
- [(store (X86sbb (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
+ [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
OpSize;
def SBB32mi8 : Ii8<0x83, MRM3m, (ops i32mem:$dst, i32i8imm :$src2),
"sbb{l} {$src2, $dst|$dst, $src2}",
- [(store (X86sbb (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
+ [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
}
def SBB8ri : Ii8<0x80, MRM3r, (ops R8:$dst, R8:$src1, i8imm:$src2),
"sbb{b} {$src2, $dst|$dst, $src2}",
- [(set R8:$dst, (X86sbb R8:$src1, imm:$src2))]>;
+ [(set R8:$dst, (sube R8:$src1, imm:$src2))]>;
def SBB16ri : Ii16<0x81, MRM3r, (ops R16:$dst, R16:$src1, i16imm:$src2),
"sbb{w} {$src2, $dst|$dst, $src2}",
- [(set R16:$dst, (X86sbb R16:$src1, imm:$src2))]>, OpSize;
+ [(set R16:$dst, (sube R16:$src1, imm:$src2))]>, OpSize;
def SBB32rm : I<0x1B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
"sbb{l} {$src2, $dst|$dst, $src2}",
- [(set R32:$dst, (X86sbb R32:$src1, (load addr:$src2)))]>;
+ [(set R32:$dst, (sube R32:$src1, (load addr:$src2)))]>;
def SBB32ri : Ii32<0x81, MRM3r, (ops R32:$dst, R32:$src1, i32imm:$src2),
"sbb{l} {$src2, $dst|$dst, $src2}",
- [(set R32:$dst, (X86sbb R32:$src1, imm:$src2))]>;
+ [(set R32:$dst, (sube R32:$src1, imm:$src2))]>;
def SBB16ri8 : Ii8<0x83, MRM3r, (ops R16:$dst, R16:$src1, i16i8imm:$src2),
"sbb{w} {$src2, $dst|$dst, $src2}",
- [(set R16:$dst, (X86sbb R16:$src1, i16immSExt8:$src2))]>,
+ [(set R16:$dst, (sube R16:$src1, i16immSExt8:$src2))]>,
OpSize;
def SBB32ri8 : Ii8<0x83, MRM3r, (ops R32:$dst, R32:$src1, i32i8imm:$src2),
"sbb{l} {$src2, $dst|$dst, $src2}",
- [(set R32:$dst, (X86sbb R32:$src1, i32immSExt8:$src2))]>;
+ [(set R32:$dst, (sube R32:$src1, i32immSExt8:$src2))]>;
let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
def IMUL16rr : I<0xAF, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
@@ -3077,22 +3068,22 @@
(CALLpcrel32 texternalsym:$dst)>;
// X86 specific add which produces a flag.
-def : Pat<(X86addflag R32:$src1, R32:$src2),
+def : Pat<(addc R32:$src1, R32:$src2),
(ADD32rr R32:$src1, R32:$src2)>;
-def : Pat<(X86addflag R32:$src1, (load addr:$src2)),
+def : Pat<(addc R32:$src1, (load addr:$src2)),
(ADD32rm R32:$src1, addr:$src2)>;
-def : Pat<(X86addflag R32:$src1, imm:$src2),
+def : Pat<(addc R32:$src1, imm:$src2),
(ADD32ri R32:$src1, imm:$src2)>;
-def : Pat<(X86addflag R32:$src1, i32immSExt8:$src2),
+def : Pat<(addc R32:$src1, i32immSExt8:$src2),
(ADD32ri8 R32:$src1, i32immSExt8:$src2)>;
-def : Pat<(X86subflag R32:$src1, R32:$src2),
+def : Pat<(subc R32:$src1, R32:$src2),
(SUB32rr R32:$src1, R32:$src2)>;
-def : Pat<(X86subflag R32:$src1, (load addr:$src2)),
+def : Pat<(subc R32:$src1, (load addr:$src2)),
(SUB32rm R32:$src1, addr:$src2)>;
-def : Pat<(X86subflag R32:$src1, imm:$src2),
+def : Pat<(subc R32:$src1, imm:$src2),
(SUB32ri R32:$src1, imm:$src2)>;
-def : Pat<(X86subflag R32:$src1, i32immSExt8:$src2),
+def : Pat<(subc R32:$src1, i32immSExt8:$src2),
(SUB32ri8 R32:$src1, i32immSExt8:$src2)>;
def : Pat<(truncstore (i8 imm:$src), addr:$dst, i1),
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