[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp SelectionDAG.cpp
Nate Begeman
natebegeman at mac.com
Thu Feb 16 21:44:12 PST 2006
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.103 -> 1.104
LegalizeDAG.cpp updated: 1.305 -> 1.306
SelectionDAG.cpp updated: 1.256 -> 1.257
---
Log message:
kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.
---
Diffs of the changes: (+47 -62)
DAGCombiner.cpp | 46 --------------------------------------------
LegalizeDAG.cpp | 57 +++++++++++++++++++++++++++++++++++++++++--------------
SelectionDAG.cpp | 6 +++--
3 files changed, 47 insertions(+), 62 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.103 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.104
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.103 Thu Feb 16 15:11:51 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Feb 16 23:43:56 2006
@@ -157,14 +157,11 @@
SDOperand visitSELECT(SDNode *N);
SDOperand visitSELECT_CC(SDNode *N);
SDOperand visitSETCC(SDNode *N);
- SDOperand visitADD_PARTS(SDNode *N);
- SDOperand visitSUB_PARTS(SDNode *N);
SDOperand visitSIGN_EXTEND(SDNode *N);
SDOperand visitZERO_EXTEND(SDNode *N);
SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
SDOperand visitTRUNCATE(SDNode *N);
SDOperand visitBIT_CONVERT(SDNode *N);
-
SDOperand visitFADD(SDNode *N);
SDOperand visitFSUB(SDNode *N);
SDOperand visitFMUL(SDNode *N);
@@ -183,7 +180,6 @@
SDOperand visitBRCONDTWOWAY(SDNode *N);
SDOperand visitBR_CC(SDNode *N);
SDOperand visitBRTWOWAY_CC(SDNode *N);
-
SDOperand visitLOAD(SDNode *N);
SDOperand visitSTORE(SDNode *N);
@@ -550,8 +546,6 @@
case ISD::SELECT: return visitSELECT(N);
case ISD::SELECT_CC: return visitSELECT_CC(N);
case ISD::SETCC: return visitSETCC(N);
- case ISD::ADD_PARTS: return visitADD_PARTS(N);
- case ISD::SUB_PARTS: return visitSUB_PARTS(N);
case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
@@ -1509,46 +1503,6 @@
cast<CondCodeSDNode>(N->getOperand(2))->get());
}
-SDOperand DAGCombiner::visitADD_PARTS(SDNode *N) {
- SDOperand LHSLo = N->getOperand(0);
- SDOperand RHSLo = N->getOperand(2);
- MVT::ValueType VT = LHSLo.getValueType();
-
- // fold (a_Hi, 0) + (b_Hi, b_Lo) -> (b_Hi + a_Hi, b_Lo)
- if (TLI.MaskedValueIsZero(LHSLo, (1ULL << MVT::getSizeInBits(VT))-1)) {
- SDOperand Hi = DAG.getNode(ISD::ADD, VT, N->getOperand(1),
- N->getOperand(3));
- WorkList.push_back(Hi.Val);
- CombineTo(N, RHSLo, Hi);
- return SDOperand();
- }
- // fold (a_Hi, a_Lo) + (b_Hi, 0) -> (a_Hi + b_Hi, a_Lo)
- if (TLI.MaskedValueIsZero(RHSLo, (1ULL << MVT::getSizeInBits(VT))-1)) {
- SDOperand Hi = DAG.getNode(ISD::ADD, VT, N->getOperand(1),
- N->getOperand(3));
- WorkList.push_back(Hi.Val);
- CombineTo(N, LHSLo, Hi);
- return SDOperand();
- }
- return SDOperand();
-}
-
-SDOperand DAGCombiner::visitSUB_PARTS(SDNode *N) {
- SDOperand LHSLo = N->getOperand(0);
- SDOperand RHSLo = N->getOperand(2);
- MVT::ValueType VT = LHSLo.getValueType();
-
- // fold (a_Hi, a_Lo) - (b_Hi, 0) -> (a_Hi - b_Hi, a_Lo)
- if (TLI.MaskedValueIsZero(RHSLo, (1ULL << MVT::getSizeInBits(VT))-1)) {
- SDOperand Hi = DAG.getNode(ISD::SUB, VT, N->getOperand(1),
- N->getOperand(3));
- WorkList.push_back(Hi.Val);
- CombineTo(N, LHSLo, Hi);
- return SDOperand();
- }
- return SDOperand();
-}
-
SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
SDOperand N0 = N->getOperand(0);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.305 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.306
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.305 Thu Feb 16 22:32:33 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Feb 16 23:43:56 2006
@@ -575,7 +575,7 @@
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
break;
}
- break;
+ break;
case ISD::Constant:
// We know we don't need to expand constants here, constants only have one
@@ -1749,8 +1749,6 @@
}
break;
- case ISD::ADD_PARTS:
- case ISD::SUB_PARTS:
case ISD::SHL_PARTS:
case ISD::SRA_PARTS:
case ISD::SRL_PARTS: {
@@ -1830,7 +1828,32 @@
break;
}
break;
+
+ case ISD::ADDC:
+ case ISD::SUBC:
+ Tmp1 = LegalizeOp(Node->getOperand(0));
+ Tmp2 = LegalizeOp(Node->getOperand(1));
+ Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
+ // Since this produces two values, make sure to remember that we legalized
+ // both of them.
+ AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
+ AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
+ return Result;
+ break;
+ case ISD::ADDE:
+ case ISD::SUBE:
+ Tmp1 = LegalizeOp(Node->getOperand(0));
+ Tmp2 = LegalizeOp(Node->getOperand(1));
+ Tmp3 = LegalizeOp(Node->getOperand(2));
+ Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
+ // Since this produces two values, make sure to remember that we legalized
+ // both of them.
+ AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
+ AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
+ return Result;
+ break;
+
case ISD::BUILD_PAIR: {
MVT::ValueType PairTy = Node->getValueType(0);
// TODO: handle the case where the Lo and Hi operands are not of legal type
@@ -3980,17 +4003,23 @@
SDOperand LHSL, LHSH, RHSL, RHSH;
ExpandOp(Node->getOperand(0), LHSL, LHSH);
ExpandOp(Node->getOperand(1), RHSL, RHSH);
-
- std::vector<SDOperand> Ops;
- Ops.push_back(LHSL);
- Ops.push_back(LHSH);
- Ops.push_back(RHSL);
- Ops.push_back(RHSH);
- std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
- unsigned Opc =
- Node->getOpcode() == ISD::ADD ? ISD::ADD_PARTS : ISD::SUB_PARTS;
- Lo = DAG.getNode(Opc, VTs, Ops);
- Hi = Lo.getValue(1);
+ std::vector<MVT::ValueType> VTs;
+ std::vector<SDOperand> LoOps, HiOps;
+ VTs.push_back(LHSL.getValueType());
+ VTs.push_back(MVT::Flag);
+ LoOps.push_back(LHSL);
+ LoOps.push_back(RHSL);
+ HiOps.push_back(LHSH);
+ HiOps.push_back(RHSH);
+ if (Node->getOpcode() == ISD::ADD) {
+ Lo = DAG.getNode(ISD::ADDC, VTs, LoOps);
+ HiOps.push_back(Lo.getValue(1));
+ Hi = DAG.getNode(ISD::ADDE, VTs, HiOps);
+ } else {
+ Lo = DAG.getNode(ISD::SUBC, VTs, LoOps);
+ HiOps.push_back(Lo.getValue(1));
+ Hi = DAG.getNode(ISD::SUBE, VTs, HiOps);
+ }
break;
}
case ISD::MUL: {
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.256 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.257
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.256 Thu Feb 9 16:11:03 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Feb 16 23:43:56 2006
@@ -2552,8 +2552,10 @@
case ISD::SETCC: return "setcc";
case ISD::SELECT: return "select";
case ISD::SELECT_CC: return "select_cc";
- case ISD::ADD_PARTS: return "add_parts";
- case ISD::SUB_PARTS: return "sub_parts";
+ case ISD::ADDC: return "addc";
+ case ISD::ADDE: return "adde";
+ case ISD::SUBC: return "subc";
+ case ISD::SUBE: return "sube";
case ISD::SHL_PARTS: return "shl_parts";
case ISD::SRA_PARTS: return "sra_parts";
case ISD::SRL_PARTS: return "srl_parts";
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