[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.84 -> 1.85
---
Log message:

Emit comparisons against the sign bit better.  Codegen this:

bool %test1(long %X) {
        %A = setlt long %X, 0
        ret bool %A
}

like this:

test1:
        cmpl $0, 8(%esp)
        setl %al
        movzbl %al, %eax
        ret

instead of:

test1:
        movl 8(%esp), %ecx
        cmpl $0, %ecx
        setl %al
        movzbw %al, %ax
        cmpl $0, 4(%esp)
        setb %dl
        movzbw %dl, %dx
        cmpl $0, %ecx
        cmove %dx, %ax
        movzbl %al, %eax
        ret



---
Diffs of the changes:  (+10 -0)

 LegalizeDAG.cpp |   10 ++++++++++
 1 files changed, 10 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.84 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.85
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.84	Mon Apr 11 20:46:05 2005
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Mon Apr 11 21:19:10 2005
@@ -768,6 +768,16 @@
                               DAG.getConstant(0, Tmp1.getValueType()));
         break;
       default:
+        // If this is a comparison of the sign bit, just look at the top part.
+        // X > -1,  x < 0
+        if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Node->getOperand(1)))
+          if ((cast<SetCCSDNode>(Node)->getCondition() == ISD::SETLT && 
+               CST->getValue() == 0) ||              // X < 0
+              (cast<SetCCSDNode>(Node)->getCondition() == ISD::SETGT &&
+               (CST->isAllOnesValue())))             // X > -1
+            return DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(),
+                                Node->getValueType(0), LHSHi, RHSHi);
+
         // FIXME: This generated code sucks.
         ISD::CondCode LowCC;
         switch (cast<SetCCSDNode>(Node)->getCondition()) {