[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Chris Lattner lattner at cs.uiuc.edu
Mon Apr 11 18:46:22 PDT 2005



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.83 -> 1.84
---
Log message:

Emit long comparison against -1 better.  Instead of this (x86):

test2:
        movl 8(%esp), %eax
        notl %eax
        movl 4(%esp), %ecx
        notl %ecx
        orl %eax, %ecx
        cmpl $0, %ecx
        sete %al
        movzbl %al, %eax
        ret

or this (PPC):

_test2:
        nor r2, r4, r4
        nor r3, r3, r3
        or r2, r2, r3
        cntlzw r2, r2
        srwi r3, r2, 5
        blr

Emit this:

test2:
        movl 8(%esp), %eax
        andl 4(%esp), %eax
        cmpl $-1, %eax
        sete %al
        movzbl %al, %eax
        ret

or this:

_test2:
.LBB_test2_0:   ; 
        and r2, r4, r3
        cmpwi cr0, r2, -1
        li r3, 1
        li r2, 0
        beq .LBB_test2_2        ; 
.LBB_test2_1:   ; 
        or r3, r2, r2
.LBB_test2_2:   ; 
        blr

it seems like the PPC isel could do better for R32 == -1 case.



---
Diffs of the changes:  (+10 -0)

 LegalizeDAG.cpp |   10 ++++++++++
 1 files changed, 10 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.83 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.84
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.83	Mon Apr 11 15:29:59 2005
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Mon Apr 11 20:46:05 2005
@@ -750,6 +750,16 @@
       switch (cast<SetCCSDNode>(Node)->getCondition()) {
       case ISD::SETEQ:
       case ISD::SETNE:
+        if (RHSLo == RHSHi)
+          if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
+            if (RHSCST->isAllOnesValue()) {
+              // Comparison to -1.
+              Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
+              Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(), 
+                                    Node->getValueType(0), Tmp1, RHSLo);
+              break;                                    
+            }
+
         Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
         Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
         Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);






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