[llvm-bugs] [Bug 44877] [CodeGenPrepare] Store splitting creates invalid alignments on big-endian targets, and under-aligned stores on all targets

via llvm-bugs llvm-bugs at lists.llvm.org
Wed Feb 19 04:11:17 PST 2020


https://bugs.llvm.org/show_bug.cgi?id=44877

Hans Wennborg <hans at chromium.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|RESOLVED                    |REOPENED
         Resolution|FIXED                       |---

--- Comment #9 from Hans Wennborg <hans at chromium.org> ---
That's strange. The test passes on my machine, and the output of the first run
line looks like this:

$ /work/llvm.monorepo.rel/build.release/bin/opt -S -codegenprepare
-mtriple=powerpc64-unknown-linux-gnu -data-layout="E-m:e-i64:64-n32:64"
-force-split-store <
/work/llvm.monorepo.rel/llvm/test/Transforms/CodeGenPrepare/PowerPC/split-store-alignment.ll
| head -19
; ModuleID = '<stdin>'
source_filename = "<stdin>"
target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu"

define void @split_store_align1(float %x, i64* %p) {
  %b = bitcast float %x to i32
  %z = zext i32 0 to i64
  %s = shl nuw nsw i64 %z, 32
  %z2 = zext i32 %b to i64
  %o = or i64 %s, %z2
  %1 = bitcast i64* %p to i32*
  %2 = getelementptr i32, i32* %1, i32 1
  store i32 %b, i32* %2, align 1
  %3 = bitcast i64* %p to i32*
  store i32 0, i32* %3, align 1
  ret void
}


Could it be due to a difference in host architecture or build configuration or
something?

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