[llvm-bugs] [Bug 47179] New: ARM64: Loading 64 bit/128 bit literals into SIMD&FP registers not working correctly

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https://bugs.llvm.org/show_bug.cgi?id=47179

            Bug ID: 47179
           Summary: ARM64: Loading 64 bit/128 bit literals into SIMD&FP
                    registers not working correctly
           Product: tools
           Version: trunk
          Hardware: Other
                OS: FreeBSD
            Status: NEW
          Severity: normal
          Priority: P
         Component: gccas
          Assignee: unassignedbugs at nondot.org
          Reporter: fuzxxl at gmail.com
                CC: llvm-bugs at lists.llvm.org

I'm trying to load a bit mask into an ARM64 SIMD&FP register like this:

    ldr d10, =0x8040201008040201

LLVM-as complains upon seeing this code:

    count8asm.s:8:11: error: Immediate too large for register
        ldr d10, =0x8040201008040201

However, this error message is clearly nonsensical.  GNU as assembles this just
fine.

The reason for this seems to be a borked check in AArch64AsmParser.cpp which
wants to check if the immediate is a 32 bit number when the argument is a W
register, but it instead does this check for all registers instead of X
registers, which is clearly incorrect.  More sophisticated handling, including
code to deal with 128 bit literals is needed.

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