[llvm-bugs] [Bug 45744] New: llc emits unnecessary 'and' instructions for multiple backends

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=45744

            Bug ID: 45744
           Summary: llc emits unnecessary 'and' instructions for multiple
                    backends
           Product: tools
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: llc
          Assignee: unassignedbugs at nondot.org
          Reporter: janekvoirschot at gmail.com
                CC: llvm-bugs at lists.llvm.org

'And' instructions are occasionally emitted for targets even though the value
masked originates from a zero extended byte load. Debugging a little bit
through the code, it seems that the 'and' instruction is as a result of a
truncation but no combine/peephole optimizer removes it as the byte load
instructions that load the values to be masked are copy instructions all the
way until register coalescing.

Example LLVM IR:

define i32 @foo(i8* %s1, i8* %s2) {
entry:
  %0 = load i8, i8* %s1, align 1
  %cmp16 = icmp eq i8 %0, 0
  br i1 %cmp16, label %for.end, label %for.body

for.body:                                         ; preds = %entry, %if.end
  %1 = phi i8 [ %3, %if.end ], [ %0, %entry ]
  %ss2.018 = phi i8* [ %incdec.ptr, %if.end ], [ %s2, %entry ]
  %ss1.017 = phi i8* [ %incdec.ptr6, %if.end ], [ %s1, %entry ]
  %2 = load i8, i8* %ss2.018, align 1
  %cmp4 = icmp eq i8 %1, %2
  br i1 %cmp4, label %if.end, label %for.end

if.end:                                           ; preds = %for.body
  %incdec.ptr = getelementptr inbounds i8, i8* %ss2.018, i32 1
  %incdec.ptr6 = getelementptr inbounds i8, i8* %ss1.017, i32 1
  %3 = load i8, i8* %incdec.ptr6, align 1
  %cmp = icmp eq i8 %3, 0
  br i1 %cmp, label %for.end, label %for.body

for.end:                                          ; preds = %if.end, %for.body,
%entry
  %ss2.0.lcssa = phi i8* [ %s2, %entry ], [ %ss2.018, %for.body ], [
%incdec.ptr, %if.end ]
  %.lcssa = phi i8 [ 0, %entry ], [ %1, %for.body ], [ 0, %if.end ]
  %conv7 = zext i8 %.lcssa to i32
  %4 = load i8, i8* %ss2.0.lcssa, align 1
  %conv8 = zext i8 %4 to i32
  %sub = sub nsw i32 %conv7, %conv8
  ret i32 %sub
}

compiled for riscv64 (generic-rv64) emits:

foo:                                    # @foo
        lbu     a2, 0(a0)
        beqz    a2, .LBB0_4
        addi    a0, a0, 1
.LBB0_2:                                # %for.body
        lbu     a3, 0(a1)
        andi    a4, a2, 255
        bne     a4, a3, .LBB0_5
        lbu     a2, 0(a0)
        addi    a1, a1, 1
        addi    a0, a0, 1
        bnez    a2, .LBB0_2
.LBB0_4:
        mv      a2, zero
.LBB0_5:                                # %for.end
        lbu     a0, 0(a1)
        andi    a1, a2, 255
        sub     a0, a1, a0
        ret

Compiled for aarch64 (cortex-a76):

foo:                                    // @foo
        ldrb    w8, [x0]
        cbz     w8, .LBB0_4
        add     x9, x0, #1              // =1
.LBB0_2:                                // %for.body
        ldrb    w10, [x1]
        cmp     w10, w8, uxtb
        b.ne    .LBB0_4
        add     x1, x1, #1              // =1
        ldrb    w8, [x9], #1
        cbnz    w8, .LBB0_2
.LBB0_4:                                // %for.end
        and     w8, w8, #0xff
        ldrb    w9, [x1]
        sub     w0, w8, w9
        ret

Haven't tested with other upstream targets.

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