[llvm-bugs] [Bug 43837] New: [X86][MCA] X86 Models should declare dependency breaking idioms and optimizable register moves

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https://bugs.llvm.org/show_bug.cgi?id=43837

            Bug ID: 43837
           Summary: [X86][MCA] X86 Models should declare dependency
                    breaking idioms and optimizable register moves
           Product: tools
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: llvm-mca
          Assignee: unassignedbugs at nondot.org
          Reporter: andrea.dibiagio at gmail.com
                CC: andrea.dibiagio at gmail.com, llvm-bugs at lists.llvm.org,
                    matthew.davis at sony.com

With the only exception of BtVer2, X86 processor models don't describe
optimizable register moves and dependency breaking idioms for MCA.

In the past, special tablegen classes have been added just for the purpose of
describing optimizable register moves and dependency breaking instructions to
MCA.

MCA knows how to correctly simulate optimizable register moves. However, the
simulation requires explicitly knowledge from the target. At the moment, BtVer2
is the only model which describes optimizable register moves for MCA.

This is how we describe optimizable register movess in BtVer2:

```
def : IsOptimizableRegisterMove<[
  InstructionEquivalenceClass<[
    // GPR variants.
    MOV32rr, MOV64rr,

    // MMX variants.
    MMX_MOVQ64rr,

    // SSE variants.
    MOVAPSrr, MOVUPSrr,
    MOVAPDrr, MOVUPDrr,
    MOVDQArr, MOVDQUrr,

    // AVX variants.
    VMOVAPSrr, VMOVUPSrr,
    VMOVAPDrr, VMOVUPDrr,
    VMOVDQArr, VMOVDQUrr
  ], TruePred >
]>;
```

Models can further constraint register renaming via tablegen class
RegisterFile. In particular, models can limit how often move elimiation occurs
during a single cycle. On BtVer2, move elimination is only enabled for known
zero registers (i.e. registers previously cleared by a zero idiom).


--

Tablegen class `IsZeroIdiomFunction` and `IsDepBreakingFunction` can be
instantiated by scheduling models that want to teach to MCA how to identify
zero-idioms and known dependency-breaking idioms.

Currently these definitions are only present in the BtVer2 model.


Example of AVX zero-idioms on BtVer2 (Code snippet taken from
X86ScheduleBtver2.td):


```
def : IsZeroIdiomFunction<[
  // AVX Zero-idioms.
  DepBreakingClass<[
    // xmm fp variants.
    VXORPSrr, VXORPDrr, VANDNPSrr, VANDNPDrr,

    // xmm int variants.
    VPXORrr, VPANDNrr,
    VPSUBBrr, VPSUBWrr, VPSUBDrr, VPSUBQrr,
    VPSUBSBrr, VPSUBSWrr, VPSUBUSBrr, VPSUBUSWrr,
    VPCMPGTBrr, VPCMPGTWrr, VPCMPGTDrr, VPCMPGTQrr,

    // ymm variants.
    VXORPSYrr, VXORPDYrr, VANDNPSYrr, VANDNPDYrr
  ], ZeroIdiomPredicate>
]>;
```

The issue with the absence of knowledge about optimizable register moves was
recently raised in a code review upstream: https://reviews.llvm.org/D67875


As I previously wrote, there is already a framework in MCA/tablegen to describe
optimizable register moves and dependency breaking instructions. However, none
of the upstream X86 models currently use it except for BtVer2.

So this bug is essentially about describing those idioms/register move
optimizations on other X86 processors.

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