[llvm-bugs] [Bug 44327] New: @sdiv3 and @sdiv5 tests in test/Transforms/InstCombine/exact.ll are miscompiles for undef

via llvm-bugs llvm-bugs at lists.llvm.org
Tue Dec 17 14:45:26 PST 2019


https://bugs.llvm.org/show_bug.cgi?id=44327

            Bug ID: 44327
           Summary: @sdiv3 and @sdiv5 tests in
                    test/Transforms/InstCombine/exact.ll are miscompiles
                    for undef
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Scalar Optimizations
          Assignee: unassignedbugs at nondot.org
          Reporter: lebedev.ri at gmail.com
                CC: llvm-bugs at lists.llvm.org

Noticed accidentally when looking at https://reviews.llvm.org/D71568 and trying
to ensure that the baseline udiv-by-select tests aren't miscompiles also.

----------------------------------------
define i32 @sdiv3(i32 %x) {
%0:
  %y = sdiv i32 %x, 3
  %z = mul i32 %y, 3
  ret i32 %z
}
=>
define i32 @sdiv3(i32 %x) {
%0:
  %1 = srem i32 %x, 3
  %z = sub i32 %x, %1
  ret i32 %z
}
Transformation doesn't verify!
ERROR: Value mismatch

Example:
i32 %x = undef

Source:
i32 %y = #x00000000 (0) [based on undef value]
i32 %z = #x00000000 (0)

Target:
i32 %1 = #x00000000 (0)
i32 %z = #x00010000 (65536)
Source value: #x00000000 (0)
Target value: #x00010000 (65536)

----------------------------------------
define i32 @sdiv5(i32 %x) {
%0:
  %y = sdiv i32 %x, 3
  %z = mul i32 %y, 4294967293
  ret i32 %z
}
=>
define i32 @sdiv5(i32 %x) {
%0:
  %1 = srem i32 %x, 3
  %z = sub i32 %1, %x
  ret i32 %z
}
Transformation doesn't verify!
ERROR: Value mismatch

Example:
i32 %x = undef

Source:
i32 %y = #x00000000 (0) [based on undef value]
i32 %z = #x00000000 (0)

Target:
i32 %1 = #x00000000 (0)
i32 %z = #x10000000 (268435456)
Source value: #x00000000 (0)
Target value: #x10000000 (268435456)

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