[llvm-bugs] [Bug 37461] New: shr + and -> shr optimisation seems to prevent rotation instructions from being generated

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=37461

            Bug ID: 37461
           Summary: shr + and -> shr optimisation seems to prevent
                    rotation instructions from being generated
           Product: libraries
           Version: 4.0
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: X86
          Assignee: unassignedbugs at nondot.org
          Reporter: simonas+llvm.org at kazlauskas.me
                CC: llvm-bugs at lists.llvm.org

Reading
https://www.reddit.com/r/rust/comments/8jeybi/rust_does_not_rotate_or_rather_llvm/
and testing around I’ve noticed that while LLVM does not generate a rotation
instruction for the most simple case extracted from the post
(https://paste.rs/jZ4) or when the RHS of the rotate operation is wrapped to
the bit-width of the LHS (https://paste.rs/3XG), but will happily generate a
`ror` instruction if the RHS` is wrapped down to the previous power-of-two
(https://paste.rs/OHC).

Upon the first inspection it seems that the issue stems from the fact that `%y
= lshr i64 %x, 59` optimises out the `and %y, 31`, because the `and` is a no-op
(obviously), and later the isel for `ror` is unable to figure whether it is
able generate `ror` here?

The hypothesis seems to be confirmed by the fact that https://paste.rs/Czx
generates `ror` just fine.

This is not a problem with e.g. the ARM backend.

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