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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - shr + and -> shr optimisation seems to prevent rotation instructions from being generated"
href="https://bugs.llvm.org/show_bug.cgi?id=37461">37461</a>
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<th>Summary</th>
<td>shr + and -> shr optimisation seems to prevent rotation instructions from being generated
</td>
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<th>Product</th>
<td>libraries
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<th>Version</th>
<td>4.0
</td>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>Linux
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>enhancement
</td>
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Backend: X86
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
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<th>Reporter</th>
<td>simonas+llvm.org@kazlauskas.me
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<th>CC</th>
<td>llvm-bugs@lists.llvm.org
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<p>
<div>
<pre>Reading
<a href="https://www.reddit.com/r/rust/comments/8jeybi/rust_does_not_rotate_or_rather_llvm/">https://www.reddit.com/r/rust/comments/8jeybi/rust_does_not_rotate_or_rather_llvm/</a>
and testing around I’ve noticed that while LLVM does not generate a rotation
instruction for the most simple case extracted from the post
(<a href="https://paste.rs/jZ4">https://paste.rs/jZ4</a>) or when the RHS of the rotate operation is wrapped to
the bit-width of the LHS (<a href="https://paste.rs/3XG">https://paste.rs/3XG</a>), but will happily generate a
`ror` instruction if the RHS` is wrapped down to the previous power-of-two
(<a href="https://paste.rs/OHC">https://paste.rs/OHC</a>).
Upon the first inspection it seems that the issue stems from the fact that `%y
= lshr i64 %x, 59` optimises out the `and %y, 31`, because the `and` is a no-op
(obviously), and later the isel for `ror` is unable to figure whether it is
able generate `ror` here?
The hypothesis seems to be confirmed by the fact that <a href="https://paste.rs/Czx">https://paste.rs/Czx</a>
generates `ror` just fine.
This is not a problem with e.g. the ARM backend.</pre>
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