[llvm-bugs] [Bug 35837] New: [X86] Assembler for vcvtsd2sil (%rax), %ebx favors EVEX encoding even though there's nothing requiring EVEX

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https://bugs.llvm.org/show_bug.cgi?id=35837

            Bug ID: 35837
           Summary: [X86] Assembler for vcvtsd2sil (%rax), %ebx favors
                    EVEX encoding even though there's nothing requiring
                    EVEX
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: X86
          Assignee: unassignedbugs at nondot.org
          Reporter: craig.topper at gmail.com
                CC: llvm-bugs at lists.llvm.org

The assembler matching table is incorrectly biasing towards EVEX instructions
for any instruction that doesn't use a VR128X/VR256X/FR32X/FR64X register
class.

This is because the HasAVX512 assembler predicate is forcing it to have a
higher priority. Most instructions don't have this issue because
VR128/VR256/FR32/FR64 register classes are given priority over their X
counterparts regardless of assembler predicate.

Currently unsure how to fix this short of marking all the ambiguous
instructions "CodeGenOnly = 1, ForceDisassemble = 1". This will hide them from
the asm matcher table.

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