[llvm-bugs] [Bug 34733] New: Moffs operands are not encoded
llvm-bugs at lists.llvm.org
Tue Sep 26 02:43:14 PDT 2017
Bug ID: 34733
Summary: Moffs operands are not encoded
Component: Backend: X86
Assignee: unassignedbugs at nondot.org
Reporter: kadircetinkaya.06.tr at gmail.com
CC: llvm-bugs at lists.llvm.org
LLVM is not able to generate instructions with moffs operands, when I try to
mov al, [0x01]
with llvm-mc it generates encoding, [0x8a,0x04,0x25,0x01,0x00,0x00,0x00] which
is an instruction that actually uses full modr/m and sib. Which should decode
into mov al, byte ptr [0x01].
It should've generated "\xa0\x01\x00\x00\x00\x00\x00\x00\x00". As mentioned in
page 45 of Intel SDM, Instruction Set Reference, July 2017.
18.104.22.168 Direct Memory-Offset MOVs
In 64-bit mode, direct memory-offset forms of the MOV instruction are extended
to specify a 64-bit immediate absolute address. This address is called a
moffset. No prefix is needed to specify this 64-bit memory offset. For these
MOV instructions, the size of the memory offset follows the address-size
default (64 bits in 64-bit mode). See Table 2-6.
this assembler manages to do it even tough they are using Keystone and
Capstone. May be it was correct in previous versions, and got broken in a later
You are receiving this mail because:
You are on the CC list for the bug.
-------------- next part --------------
An HTML attachment was scrubbed...
More information about the llvm-bugs