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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - Moffs operands are not encoded"
href="https://bugs.llvm.org/show_bug.cgi?id=34733">34733</a>
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<th>Summary</th>
<td>Moffs operands are not encoded
</td>
</tr>
<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
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<th>Version</th>
<td>4.0
</td>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>Linux
</td>
</tr>
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>enhancement
</td>
</tr>
<tr>
<th>Priority</th>
<td>P
</td>
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<th>Component</th>
<td>Backend: X86
</td>
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
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<th>Reporter</th>
<td>kadircetinkaya.06.tr@gmail.com
</td>
</tr>
<tr>
<th>CC</th>
<td>llvm-bugs@lists.llvm.org
</td>
</tr></table>
<p>
<div>
<pre>LLVM is not able to generate instructions with moffs operands, when I try to
assemble
mov al, [0x01]
with llvm-mc it generates encoding, [0x8a,0x04,0x25,0x01,0x00,0x00,0x00] which
is an instruction that actually uses full modr/m and sib. Which should decode
into mov al, byte ptr [0x01].
It should've generated "\xa0\x01\x00\x00\x00\x00\x00\x00\x00". As mentioned in
page 45 of Intel SDM, Instruction Set Reference, July 2017.
"
2.2.1.4 Direct Memory-Offset MOVs
In 64-bit mode, direct memory-offset forms of the MOV instruction are extended
to specify a 64-bit immediate absolute address. This address is called a
moffset. No prefix is needed to specify this 64-bit memory offset. For these
MOV instructions, the size of the memory offset follows the address-size
default (64 bits in 64-bit mode). See Table 2-6.
"
Somehow,
<a href="http://shell-storm.org/online/Online-Assembler-and-Disassembler/?inst=mov+al%2C+%5B0x01%5D&arch=x86-64#assembly">http://shell-storm.org/online/Online-Assembler-and-Disassembler/?inst=mov+al%2C+%5B0x01%5D&arch=x86-64#assembly</a>
this assembler manages to do it even tough they are using Keystone and
Capstone. May be it was correct in previous versions, and got broken in a later
release?</pre>
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