[llvm-bugs] [Bug 34478] New: MOV16ms uses operand size override prefix
llvm-bugs at lists.llvm.org
Tue Sep 5 08:06:51 PDT 2017
Bug ID: 34478
Summary: MOV16ms uses operand size override prefix
Component: Backend: X86
Assignee: unassignedbugs at nondot.org
Reporter: kadircetinkaya.06.tr at gmail.com
CC: llvm-bugs at lists.llvm.org
When assembling an instruction like
movw %fs, (%rsi)
LLVM encodes with:
66 8c 26 mov %fs,(%rsi)
which adds operand size override prefix whereas gcc doesn't append 66 and
encodes the instruction as:
8c 26 mov %fs,(%rsi)
Intel defines the behavior of the instruction on page 694 of Instruction Set
Reference, July 2017 and it doesn't provide detailed information for that case,
but I feel like using only the least 16 bits of an address might cause problems
in 64 bit mode.
Do we know if it is a bug or X86InstrSystem.td contains OpSize16 for MOV16ms on
a specific purpose?
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