[llvm-bugs] [Bug 34819] New: [ARM] machine verifier fails after Machine Peephole pass

via llvm-bugs llvm-bugs at lists.llvm.org
Tue Oct 3 12:48:02 PDT 2017


            Bug ID: 34819
           Summary: [ARM] machine verifier fails after Machine Peephole
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: ARM
          Assignee: unassignedbugs at nondot.org
          Reporter: gberry at codeaurora.org
                CC: llvm-bugs at lists.llvm.org

The following IR:

define i32 @foo(i32 %m, i32 %pre, i32 %v) {
  %mul = mul nsw i32 %pre, %m
  %add = add i32 %v, -1
  %cmp = icmp slt i32 %v, 2
  %sub = select i1 %cmp, i32 0, i32 %add
  %mul.sub = add i32 %mul, %sub
  ret i32 %mul.sub

when compiled with llc hits a machine verifier error:

$ llc -mtriple armv7-linux-gnueabi  -mcpu cortex-a15  -verify-machineinstrs

# After Peephole Optimizations
# Machine code for function foo: IsSSA, TracksLiveness
Function Live Ins: %R0 in %vreg0, %R1 in %vreg1, %R2 in %vreg2

BB#0: derived from LLVM BB %entry
    Live Ins: %R0 %R1 %R2
        %vreg2<def> = COPY %R2; GPRnopc:%vreg2
        %vreg1<def> = COPY %R1; GPRnopc:%vreg1
        %vreg0<def> = COPY %R0; GPRnopc:%vreg0
        %vreg3<def> = MLA %vreg1, %vreg0, %vreg2, pred:14, pred:%noreg,
opt:%noreg; GPRnopc:%vreg3,%vreg1,%vreg0,%vreg2
        %vreg5<def> = SUBri %vreg3<kill>, 1, pred:14, pred:%noreg, opt:%noreg;
GPR:%vreg5 GPRnopc:%vreg3
        CMPri %vreg2, 2, pred:14, pred:%noreg, %CPSR<imp-def>; GPRnopc:%vreg2
        %vreg6<def,tied6> = MUL %vreg1, %vreg0, pred:11, pred:%CPSR,
opt:%noreg, %vreg5<imp-use,tied0>; GPR:%vreg6,%vreg5 GPRnopc:%vreg1,%vreg0
        %R0<def> = COPY %vreg6; GPR:%vreg6
        BX_RET pred:14, pred:%noreg, %R0<imp-use>

# End machine code for function foo.

*** Bad machine code: Illegal virtual register for instruction ***
- function:    foo
- basic block: BB#0 entry (0x5189518)
- instruction: %vreg6<def,tied6> = MUL
- operand 0:   %vreg6<def,tied6>
Expected a GPRnopc register, but got a GPR register

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