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<base href="https://bugs.llvm.org/">
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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [ARM] machine verifier fails after Machine Peephole pass"
href="https://bugs.llvm.org/show_bug.cgi?id=34819">34819</a>
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<th>Summary</th>
<td>[ARM] machine verifier fails after Machine Peephole pass
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<th>Product</th>
<td>libraries
</td>
</tr>
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<th>Version</th>
<td>trunk
</td>
</tr>
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<th>Hardware</th>
<td>PC
</td>
</tr>
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<th>OS</th>
<td>Windows NT
</td>
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<th>Status</th>
<td>NEW
</td>
</tr>
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<th>Severity</th>
<td>enhancement
</td>
</tr>
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Backend: ARM
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>gberry@codeaurora.org
</td>
</tr>
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<th>CC</th>
<td>llvm-bugs@lists.llvm.org
</td>
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<pre>The following IR:
define i32 @foo(i32 %m, i32 %pre, i32 %v) {
entry:
%mul = mul nsw i32 %pre, %m
%add = add i32 %v, -1
%cmp = icmp slt i32 %v, 2
%sub = select i1 %cmp, i32 0, i32 %add
%mul.sub = add i32 %mul, %sub
ret i32 %mul.sub
}
when compiled with llc hits a machine verifier error:
$ llc -mtriple armv7-linux-gnueabi -mcpu cortex-a15 -verify-machineinstrs
foo.ll
# After Peephole Optimizations
# Machine code for function foo: IsSSA, TracksLiveness
Function Live Ins: %R0 in %vreg0, %R1 in %vreg1, %R2 in %vreg2
BB#0: derived from LLVM BB %entry
Live Ins: %R0 %R1 %R2
%vreg2<def> = COPY %R2; GPRnopc:%vreg2
%vreg1<def> = COPY %R1; GPRnopc:%vreg1
%vreg0<def> = COPY %R0; GPRnopc:%vreg0
%vreg3<def> = MLA %vreg1, %vreg0, %vreg2, pred:14, pred:%noreg,
opt:%noreg; GPRnopc:%vreg3,%vreg1,%vreg0,%vreg2
%vreg5<def> = SUBri %vreg3<kill>, 1, pred:14, pred:%noreg, opt:%noreg;
GPR:%vreg5 GPRnopc:%vreg3
CMPri %vreg2, 2, pred:14, pred:%noreg, %CPSR<imp-def>; GPRnopc:%vreg2
%vreg6<def,tied6> = MUL %vreg1, %vreg0, pred:11, pred:%CPSR,
opt:%noreg, %vreg5<imp-use,tied0>; GPR:%vreg6,%vreg5 GPRnopc:%vreg1,%vreg0
%R0<def> = COPY %vreg6; GPR:%vreg6
BX_RET pred:14, pred:%noreg, %R0<imp-use>
# End machine code for function foo.
*** Bad machine code: Illegal virtual register for instruction ***
- function: foo
- basic block: BB#0 entry (0x5189518)
- instruction: %vreg6<def,tied6> = MUL
- operand 0: %vreg6<def,tied6>
Expected a GPRnopc register, but got a GPR register</pre>
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