[llvm-bugs] [Bug 32940] New: Failure to recognise consecutive load chain from i64 types on 32-bit target

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=32940

            Bug ID: 32940
           Summary: Failure to recognise consecutive load chain from i64
                    types on 32-bit target
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: X86
          Assignee: unassignedbugs at nondot.org
          Reporter: llvm-dev at redking.me.uk
                CC: llvm-bugs at lists.llvm.org

llc -mtriple=i686-unknown -mcpu=btver2

define <2 x i64> @test_buildvector_v2i64(i64 %a0, i64 %a1) {
  %ins0 = insertelement <2 x i64> undef, i64 %a0, i32 0
  %ins1 = insertelement <2 x i64> %ins0, i64 %a1, i32 1
  ret <2 x i64> %ins1
}

test_buildvector_v2i64:
        vmovd   4(%esp), %xmm0          # xmm0 = mem[0],zero,zero,zero
        vpinsrd $1, 8(%esp), %xmm0, %xmm0
        vpinsrd $2, 12(%esp), %xmm0, %xmm0
        vpinsrd $3, 16(%esp), %xmm0, %xmm0
        retl

Despite being consecutive 4-byte loads, EltsFromConsecutiveLoads /
SelectionDAG::areNonVolatileConsecutiveLoads fails to recognise this.

It appears to be because 

  vpinsrd       $3, 16(%esp), %xmm0, %xmm0

is offset from 

  vpinsrd       $2, 12(%esp), %xmm0, %xmm0

while the other 2 loads are offset from

  vmovd 4(%esp), %xmm0

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