[llvm-bugs] [Bug 35713] New: [X86] VPERMW assigned to wrong port in SKX sheduler model

via llvm-bugs llvm-bugs at lists.llvm.org
Wed Dec 20 22:55:43 PST 2017


            Bug ID: 35713
           Summary: [X86] VPERMW assigned to wrong port in SKX sheduler
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: X86
          Assignee: unassignedbugs at nondot.org
          Reporter: craig.topper at gmail.com
                CC: llvm-bugs at lists.llvm.org

I would be very surprised if VPERMW is on port0. Seems more likely on port5
like every other shuffle. The memory form is using port23 and port5 in the
scheduler model.

def SKXWriteResGroup72 : SchedWriteRes<[SKXPort0]> {
  let Latency = 6;
  let NumMicroOps = 2;
  let ResourceCycles = [2];
def: InstRW<[SKXWriteResGroup72], (instregex "VPERMWZ128rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup72], (instregex "VPERMWZ256rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup72], (instregex "VPERMWZrr(b?)(k?)(z?)")>;

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